JPH01154659A - Plural cable communication system - Google Patents

Abstract

PURPOSE:To realize a high speed circuit by distributing the information of plural consecutive bits at every plural circuit lines and sending it in parallel. CONSTITUTION:When a 1-byte data is written to a transmission shift register 30 from a memory 11, the written data is shifted one by one bit at every clock supplied from a clock generating circuit 28. Simultaneously, communication lines 31-38 are switched sequentially at the interval of clocks supplied from the clock generating circuit 28 by a line scanning circuit 27. Thus, the shifted data is distributed one by one bit to the communication lines 31-38 and sent in parallel. On the other hand, the shift of a reception shift register 29 and the scan of the communication lines 31-38 by the line scan circuit 27 are implemented similarly at the reception and one byte data is formed at every scan of the communication lines 31-38.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer system for communication lines, and particularly to a double-wire cable communication system having a plurality of communication lines.

[Conventional technology]

Conventional communication lines can only connect one communication path with a single wire.

[Problem that the invention seeks to solve]

With the conventional communication lines mentioned above, data could only be transmitted in series, so even if high-speed communication was attempted, it would depend on the transfer capacity of one communication line and could not further increase the speed.

[Means for solving problems]

The double-wire cable communication system according to the present invention includes a plurality of communication lines, a means for distributing consecutive plural bits of information for each communication line, and a means for distributing information distributed to the plurality of communication lines in parallel in one line scan. means for transmitting, means for receiving a single information bit for each of the plurality of communication lines during one line scan, and means for collecting the single information bit received for each of the plurality of communication lines. are doing.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 2, in one embodiment of the present invention, a communication control device 1 and a terminal device 2 are connected via a line termination device 4.5 and a digital exchange 3 by a double-wire communication cable 6.

Referring to FIG. 1, the communication control device 1 includes a processor 1
0, memory 11, data read register 21, data write register 22, command register 23,
A report register 24, a memory transfer control circuit 25, a state control circuit 26, a 9-line scan circuit 27, and a clock generation circuit 28.

It is composed of a reception shift register 29 and a transmission shift register 30.

The transmission shift register 30 connects the communication line 3 to the line termination device 4.
They are connected from 1 to 38.

When transmitting data from the communication control device 1 to the terminal device 2, the processor 10 sends an instruction to transmit the data stored in the memory 11 to the state control circuit 26 via the command register 23.
give to The state control circuit 26 is the memory transfer control circuit 25
The memory address fetched from the command register 23 is given to the memory transfer control circuit 25, and the data in the shift memory 11 is written into the data read register 21 one byte at a time. The data held in the data read register 21 is immediately transferred to the transmission shift register 30.

The line scan circuit 27 sequentially switches communication lines 31 to 38 at clock intervals of the clock generation circuit 28. The clock generation circuit 28 supplies the same clock given to the line scan circuit 27 to the transmission shift register 30, and shifts the data stored in the transmission shift register 30 one bit at a time for each clock.

The shifted out 1-bit data is sent to line scan circuit 2.
Send it on the communication line switched in step 7. Data is transmitted in parallel to nine communication lines 31 to 38 by switching communication lines 31 to 38 every time one pit shift is performed. When one line scan from the communication lines 31 to 38 is completed, the single line scan circuit 27 notifies the memory transfer control circuit 25 of the completion of the scan and takes in the secondary data from the memory 11 again. When the transmission operation for the data transfer length specified by the command register 23 is completed, the state control circuit 26 writes report information of transmission completion to the report register 24 in order to notify the processor 10 of the completion of transmission. - Next, when receiving data from the terminal device 2, the processor 10 provides a memory storage address and a data reception instruction to the state control circuit 26 via the command register 23. The line scan circuit 27 scans the communication lines 31 to 38 at the clock interval of the clock generation circuit 28, and supplies the same clock applied to the clock generation circuit 28I/i line scan circuit 27 to the reception shift register 29. The reception shift register 29 shifts one bit at a time for each clock to form one byte of data for each scan of one communication line 31 to 38. When one line scan from the communication lines 31 to 38 is completed, the line scan circuit 27 notifies the memory transfer control circuit 25 of the completion of the scan. The memory transfer control circuit 25 transfers the received data of the reception shift register 29 to the data write register 22, transfers the data from the data write register 22 to the memory 11, and updates the memory storage address. To complete the reception, the state control circuit 26 writes reception completion information to the report register 24, and the processor 1
This is done by notifying 0.

〔Effect of the invention〕

As explained above, the present invention has the effect of increasing the speed of one communication by treating a plurality of communication lines as one communication path.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the communication control device shown in FIG. 2 that implements the multiple cable communication system according to an embodiment of the present invention, and FIG. 1 is a block diagram showing the overall configuration of a communication system. l... Communication control device, 2... Terminal device, 3... Digital exchange, 4, 5... Line termination device, 6...
Multiple communication cables, 10... processors, 11...
memory. 21...Data read register, 22...Data write register, 23...Command register, 24...
・Report register, 25...Memory transfer control circuit, 26
... State control circuit, 27 ... Line scan circuit, 2
8... Clock generation circuit, 29... Reception shift register. 30...Transmission shift register.

Claims (1)

[Claims] 1. a plurality of communication lines, a means for distributing a plurality of continuous bits of information to each of the communication lines, a means for transmitting the information distributed to the plurality of communication lines in parallel in one line scan; A double-line cable comprising: means for receiving a single information bit for each of the plurality of communication lines during line scanning; and means for collecting the single information bit received for each of the plurality of communication lines. Communication method.