JPH01154483U - - Google Patents
Info
- Publication number
- JPH01154483U JPH01154483U JP5058788U JP5058788U JPH01154483U JP H01154483 U JPH01154483 U JP H01154483U JP 5058788 U JP5058788 U JP 5058788U JP 5058788 U JP5058788 U JP 5058788U JP H01154483 U JPH01154483 U JP H01154483U
- Authority
- JP
- Japan
- Prior art keywords
- transistor
- control section
- pseudo
- input side
- error input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Logic Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5058788U JPH01154483U (en:Method) | 1988-04-15 | 1988-04-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5058788U JPH01154483U (en:Method) | 1988-04-15 | 1988-04-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01154483U true JPH01154483U (en:Method) | 1989-10-24 |
Family
ID=31276625
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5058788U Pending JPH01154483U (en:Method) | 1988-04-15 | 1988-04-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01154483U (en:Method) |
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1988
- 1988-04-15 JP JP5058788U patent/JPH01154483U/ja active Pending