JPH01152820A - A/d conversion circuit - Google Patents

Abstract

PURPOSE:To vary optionally the accuracy of A/D conversion in the combination with the A/D conversion time by providing a means selecting an optional signal from plural conversion accuracy selection signals and using the selection means to control a controller. CONSTITUTION:Plural conversion accuracy selection signal terminals 3 and a decoder 5 receiving a selection signal from the terminals are added to a conventional circuit. A selection signal from the conversion accuracy selection signal terminal 3 is decoded by the decoder 5 to control the controller 9. When the result of A/D conversion of an SAR 10 is selected by an output of the decoder 5 and reaches the selected conversion accuracy, the controller 9 controls the SAR 10 to complete the A/D conversion to output the result of A/D conversion. Moreover, an ADCR 11 latches the result of A/D conversion outputted from the SAR 10 to output a digital output value 15. A selection signal from the conversion accuracy selection signal terminal 3 is varied optionally, then the A/D conversion accuracy and the A/D conversion time are selected optionally by switching the conversion selection signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an A/D conversion circuit, and more particularly to an A/D conversion circuit that performs successive conversion on an analog input.

[Conventional technology]

Conventionally, successive conversion type A/D conversion circuits (hereinafter referred to as A/D converters) have high A/D conversion accuracy. - It is fixed at a location and A/D conversion is performed.

FIG. 3 is an A/D converter circuit diagram for explaining an example of such a conventional method.

As shown in FIG. 3, the A/D converter includes a selector 4 that selects a signal from an analog input terminal 1 with a signal from an input selection signal terminal 2, a sampling switch 6 that switches the output of this selector 4, An analog input voltage holding capacitor 7, a comparator 8 that compares the output of the selector 4 and the output of the tap decoder 12, and an A/D
A conversion controller 9, a successive approximation register (hereinafter referred to as SAR) 10 that latches the output of the comparator 8 under the control of this controller 9, and latches the final conversion result from this 8A810 and outputs a digital output value 15. A/D conversion result register (hereinafter referred to as ADCR) l
l, the tap decoder 12 mentioned above, and an analog power supply (
(hereinafter referred to as vAnef) 14 and a ladder resistor 13 connected between the ground and ground. The circuit operation of the A/D converter having such a configuration will be explained below.

The potential of the analog input terminal l (hereinafter referred to as VAn) is selected by the selector 4 in accordance with the selection signal 2, and the result sampled by the sampling switch 6 is held in the capacitor 7. In addition, the comparator 8 is connected to the ladder resistor 13 and V
The reference potential (hereinafter referred to as vRe) generated by the voltage from the ARef terminal 14 and selected by 5ARIO and the tap decoder 12
f) and the analog input potential VAn held in the capacitor 7 described above, and the comparison result is expressed as 8AR.
Output to 10. This 8AR10 latches the comparison result of the comparator 8, controls the tap decoder 12 based on the comparison result and the control of the controller 9, and outputs VRef.
'k Iteratively approximates VAn. By repeating this comparison with comparator 8 and successive approximation of VRef, #)SA
The A/D conversion result is latched into RIQ starting from the most significant bit. When the conversion is completed to the lowest and t, the 8AR10 converts the A/D conversion result t-AD under the control of the controller 9.
Output to CRll.

This ADCRII latches the A/D conversion result and outputs a digital output value of 15.

[Problem that the invention seeks to solve]

Therefore, even if the above-mentioned A/D conversion circuit repeats comparison, approximation, and latching in this way, the A/D conversion accuracy remains constant.
), there is a drawback that only a constant υλ/D conversion time can be obtained unless the frequency of the clock controlling the A/D converter is changed.

An object of the present invention is to provide an entire A/D conversion circuit that can vary the A/D conversion accuracy in combination with t-A/D conversion time.

[Means for solving problems]

The present invention comprises a selector that selects an analog input signal, a comparator that samples the selector output and compares the held analog input potential with a reference potential, a successive approximation register that reads the output of this comparator, and In an A/D converter having an A/D conversion result register as a successive approximation register, a controller for controlling the successive approximation register, a tap decoder and a ladder resistor for creating the reference potential, a plurality of conversion accuracy selection signals are provided. 9 by providing means for selecting an arbitrary signal from 9 and controlling the controller by this selection means.
It is configured to arbitrarily select the A/D conversion precision.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the OA/D for explaining the first embodiment of the present invention.
FIG. 3 is a converter circuit diagram.

As shown in FIG. 1, in addition to the conventional circuit explained in FIG. 3, the A/D converter circuit of this embodiment has a plurality of conversion accuracy selection signal terminals 3 and input selection signals from these terminals. A decoder 5 is provided, and a controller 9 is controlled by the output of the decoder 5. still,
Components with the same numbers as those shown in FIG. 3 use the same circuits.

Next, the circuit operation of this A/D converter will be explained.

The potential vAfi applied to the analog input terminal 1 is selected by the selector 4 according to a selection signal from the input selection signal terminal 2, and the result sampled by the sampling switch 6 is held in the hold capacitor 7. Further, the comparator 8 uses the analog input potential VAn held in the capacitor 7 as one comparison potential, and the ladder resistor 13 and VAn.
Generated from the power supply potential from the Re f terminal 14 and at 8A
Vne selected by R10 and tap decoder 12
t - Successive comparison is performed as the other comparison potential, and the comparison results are sequentially output to 5ARIO. This 8A output is controlled by the tap decoder 12t based on the output of the comparator 8 and the control of the controller 9.
f is successively approximated to VAn, and the A/D conversion results are sequentially applied from 1 to 3 until the end of the conversion. On the other hand, the selection signal from the conversion accuracy selection signal terminal 3 is decoded by the decoder 5 and controls the controller 9.

When the A/D conversion result of 8 A/D reaches the conversion accuracy selected by the output of the decoder 5, the controller 9
Controls R1O to complete the A/D conversion and output the A/D conversion result. In addition, the human DCR 11 reads the A/D conversion result output from the 5ARIO and outputs a digital output value of 1.
Outputs 5.

Since the selection signal from the conversion accuracy selection signal terminal 3 mentioned above can be changed arbitrarily, the fi A/D conversion accuracy and A/D conversion time can be arbitrarily selected by switching the conversion accuracy selection signal. .

For example, sampling [36 μs, successive approximation 36 μs
Consider an 8-bit precision A/D converter that requires 36 μs to output the A/D conversion result. In this case, the A/D conversion time for 8-bit precision A/D conversion is 360 μs, whereas when the A/D conversion precision is set to 6-bit precision and 4-bit precision, the A/D conversion time is 288 μs for each. and can be shortened to 216 μs.

FIG. 2 is an A/D for explaining the second embodiment of the present invention.
FIG. 3 is a converter circuit diagram.

As shown in FIG. 2, the difference between this embodiment and the first embodiment described above is that a selector 16 similar to the selector 4 is used instead of the decoder 5, and that the number of conversion accuracy selection signal terminals 3 is reduced. Selector 16 input selection signal terminal 2
It was used for selection control. The other circuits are the same as the circuits with the same numbers shown in FIGS. 1 and 3. below,
The circuit operation of such an A/D converter will be explained.

The plurality of analog input potentials VAn of the analog input terminal 1 are selected by the selector 4 by a selection signal from the input selection signal terminal 2.
is selected and held in a capacitor 7 via a sampling switch 6. On the other hand, the reference potential V of the comparator 8
Ref is generated by seven power sources Ref from the ladder resistor 13 and the power supply terminal 14, and is selected by the 8AR 10 and the evening/tube decoder 12. Further, as in the first embodiment described above, the comparator 8 performs a successive comparison between VAn and VRaf, and latches the comparison result at t-8AR10.

1[K, 8 A R10c VRef 't' vAn
K successive approximation is performed and the A/D conversion results are output in order from the most significant bit until the conversion is completed.

On the other hand, the conversion accuracy selection signal 3 is selected by one selector 16 according to the selection signal from the analog input selection signal terminal 2, but each conversion accuracy selection signal corresponds to the input signal from the analog input terminal 1.夛、Analog input terminal 1
The conversion precision is arbitrarily selected for each. Further, when the A/D conversion result of 5ARIO reaches the conversion accuracy selected by the output of the selector 5, the controller 9 controls the 8A converter 10 to finish the A/D conversion, and transfers the A/D conversion result to ADCRll. Output. This ADCRII is 5AR
The output of IO is cleared and output as digital output value 15.

With this configuration, each selection signal from the conversion accuracy selection signal terminal 3 corresponds to the analog input terminal l, so the A/D conversion accuracy and A/D conversion time can be adjusted for each analog input terminal. It becomes possible to set it arbitrarily.

Two embodiments have been described above, but in short, the present invention has means for arbitrarily selecting the A/D conversion accuracy, so the A/D conversion accuracy and A/D conversion accuracy are always adjusted according to the characteristics of the analog input source. An optimal combination with the D conversion time can be obtained.

〔Effect of the invention〕

As explained above, the A/D converter of the present invention
Since we have provided a means to arbitrarily set the D conversion accuracy,
This has the advantage that it can be set arbitrarily according to the electrical characteristics of the analog input source and the purpose of A/D conversion, which solves the problem of how high the A/D conversion accuracy and how short the A/D conversion time is. be.

For example, if the analog input potential changes significantly during A/I conversion time, high conversion accuracy is not required.
For example, if a shorter conversion time is better, the combination of A/L) conversion accuracy and A/D conversion time can be optimized depending on the method of use, and the versatility of the A/L) converter can be increased.

In addition, in cases such as voltage setting and motor control, the A/D
It is possible to reduce the conversion accuracy to shorten the A/D conversion time, while increasing the A/D conversion accuracy as the analog input voltage approaches the set value.

In this way, the A/D converter of the present invention can optimize the combination of A/D conversion accuracy and A/D conversion time depending on the usage method, so it has high versatility, especially when built into a micro converter etc. It is valid.

[Brief explanation of the drawing]

FIG. 1 is an A/D for explaining the first embodiment of the present invention.
FIG. 2 is an A/D conversion circuit diagram for explaining a second embodiment of the present invention, and FIG. 3 is an h/D conversion circuit diagram for explaining a conventional example. l... Analog input terminal, 2... Input selection signal terminal, 3... Conversion accuracy selection signal terminal,
4...-Selector, 5...Decoder,
6...Sampling switch, 7...
・Hold capacitor, 8...Comparator, 9...Controller, 10...8A
R, 11...ADCB, 12...Tag decoder, 13...Ladder resistor, 14...
...V ARa f terminal, 15...Digital output value, 16...Selector. Agent: Patent Attorney Uchihara Onto I Zuman Z Zu

Claims (1)

[Claims] A selector that selects an analog input signal, a comparator that samples the selector output and compares the held analog input potential with a reference potential, a successive approximation register that latches the output of this comparator, and a An A/D conversion result register that latches and digitally outputs the final conversion result, a controller that controls the successive approximation register, and a tap decoder and a ladder resistor that creates the reference potential.
The D conversion circuit is provided with means for selecting an arbitrary signal from a plurality of conversion accuracy selection signals, and the selection means controls the controller to arbitrarily select the A/D conversion accuracy. D conversion circuit.