JPH01149294A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To decrease the charging and discharging current of a bit line by setting the potential of a first voltage supplying route to a prescribed potential and setting one of the pair of the bit lines to the prescribed potential and the other one to a second power source voltage at an amplifying time. CONSTITUTION:The device is inserted to a first voltage supplying route HL and with corresponding to a potential detecting signal, when the potential of the first voltage supplying route HL is out of the neighboring of the prescribed potential, a high speed charging is executed so as to be closed to the prescribed potential by rapidly charging the first voltage supplying route HL. Then, when the potential of the first voltage supplying route HL is in the neighboring of the prescribed potential, a first power source voltage is shifted down and a voltage is caused to be fall so that the potential of the first voltage supplying route HL can be set to the prescribed potential. Then, the potential of the first voltage supplying route HL is set to the prescribed potential at the high speed. One of the pair of bit lines BL and the inverse of BL is set to the prescribed potential and the other one is set to the second power source voltage level at the amplifying time. Thus, the charging and discharging current of the pair of the bit lines can be decreased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sensing device in which a first power supply voltage and a second power supply voltage are supplied from first and second voltage supply paths in accordance with a first control signal. The present invention relates to a semiconductor memory device that reads information from a memory cell by detecting and amplifying the potential difference between a pair of bit lines using an amplifier.

[Conventional technology]

In recent years, dynamic MO8RAM (hereinafter referred to as [DRAM
It's called J. ), etc., there is a desire for lower power consumption as the integration becomes higher.

In DRAM, the charging time of bit line pair in total current consumption is
The i7a current accounts for a large proportion. Therefore, attempts were made to reduce the charging and discharging current of the bit line pair.

Figure 7 is r l5SCCDTGEST OF TECH
NIC^L PAPERSFeb, 1987 pp, 1
°' A 90nS IIHb described in 2-13J
1 is a circuit diagram showing a memory cell and a sense amplifier periphery, which is a diagram showing the concept of a DRAM disclosed in "DRAM in a 300 mil Dip".

In the figure, a memory cell 1 is composed of a selection transistor QO and a memory capacitor CO, and is connected to a bit line BL and a word line WL via the selection transistor QO.

Reference numeral 2 designates a sense amplifier, which is an n-channel MIS transistor Ql provided between bit lines BL' and BL', and whose source is commonly connected to a connection line LL.

7 lips and 70 tubes are formed from Q2, and the source is connected to the connection line H.
p-channel MIS transistor Q commonly connected to L
3. By configuring seven lip-flops from Q4, the potential difference between bit lines BL' and BL' is detected and one is amplified to the potential of the connection line Lm and the other to the potential of the connection line H[.

The connection line LL is connected to the ground level (“L”) via an n-channel MIS transistor Q5 to whose gate the control signal SO is applied.
'' level, the connection line HL is connected to the power supply voltage V through the p-channel MIS transistor Q6 to which the inverted control signal SO is applied to the gate.

(“HIt level)” and functions as a voltage supply path. Also, Q7 is a bit line pair BL.

Q8. is an n-channel MIS transistor for equalizing the potential of BL. Q9 are bit line pairs BL, BL, respectively.
n channel MI for precharging to potential VBL
S transistors, and these transistors 07 to Q
An equalize signal EQ is applied to the gate of 9.

The bit lines BL and BL', BL and BL' each have a power supply voltage ■ at their gates. They are connected via n-channel MIS transistors QB and Qi to which threshold voltage Vth of 0 is applied. Also, between bit lines BL' and 110, between BL' and 110
0, n-channel MI to which signal Y is applied to each gate.
S transistor Q10. Connected via Qll.

FIG. 8 is a timing diagram showing the read operation of the DRAM shown in FIG. 7. The read operation will be explained below with reference to the same figure.

When the equalize signal EQ falls at time T1, transistors Q7 to Q9 become non-conductive, so that (Vcc-Vth
)/2, the bit line pair BL, BL becomes a floating state.

Then, when the word line WL rises to the "H" level from time T2, the selection transistor QO in the memory cell 1 becomes conductive, the charge accumulated in the memory capacitor CO is transmitted to the bit line BL, and the memory capacitor CO reaches the H11 level. If it is stored, the potential of the bit line 8m rises slightly as shown by the solid line in FIG. This rise is also transmitted to the potential of bit line BL' via transistor Q8.

Then, at time T3, the control signal So (So) is set to “HII”.
By raising (falling) the level (111It level), transistor Q5. Make Q6 conductive and connect the connecting wire LL,
The potential of HL is set to ground level and power supply voltage V, respectively. . Sense amplifier 2 is activated by setting the level. When sense amplifier 2 is activated, a slight potential difference between bit lines BL' and BL' causes transistors Q1. By making Q4 conductive and transistors Q2 and Q3 non-conductive, bit line BL
', and the potential of BL, respectively. . level, amplify to ground level.

The simultaneously amplified potentials of the bit lines BL' and BL' are transmitted to the bit lines BL and BL via the transistors Q and Qi. At this time, the potential of the bit line BL becomes the potential ■ of the bit line BL' via the transistor QB having the threshold voltage ■th. 0 is transmitted, so in reality (Voo-V
th).

Then, at time -4, the signal Y rises to the H' level, transistors Q10 and Qll become conductive, and the potentials of the bit lines BL' and BL' rise to the I10 and Ilo lines.
It is then amplified and output to “H” from the external output terminal.
The level is output.

Then, at time T5, by lowering the word line W[ to the °LIT level, the memory cell 1 and the bit line BL are cut off.At the same time, by lowering the signal Y, the bit line pair BL'
, BL' and l10f line pair 110°110 are cut off.

Then, by raising the signal EQ at time T6, transistors 07 to Q9 are made conductive, and bit line pair BL (BL
) and BL (BL') respectively precharge the internal power supply bit line pair BL, BL (BL', BL'). Note that the portions indicated by dotted lines in the eighth section indicate the waveforms of each signal when the memory capacitor CO stores the "L" level.

In this way, by reducing the maximum amplitude (potential difference) between the bit lines 81 and 31 from the conventional Vcc to (Voc-Vth), the charge/discharge current of the bit line pair BL, BL can be reduced.

Moreover, when the "H" level of the word line WL is V.0,
The "H" level written into the memory cell 1 is hH, where the threshold voltage of the selection transistor QO is 2, and (vCC-vthH), and the read charge is lost by the threshold voltage v1hH. From this, the bit lines BL, B
The precharge potential of L was changed from the conventional vcc/2 to (Voc
-V, , )/2, memory cell 1's “
It also has the effect of increasing the read margin for H" level storage and improving the operating margin. In this case, if the read margin for the "[" level is also taken into consideration, Vth
It is most desirable to set =■thH.

[Problem that the invention seeks to solve]

The conventional ORAM designed to reduce the bit line charging/discharging current is configured as described above, and the bit lines BL', B cannot be equalized by simply turning on the transistor Q7.
The potential difference between L' is V. 0, and the potential of the bit line pair BL, BL cannot be set to (■o.-Vth)/2. Therefore, due to the internal power supply VBL, the bit line pair BL,
BL (BL', BL') (Voo-vth)/
It is necessary to forcibly precharge to 2.

This internal power supply VB is the normal power supply voltage V. The bit line pair BL, BL (BL') is generated by a resistor divider circuit between C and the ground level, but as described above.

In order to forcibly set the potential of BL' to (■Co-Vth)/2, it was necessary to increase the driving capability, and it was not possible to increase the resistance value of the dividing resistor.

As a result, the power supply voltage VCo when the DRAM is not accessed,
There is a problem in that the standby current that flows in a DC manner between the ground levels increases, resulting in increased power consumption.

This invention was made to solve the above-mentioned problems, and its purpose is to provide a semiconductor memory device that reduces bit line charging and discharging current without increasing the amount of standby current. shall be.

[Means for solving problems]

In the semiconductor memory device according to the present invention, the first power supply voltage and the second power supply voltage are supplied from the first and second voltage supply paths respectively according to the first control signal. This is a method of reading information in a memory cell by detecting and amplifying a potential difference, and is activated by a second control signal related to the first control signal, and detects the potential of the first voltage supply path. a potential detecting means for providing an output signal indicating whether the potential is near a predetermined potential obtained by shifting down the first power supply voltage; In response to an output signal, if the potential of the first voltage supply path is outside the vicinity of the predetermined potential, a fast charging mode is provided that approaches the predetermined potential by rapidly charging the first voltage supply path. and if the potential of the first voltage supply path is within the vicinity of the predetermined potential, the first power supply voltage is shifted down to set the potential of the first voltage supply path to the predetermined potential. and means for quickly setting the potential of the first voltage supply path to the predetermined potential by operating a drop function, and the sense amplifier 1n sets one of the bit line pair to the predetermined potential during amplification and sets the other to the predetermined potential. is set to the second power supply voltage level.

[Effect]

The sense amplifier according to the present invention shifts the first power supply voltage of one of the bit line pairs to 1 by voltage drop means during amplification.
- Since the lowered predetermined potential is set to the second power supply voltage level, the potential of the bit line pair can be set to 1/2 of the predetermined potential by connecting both bit line pairs after amplification. Can be done.

〔Example〕

FIG. 1 is a diagram of a DRAM memory cell and a sense amplifier peripheral circuit according to an embodiment of the present invention.

In the figure, memory cell 1. Sense amplifier 2° transistor 05~Q11. W.L., LL., and Ilo.

110, signal EQ, Y, 80. Since So is the same as the conventional example shown in FIG. 7, the explanation will be omitted.

Unlike the conventional example, in order to reduce the maximum amplitude between the bit line pair 81.81, the distance between the bit lines 81.81', 100, BL'
Transistor QB provided between.

Qi has been removed.

Also, transistor Q6. Node "81" on the connection line HL
In the meantime, the n-channel MIS transistor Q has a control signal RS OB applied to its gate. is provided.

Transistor Q. is the conventional transistor Q8 (Q-)
The control signal SOB has the same threshold voltage Vth as the power supply voltage Vth when the transistor Q6 is conductive. 0, and the power supply voltage V is also applied to the drain through the transistor Q6. If 0 is given, node N, 1 . potential (that is, the connection line HL
It functions to shift down the potential of (V oo - V th). In addition, the control signal S OB (V cc+
When set to V th) or higher, the node N)1. ■Power supply voltage. 0 can be connected without voltage drop, and the potential of node N□1 can be connected to the power supply voltage V. It functions to rapidly charge towards C.

The control signal SOB is output by the SOB control circuit 3,
Normally, the potential V is maintained at (V cc + V th) or higher,
After the control signal So (30) is activated, the node N1
1. Immediately before the potential reaches (V,, -V th>), the potential decreases to the ■oo level, and the control signal 5O(So)
This is a signal that becomes (Vo, +Vth) level again at the same time as becomes inactive.

Figure 2 is SOB! 1 is a circuit diagram showing a signal generating section of the i11 circuit 3. FIG. The signal generation part is transistor Q12
．． 013 and capacitors C and C2, an inverted equalization signal EQ is applied to the drain of the transistor Q12, and a power supply voltage V is applied to the gate. . , a capacitor C1 is connected to the source, and a power supply voltage ■ is connected to the drain of the transistor Q13. 61
Node N, which is the source of transistor Q12, is connected to the gate.
A capacitor C2 is connected to one source. Further, signals 3od and Sod, which will be described later, are applied to the capacitors C1 and C2, respectively, and the transistors Q13. A control signal SOB is output from between capacitors 02.

FIG. 3 is a circuit diagram showing a signal Sod generating section, in which p-channel MIS transistors Q16. C17 and n channel M
■S transistors Q18 to Q20 constitute a current mirror type amplifier circuit 4, and transistors 018. C1
The potential of node N5' changes due to the difference in magnitude between the gate voltages of node N5'.

The gate of the transistor 018 is connected to the power supply voltage V. 0 is connected via a transistor Q14°C15 whose drain and gate are common. The threshold voltage of these transistors Q14 and C15 sets the potential of node N3 to (Voo-V, ,
) is set to the following predetermined potential. On the other hand, the potential VH4 of the node N□ is applied to the gate of the transistor Q19.

Also, node N5' between transistors 017 and 019
becomes one input of the AND gate AND1 via the inverter 'c1. The other input of this AND gate ANDl is the control signal so, and its output becomes the signal Sod.

Further, the control signal SOF is applied to the gate of the transistor Q20. This control signal SOF is a signal generated in association with the control signal So, rises earlier than the control signal SO, and falls simultaneously with the control signal SO. FIG. 4 shows the control signals SOF,S.

This is a circuit diagram showing an example of the generation of the control signal SOF. As shown in the figure, the -6 input is directly inputted, the other input is delayed for a predetermined time via an even number of inverter groups I, and is input to the AND gate AND2. By doing so, the control signal SO is generated.

Figure 5 shows the SOB file shown in Figures 2 to 4.
1 is a timing diagram showing the operation of the lt211 circuit. The operation of generating the control signal SOB will be explained below with reference to the same figure.

Equalize signal @EQ rises at time T1. That is, the inverted equalize signal EQ rises to the "H" level. Then, the node N8 is connected via the transistor Q12 (threshold voltage ■12).
The potential of node N8 rises to (Vcc-V12). At this time, the potential of the control signal SOB is VP (more than vcc+vth) due to the capacitive coupling of the capacitor C2 to which the "H" level signal Sod is applied, so the transistor Q13 remains non-conductive.

Then, at time T3', which is a little before time T, the signal SO
When F rises to the "H11" level, transistor Q20 becomes conductive and current mirror amplifier circuit 4 is activated.

Then, at time T3, the control signal SO rises to the "H" level, and one input of the AND gate AND1 becomes "H". However, at this time, the potential VHL of the node NHL
is (Vo, -V th)/2, and Vl, <VH
2, the transistor Q19 is not conductive and the potential of the node N5" maintains the "H" level. Therefore, the potential of the node N5 via the inverter c1, that is, the other input of the AND gate ANDI, maintains the "L" level. To maintain this, the signal Sod does not change from the L II level. on the other hand,
Since the transistor Q6 in FIG. 1 is conductive, the node N□
The potential VHL of E is rapidly charged toward the power supply voltage VCC. At this time, the gate of the transistor QC has (V c
c+V th) or higher potential V, (7) iiJ control signal S
Since OB is applied, the impedance of the transistor Qc is low and does not interfere with pushing up the potential of the node "HL." After time T7, ■□.

>VH2, the transistor Q19 becomes conductive, and the potential of the node N5' changes to the "L"2 level.Therefore, the other input of the AND gate AND1, which is the potential of the node N5, also becomes a "tabil bell" and the signal 5od (Sod) becomes the HTT level ( “Shiva level)”.

On the other hand, in FIG. 2, when the signal Sod becomes H" level, the potential of the node N increases to more than (V CC + V 13 (threshold voltage of transistor Q13)) due to the capacitor-mother coupling of capacitor C1, and transistor Q12 Then, the transistor Q13 becomes strongly conductive, clamping the potential of the control signal SOB to the power supply voltage 0.Meanwhile, the signal Sod changes to the "LIT" level, and due to the capacitive coupling of the capacitor C2. In order to lower the potential of the control signal SOB, the potential of the control signal SOB rapidly reaches the power supply voltage V. reaches 0.

Then, when the inverted equalize signal EQ falls to the "high" level at time T6, the potential of the node NB also becomes the "L" level, and the transistor Q13 becomes non-conductive. At this time, the control signals So and SOF also fall to the "L" level, so the signal Sod (Sod) changes to the "L" level ("T1" level), and the control signal SO8 changes due to the capacitive coupling of the capacitor C2. The potential is set to ■ again.

FIG. 6 shows signals showing the read operation of the DRAM shown in FIG. The read operation will be explained below with reference to the same figure.

When the equalize signal EQ falls at time T1, transistors oY-o9 become non-conductive, and (■cc-vth)
The bit line pair BL, BL precharged to /2 becomes a floating state.

Then, when the word line rises to the ``to1'' level at time T2, the selection transistor Q0 in the memory cell 1 becomes conductive.
The charge accumulated in the memory capacitor CO is transferred to the bit line BL.
When the memory capacitor CO stores the "HII level", the potential of the bit line BL rises slightly as shown by the solid line in FIG.

Then, at time T3, the control signal So (So) rises (falls) to the "H" level ("L II level").
Transistor Q5. If Q6 becomes conductive, the potential of the connection line LL is discharged to the ground level, and the potential of the connection line HL becomes ■. Charge towards 0. At this time, the control signal 30B is at a high potential V,
Therefore, the transistor Q. is in a low impedance state and does not interfere with the rapid charging of the connection line HL.

Then, at time T7 when the potential of the connection line HL becomes (Voo-Vth) or less (N3 in FIG. 5), the potential of the control signal SOB becomes VC. level, and set the potential of the connection rc D HL (■
oo-■th). Immediately thereafter, the potential of the connection line HL reaches (V cc - V th).

Therefore, sense amplifier 2 activated at time T3 detects a slight potential difference between bit lines BL, BL, and transistors Q1. Q4 conducts, transistor Q2. By making Q3 non-conductive, the potential of connection tfA8L becomes (V cc
-V th), the potentials of the bit line pair BL, BL are amplified to the (V cc -V th) level and the ground level, respectively.

Then, as the signal Y rises at time ■4, the transistor Q10. Qll becomes conductive, and the potential of bit lines BL and BL becomes I10 line I10. The signal is transmitted to Ilo, and then amplified, and the "FIIT level" is output from the external output terminal.

Then, by lowering the word line WL to "L" level at time 5, memory cell 1 and bit vA8L are cut off.

By simultaneously lowering the signal Y, bit line pair BL, BL
and I10 line pair I10. Place Ilo at 'a'.

And below the time. When the equalize signal EQ rises, the transistors 07 to Q9 are made conductive.

At this time, one of the bit line pair BL, BL is (Voo-Vt
h), the transistor Q7 is conductive because the other is O■
By equalizing the bit line pair BL and BL, the potential of both can be set to (■CC-■th)/2. Therefore, the internal power supply VBL does not need to forcibly precharge the bit line pair BL, BL to (Voo-v, h)/2 as in the conventional case, and only needs to hold (■oo-Vth)/2. .

Its unity, internal type'/fQv8. Since this requires almost no driving capacity and the resistance value of the dividing resistor can be increased, the standby current can be significantly reduced. Note that the portions indicated by dotted lines in FIG. 6 indicate the waveforms of each signal when the memory capacitor CO stores the L II level.

In this way, the internal power supply v at (vCc-Vth)/2 level
BL requires almost no driving capacity and can significantly reduce standby current, resulting in a significant reduction in power consumption.

Note that in this embodiment, the transistor Q. Although the explanation has been made for the case where the channel is n-channel, it can be realized even if the channel is set to n-channel by appropriately changing the control signal.

Further, the control signal SOB is V CC1 (V cc + V
th) An example of the binary potential □ of ■ and above was shown. ■P level is at around time 13, and ■ when the sense amplifier 2 is activated thereafter. . It may be at any level, and other time periods may be, for example, O■.

〔Effect of the invention〕

As described above, according to the present invention, by connecting both bit line pairs after amplification, the potential of each bit line pair can be set to 1/2 of the predetermined potential obtained by shifting down the first power supply voltage, Since precharging can be performed using an internal power supply with low driving capacity, it is possible to reduce the charging and discharging current of the bit line pair without increasing the standby current.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing the memory cell and sense amplifier periphery of a DRAM according to an embodiment of the present invention, and FIGS.
The causes are circuit diagrams showing details of the SO8 control circuit, FIG. 4 is a circuit diagram showing an example of generation of the control signal SO, and FIG. 5 is a circuit diagram showing the details of the SO8 control circuit.
6 is a timing diagram showing the operation of the OB Ill 1111 circuit; FIG. 6 is a timing diagram showing the read operation of the DRAM shown in FIG. 1; FIG. 7 is a diagram showing the memory cell and sense amplifier surroundings of a conventional DRAM; This figure is a timing diagram showing the read operation of the DRAM shown in FIG. 7. In the figure, 1 is a memory cell, 2 is a sense amplifier, 3 is an SOB control circuit, 4 is a current mirror amplifier circuit, 8m,
(BL) is a bit line, LL, and HL control signals. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (3)

[Claims] (1) A sense amplifier to which a first power supply voltage and a second power supply voltage are respectively supplied from the first and second voltage supply paths according to a first control signal detects and amplifies the potential difference between the bit line pair. In a semiconductor memory device of a type that reads information from a memory cell, a second control signal related to the first control signal is activated, the potential of the first voltage supply path is detected, and the potential is read out. potential detecting means for providing an output signal indicating whether or not the voltage is near a predetermined potential obtained by shifting down the first power supply voltage; In response, if the potential of the first voltage supply path is outside the vicinity of the predetermined potential, a fast charging function is activated to rapidly charge the first voltage supply path to approach the predetermined potential; If the potential of the first voltage supply path is within the vicinity of the predetermined potential, a voltage drop function is activated to set the potential of the first voltage supply path to the predetermined potential by shifting down the first power supply voltage. Accordingly, the sense amplifier includes means for quickly setting the potential of the first voltage supply path to the predetermined potential, and the sense amplifier sets one of the bit line pair to the predetermined potential and the other to the second potential during amplification. A semiconductor memory device characterized by being set at a power supply voltage level. (2) The means for setting the predetermined potential includes a transistor interposed in the first voltage supply path and receiving the output signal of the detecting means at a control electrode, and the means for setting the predetermined potential includes a transistor that is disposed in the first voltage supply path and receives an output signal from the detection means in the voltage drop function, and is performed by setting the output signal of the detection means to the first power supply voltage, and the fast charging in the fast charging function is performed by setting the output signal of the detection means to the first power supply voltage and the threshold voltage of the transistor. 2. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is set to be greater than or equal to the sum of . (3) The semiconductor memory device according to claim 1 or 2, wherein the second power supply voltage is at ground level.