JPH01147722A - Pipe line processing system for information processor - Google Patents

Abstract

PURPOSE:To reduce a processing time at the time of a program action which is not accompanied with an arithmetic execution requiring plural cycles and to improve a total throughput by carrying out an action mode transition which uses different long and short pipe line actions. CONSTITUTION:An instruction control device 1 reads an instruction from a memory control device 2, decodes it, obtains a logical address by an address calculation if needed, reads an operand from a device 3, and transfers an operation code, the operand, operation information, etc., to an operating device 3. At the device 3, arithmetic units 35 and 36 are provided, and they respectively carry out a floating decimal point operation and a binary basic operation. The former requires three cycles for digit matching, an operation and a normalizing circuit, on the contrary, the latter requires only one cycle. At the time of the program action of an operating system, etc., by changing to the latter short pipe line action, the total throughput can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing apparatus that performs pipeline processing, and particularly to a pipeline processing method.

[Conventional technology]

Conventionally, in this type of information processing device, operations using floating point instructions and decimal instructions are complicated to perform, and therefore the operations take multiple cycles to execute. In addition, some supercomputers and large-scale measuring machines contain calculations!
Some are A-b pipelined.

[Problem that the invention seeks to solve]

In the conventional information processing device described above, floating point instructions,
Decimal instructions and the like require multiple cycles to execute an operation, so executing such an instruction causes a disturbance in the pipeline and reduces the throughput of instruction execution. When the processing cycle is pipelined, it becomes possible to perform continuous calculations, so there is no disturbance in the pipeline and the throughput does not drop. 'r'h, there are drawbacks such as a delay in determining branch prediction failure and a long wait for address modification registers to be confirmed.

[Means for solving problems]

The pipeline processing method of the information processing device of the present invention does not perform pipeline processing for performance execution, but performs a short pipeline operation and pipeline processing for performance execution, resulting in a good pipeline! The operation mode transitions from the operation mode in which the l1 operation is performed.

[Effect]

For systems such as operating systems where the frequency of floating-point instructions is low and the slope of branch instructions is high [during 1-gram operation, the processing time of frequently occurring branch instructions is reduced by performing non-greasy vibe line operation, On the other hand, when operating a Japanese technical calculation program that uses floating point instructions frequently and branches instructions less frequently, by performing arithmetic pipeline operation, the processing time of frequently occurring floating point instructions can be reduced, and the overall Throughput can be increased.

(Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an information processing apparatus to which the vibration line processing method of the present invention is applied.

This embodiment is comprised of an instruction control device 1, a storage control bag @2, performance equipment 3, and the like.

The instruction control device 1 reads the instruction from the memory system tII device 2, decodes it, and if necessary, uses an address tool 1 to find a logical address, reads the operand from the memory control device 2, and calculates an operation code, operand, operation information, etc. Transfer to device 3. The oil cylinder device 3 performs calculations based on information set by the instruction control device 1, and updates the main memory through various registers, status, or the storage control device 2.

In the instruction control device 1, a bit field of the instruction register (IR) 11 specifies a general register file (C
GR) Read the contents of the register from 13. In an RX type instruction, an index value and a base value are read from the general register file 13 to generate an address. This index value and base value are stored in the register (xR) 15 along with the displacement value directly specified by the instruction.
(BR) 16 and (DR) 14, respectively. Based on the values of these registers 14, 15, and 16, an operand address is generated by the address adder (ADH) 17, sent to the storage control device 2, and stored in the address register (
MAR) 21. This operand address is subjected to address translation by an address translation mechanism (TLB) 22, and the cache address array (AA) 22
The data array (DA) 2 is held in the address register (PAR) 23 along with the directory information read from the data array (DA) 2.
71 is used as the read address.

From this, the operand is read from the data array 24 and sent to the arithmetic unit 3. On the other hand, the first operand of the RX type instruction RR tie! First command. The register number in which the second operand is stored is transferred to the arithmetic unit t! via register (IDR) 18 and decode information key 1-(IDQ) 19. 73
and is held in the register (EDR) 31. In calculation 11ff3, the command Ib control device 1 is executed prior to the execution of the oil cylinder.
Operands are read from the general register file (GR) 32 based on the register numbers sent from the GR. One of the read register values is set as the first operand in the operational register (DARO, FDΔRO) 51.41. The other register value is selected by the operand and selector (SEL>33) sent directly or via the data buffer (DB) 34 from the storage control device 2, and is sent to the operation register (DAR1, FDAR1) as the second operand.
It is set to 52°42. Arithmetic units 35 and 36 perform binary basic operations and floating point operations, respectively. Engin Conit (FAU) 35 performs floating point arithmetic, but floating point arithmetic requires digit alignment of the floating point number before the operation and normalization afterward, requiring multiple cycles for the operation. Must! There is r.

In this embodiment, one cycle is required for digit alignment of the arithmetic wA, 1+J cycles are required for addition and subtraction, and 1 cycle is required for normalization of the operation result, and 3 cycles are required for operation n of a floating point number. On the other hand, the arithmetic unit (B.DELTA.U) 36 performs basic binary operations, but binary operations are more difficult than floating point operations, and in this embodiment, one cycle of addition and subtraction r- ends. Note that the arithmetic unit 35 has registers 41, 42 .
44.45°47.49, a digit alignment circuit 43, a floating point stem unit (FALU) 46, and a normalization circuit 48, and the arithmetic unit 36 has a register 51.52.54°5
5.56, it is composed of a logical operation circuit (ALU) 53. The selection circuit 37 selects and outputs the output of the register 49.54.56 in response to the operation mode flag added to the PSW. By setting logic "1" to the operation mode flag by a certain instruction, processing is performed in the pipeline of operation execution, but in order to match the quality of the pipeline of operation units 35 and 36, the binary basic operation Result carrying registers (DCR, DDR) 55,56 are used. FIG. 2(a) is a time chart of the pipeline in this operation mode. In the figure, D.

A, P, C, L, IE, N, and S indicate a decode cycle, address generation cycle, paging cycle, cache read cycle, digit alignment cycle, arithmetic cycle, normalization cycle, and store cycle, respectively. The execution cycle of the binary basic instruction (player) is also controlled to run smoothly in the pipeline by taking three cycles in conjunction with the floating point instruction. A certain instruction sets the operation mode flag to a logical value of ``0'', so that pipeline processing for execution of operations is not performed.
．． Since there is no need to match the lengths of the 36 pipelines, the registers (DCR, DDR) 55 and 56 are bypassed and are not used. 21A(b) is a time chart of the pipeline in this operation mode. Figure 2(b)
The pipeline shown in FIG. 2 is different from the one shown in FIG. 2(a) in that it is a binary basic instruction pipeline, and there are no first cycle or N cycle, and the calculation processing cycle is only one cycle, the E cycle. However, since floating point instructions require 3 cycles (E and N cycles) for arithmetic processing, if 2381 instructions follow, 2 cycles will be left unused and the throughput will decrease.

Figures 2 (C) and (d) show tie hub 1 for branch instruction processing (branch prediction failure h) in two pipeline modes.
It is 1-t. The branch direction of a branch instruction is determined when the execution of the instruction immediately before the branch instruction is completed. It is also determined at this point whether the branch prediction was successful or not, and if the prediction fails, the decoding cycle begins from there. FIG. 2C shows a time chart of branch prediction failure in the arithmetic vibe line mode. In the figure, the operation cycle of the binary basic instruction immediately before the branch instruction ends in N cycles, but the success/failure of branch prediction is not known until this cycle ends. Therefore, in the case of prediction failure, there is a delay of five cycles in the execution of the branch destination instruction. Figure 2(d)
1 is a time chart showing a failure in branch prediction in the No. 1 performance pipeline mode in which the logical value II OH is set in the operation mode flag. In the figure, 23! immediately before the branch instruction! The arithmetic processing cycle of the Fumoto instruction ends in the E cycle, and at the end of this cycle, the success/failure of branch prediction is known. Therefore, in the case of branch prediction failure, the execution of the branch destination instruction takes 3 cycles of J3 delay, but the delay is 2 cycles less than in the case shown in FIG. 2(C).

As described above, in the arithmetic pipeline mode operation, even when processing an instruction such as a floating point instruction that requires multiple cycles to process 80 bits, one extra cycle is not required, but there is a large delay due to branch prediction failure, for example. On the other hand, in non-arithmetic pipeline mode operation, when processing instructions that require multiple cycles for arithmetic processing, such as floating-point instructions, the pipeline processing is disrupted by the amount of @sieving processing cycles, but the delay due to branch prediction failure is small. It has characteristics.

In this embodiment, when the operation mode flag is logic "1", the operation pipeline mode is set, and when the logic 11Jj value is "0", it is the non-operation pipeline mode, but the combination of logic values may be reversed.

[Efficacy of invention Song Dynasty]

As explained above, the present invention provides an operation mode transition between an operation mode in which a short pipeline operation is performed without pipeline processing of calculation execution, and an operation mode in which a long pipeline operation is performed with pipeline processing of calculation execution. By doing this, when operating a system program such as an operating system where the frequency of floating point instructions is low and the frequency of branch instructions is high, by performing the operation pipeline operation, you can reduce the frequency of branch instructions that occur frequently. Reduce processing time, conversely increase the frequency of floating point instructions,
When operating programs such as Japanese language technology Kl cylinder programs that have a low frequency of branch instructions, by performing a deductive pipeline test, the frequency of occurrence of branch instructions is high)? This has the effect of reducing the processing time for the first few instructions and increasing the overall throughput.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram of an embodiment of an information processing apparatus to which the pipeline processing method of the present invention is applied, and FIG. 2 is a time chart in this embodiment. DESCRIPTION OF SYMBOLS 1... Instruction control device, 2... Storage control device/r, 3... ty+disguise device 5... Floating point arithmetic unit, 36... Binary Tanuki processing unit.

Claims (1)

[Claims] In an information processing device that performs advance control, an operation mode in which a short pipeline operation is performed without pipeline processing of calculation execution, and an operation mode in which a long pipeline operation is performed with pipeline processing of calculation execution A pipeline processing method for information processing equipment that performs transitions.