JPH01147457A - Formation of pattern for semiconductor device - Google Patents

Formation of pattern for semiconductor device

Info

Publication number
JPH01147457A
JPH01147457A JP62306579A JP30657987A JPH01147457A JP H01147457 A JPH01147457 A JP H01147457A JP 62306579 A JP62306579 A JP 62306579A JP 30657987 A JP30657987 A JP 30657987A JP H01147457 A JPH01147457 A JP H01147457A
Authority
JP
Japan
Prior art keywords
light
pattern
slit
photomask
fine
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62306579A
Other languages
Japanese (ja)
Inventor
Masatsugu Komai
正嗣 駒井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP62306579A priority Critical patent/JPH01147457A/en
Publication of JPH01147457A publication Critical patent/JPH01147457A/en
Pending legal-status Critical Current

Links

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE:To process a fine pattern by providing a slit on the outer periphery of the light shielding region of a photomask. CONSTITUTION:The slit B which is not resolvable is formed at the inside of a shielding pattern A along the outer peripheral area as a light shielding pattern formed on the photomask surface, and the fine pattern is formed by using the light shielding pattern possessing such slit. Thus, the light passed through the slit is detoured around the light transmissive region which originally requires exposure, and when the exposure quantity is not enough owing to the fine light transmissive region, a photo resist is exposed with the light quantity supplement, and the fine pattern is formed.

Description

【発明の詳細な説明】 ぐ産業上の利用分野〉 本発明は半導体装置の製造工程におけるパターン形成方
法に関し、特にはホトマスクを用いて露光及び現像して
パターンを形成する方法に関する。
DETAILED DESCRIPTION OF THE INVENTION Industrial Application Field The present invention relates to a method for forming a pattern in the manufacturing process of a semiconductor device, and more particularly to a method for forming a pattern by exposure and development using a photomask.

〈従来の技術〉 半導体装置は、半導体基板への素子作呵の高密度化が進
もと共に、素子自体の寸法が非常に微細化してきている
。このような微細加工への対応はパターン炸裂工程で使
用するホトレジストや現像液或いは露光装置の改良によ
って行われている。
<Prior Art> As semiconductor devices have become more densely fabricated on semiconductor substrates, the dimensions of the elements themselves have become much finer. Such fine processing has been addressed by improving the photoresist, developer, or exposure device used in the pattern bursting process.

ぐ発明が解決しようとする問題点〉 感光材料等に関しては、分子嗜分布の分散度の向上や、
感光材に加える添加物全改良した高解像度のホトレジス
トを開発したり、露光装置に関して)ま次式に示すよう
にNA(レンズ開口径)を大きくすることによって解像
度の向上が図られている。
Problems to be solved by the invention
Improvements in resolution are being attempted by developing high-resolution photoresists with completely improved additives added to photosensitive materials and by increasing the NA (lens aperture diameter) as shown in the following equation (with respect to exposure equipment).

(R=理論解像度)  (FD=焦点深度)しかし現実
の半導体装置においては、表面に形成した酸化膜や導体
等によって段差が生じてふ・り段差の上及び下の両方に
対して黒点が合う朝囲は狭く、解像度向上の点で問題が
あった。
(R = theoretical resolution) (FD = depth of focus) However, in actual semiconductor devices, steps are created by oxide films, conductors, etc. formed on the surface, and the black dot coincidentally aligns with both the top and bottom of the steps. The morning area was narrow, and there was a problem in improving resolution.

まfLLJi光時に使用する光源の波長を短かくすれば
、同様に理論解像度は向上するが、レンズ設計が1しく
なり、且つレンズ材質の選択も難しくなる。
If the wavelength of the light source used for the fLLJi light is shortened, the theoretical resolution will be similarly improved, but the lens design will become difficult and selection of the lens material will also become difficult.

その面光の回折効果を緩和させて解19力を向上させる
CEL技術も提案されているが、工程数が増えコストも
高くなるという問題があった。
CEL technology has been proposed to improve the resolution by alleviating the diffraction effect of surface light, but this has the problem of increasing the number of steps and increasing costs.

本発明は上記問題点に鑑みてなされたもので、解像度を
低下させることなく微細パターンの加工を可能にしたパ
ターン形成方法を提供する。
The present invention has been made in view of the above problems, and provides a pattern forming method that enables processing of fine patterns without reducing resolution.

く問題点を解決するための手段〉 本発明は、半導体基板上に塗布された1嶽光材にパター
ン形成する工程において、ホトマスク面に形成する遮光
パターンとして、遮光パターンの内側に、外向に添って
解像されない程度のスリット全形成し、このようなスリ
ットをもつ遮光パターンを用いて微細パターンを形成す
る。
Means for Solving the Problems> The present invention provides a light shielding pattern formed on a photomask surface in the step of patterning a single-layer photosensitive material coated on a semiconductor substrate. All the slits are formed to such an extent that they cannot be resolved, and a fine pattern is formed using a light-shielding pattern having such slits.

く作 用〉 遮光パターンの外向に添って微小スリブ)f設けている
ため、該スリブ)k通過した光は、本来露光を必要とす
る透光性領域にまわり込み、たとえ透光性領域が微細な
ために露光計が少ない場合にも、光砒を補ってホトレジ
ストを露光し、所望のパターンを形成することができる
Function> Since the microscopic strip (f) is provided along the outside of the light-shielding pattern, the light that passes through the strip (k) will wrap around the translucent area that originally requires exposure, and even if the translucent area is microscopic. Therefore, even if there are few exposure meters, the photoresist can be exposed with supplementary light arsenic to form a desired pattern.

〈実施例〉 第1図は本発明による一実施例のホトマスクパターンを
示し、ガラス等の透明板表面に形成され斜線領域Aはク
ロム膜等をパターニングして形成した遮光領域である。
<Embodiment> FIG. 1 shows a photomask pattern of an embodiment of the present invention, in which the shaded area A formed on the surface of a transparent plate such as glass is a light-shielding area formed by patterning a chrome film or the like.

上記遮光領域Aは図に示す如く、外向から内側に微小距
1礪Δtだけ入った位置に、遮光膜のない透光性の幅Δ
ノからなるスリットBが外向を巡って形成されている。
As shown in the figure, the above-mentioned light-shielding area A has a light-transmitting width Δt without a light-shielding film at a position that is a minute distance Δt inward from the outside.
A slit B consisting of is formed outwardly.

ここで発明者が実験によって確認した値としてはΔtは
0.5μm、Δノは0.2μm程度に設計した場合にス
リ・ノドを解像することなく遮光領域A及び遮光領域C
との間で最も良好なパターンを形成することができた。
Here, the values confirmed by the inventor through experiments are that Δt is designed to be about 0.5 μm and Δ is designed to be about 0.2 μm, without resolving the pick-pocket throat.
The best pattern could be formed between the two.

即ち、上記パターンによって露光した場合、隣接する遮
光領域A、Aifi’lに位置する透光領域Cに照射さ
れた光が透過してホトレジスミJ光させる。ここでパタ
ーンが微細な場合透光領域Cの幅は極めて小さくなり、
従って露光光量も少なくホトレジストを充分に感光させ
得ない事態が生じ、微細パターンの形成に支障が生じる
。しかし上述のように遮光領域の外1曲にスリットBを
設けることにより、スリットBを透過した光はまわり込
んで透光領域Cの先遣を補充し、パターンの解像度を高
める。
That is, when exposure is performed according to the above pattern, the light irradiated to the adjacent light-shielding region A and the light-transmitting region C located at Aif'l is transmitted to produce photoresist light. Here, if the pattern is fine, the width of the transparent area C will be extremely small,
Therefore, the amount of exposure light is too small and the photoresist cannot be sufficiently exposed, causing problems in the formation of fine patterns. However, as described above, by providing the slit B in one area outside the light-shielding area, the light transmitted through the slit B goes around and replenishes the light-transmitting area C, thereby increasing the resolution of the pattern.

第2図はホトマスクにおける透光領域Cの幅を0.7μ
m、0.9μmとし、スリットがない場合とスIJ =
ン) B ’i膜形成た場合の露光時間と現像後におけ
る透光領域Cの福との間冷を示し、スリットBを設けた
場合の方がいずれの線幅においても現像限界値が低く微
5剤加工が可能であることを示している。
In Figure 2, the width of the transparent area C in the photomask is 0.7μ.
m, 0.9 μm, and when there is no slit, slit IJ =
B) It shows the cooling between the exposure time when the i film is formed and the thickness of the transparent area C after development, and the development limit value is lower and finer for any line width when the slit B is provided. This shows that five-drug processing is possible.

上記スリットBを形成したホトマスクを用いて半導体基
板上のホトレジストに対沁するパターンを形成する工程
においては、半導体基板上にポジ型レジストを塗布した
後これを熱処理してホトレジスト19中に残存する溶剤
を揮発させる。次にホトレジスト膜上に上記スリットB
全もつホトマスクを対向させて紫外線等により露光し、
有機溶剤等の現像液を用いてホトレジストを現像し、ホ
ト7スクの・遮光領域A外1i1jl K引当するパタ
ーン形成する。
In the step of forming a pattern on the photoresist on the semiconductor substrate using the photomask in which the slits B are formed, a positive resist is applied on the semiconductor substrate and then heat-treated to remove the solvent remaining in the photoresist 19. volatilize. Next, the above slit B is placed on the photoresist film.
Expose with ultraviolet rays, etc. with full photomasks facing each other,
The photoresist is developed using a developer such as an organic solvent to form a pattern corresponding to the outside of the light-shielding area A of the photoresist.

例えばL OG OS膜形成前の下地SiN/5i02
上で上記パターン形成方法を適用した場合、スリlト全
もたない遮光領域のホトマスクによるパターン形成に比
べてLOCO5による素子分帷幅を少なくとも0.1〜
0.15μmは小さくすることができたd。
For example, the base SiN/5i02 before LOG OS film formation
When the above pattern forming method is applied, the device width due to LOCO5 is at least 0.1 to 0.1% compared to pattern formation using a photomask in a light-shielding area without any slits.
d could be reduced to 0.15 μm.

〈効 果〉 以上本発明によれば、簡単な構成を付加することによ゛
り微細パターンの加工が可能になり、半導体装置の一層
の高密度化を図り得る。
<Effects> According to the present invention, by adding a simple configuration, it becomes possible to process fine patterns, and it is possible to further increase the density of the semiconductor device.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による一実施例を示すホトマスクパター
ン図、第2図は本発明を適用した露光工程時の露光時間
とパターン線幅の関係図である。
FIG. 1 is a photomask pattern diagram showing one embodiment of the present invention, and FIG. 2 is a diagram showing the relationship between exposure time and pattern line width during an exposure process to which the present invention is applied.

Claims (1)

【特許請求の範囲】 1、半導体基板上に被着した感光層をホトマスクを介し
て露光し、現像して感光層にパターンを形成する方法に
おいて、 ホトマスクに形成された遮光部は、遮光部外周から内側
に微少間隔入り込んだ位置に、入り込み量より小さい透
光性スリットを形成してなることを特徴とする半導体装
置のパターン形成方法。
[Claims] 1. In a method in which a photosensitive layer deposited on a semiconductor substrate is exposed to light through a photomask and developed to form a pattern on the photosensitive layer, a light-shielding portion formed on the photomask is formed on the outer periphery of the light-shielding portion. 1. A method for forming a pattern for a semiconductor device, comprising: forming a light-transmitting slit at a position that penetrates inward at a minute interval, the size being smaller than the amount of penetration.
JP62306579A 1987-12-02 1987-12-02 Formation of pattern for semiconductor device Pending JPH01147457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62306579A JPH01147457A (en) 1987-12-02 1987-12-02 Formation of pattern for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62306579A JPH01147457A (en) 1987-12-02 1987-12-02 Formation of pattern for semiconductor device

Publications (1)

Publication Number Publication Date
JPH01147457A true JPH01147457A (en) 1989-06-09

Family

ID=17958758

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62306579A Pending JPH01147457A (en) 1987-12-02 1987-12-02 Formation of pattern for semiconductor device

Country Status (1)

Country Link
JP (1) JPH01147457A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5115376A (en) * 1990-01-23 1992-05-19 Sharp Kabushiki Kaisha Ic card ejecting device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5115376A (en) * 1990-01-23 1992-05-19 Sharp Kabushiki Kaisha Ic card ejecting device

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