JPH01146624U - - Google Patents
Info
- Publication number
- JPH01146624U JPH01146624U JP1988041033U JP4103388U JPH01146624U JP H01146624 U JPH01146624 U JP H01146624U JP 1988041033 U JP1988041033 U JP 1988041033U JP 4103388 U JP4103388 U JP 4103388U JP H01146624 U JPH01146624 U JP H01146624U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- high frequency
- electric field
- input
- gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005684 electric field Effects 0.000 claims 3
- 230000003321 amplification Effects 0.000 claims 2
- 238000003199 nucleic acid amplification method Methods 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 4
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Control Of Amplification And Gain Control (AREA)
- Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
Description
第１図はこの考案に係るチユーナの利得制御回
路の一実施例を示すブロツク図、第２図は第１図
の実施例の具体的回路の一例を示す回路図、第３
図はこの考案に用いたＰＩＮダイオードの動作特
性図、第４図、第５図はこの考案の動作を説明す
るためのＡＧＣ動作特性図、第６図は一般的なＲ
ＦＡＧＣシステムを説明するブロツク図、第７図
は従来のチユーナ回路の構成を示すブロツク図で
ある。
２０……利得制御端子、２１……入力単同調回
路、２２……高周波増幅回路、２３……段間複同
調回路、２４……混合回路、２５……局部発振回
路、２９……ＰＩＮダイオード回路、Ｄ１……Ｐ
ＩＮダイオード、Ｄ２……ダイオード、Ｒ１，Ｒ
２，Ｒ３，Ｒ４……抵抗。
FIG. 1 is a block diagram showing an embodiment of a tuner gain control circuit according to this invention, FIG. 2 is a circuit diagram showing an example of a specific circuit of the embodiment of FIG. 1, and FIG.
The figure shows the operating characteristics of the PIN diode used in this invention, Figures 4 and 5 show the AGC operating characteristics to explain the operation of this invention, and Figure 6 shows the typical R
FIG. 7 is a block diagram illustrating the FAGC system. FIG. 7 is a block diagram showing the configuration of a conventional tuner circuit. 20...Gain control terminal, 21...Input single tuning circuit, 22...High frequency amplifier circuit, 23...Interstage double tuning circuit, 24...Mixing circuit, 25...Local oscillation circuit, 29...PIN diode circuit , D1...P
IN diode, D2... diode, R1, R
2, R3, R4...Resistance.
Claims (1)
答した電圧によつて利得制御する高周波増幅回路
と、この高周波増幅回路の出力端から混合回路の
入力端への信号経路のいずれかに接続し前記高周
波増幅回路に利得制御が働く入力電界より低い電
界域より前記高周波増幅回路からの出力を利得制
限するＰＩＮダイオードとを具備したことを特徴
とするチユーナの自動利得制御回路。 A high frequency amplification circuit that controls the gain of a high frequency signal selected as an input by a voltage responsive to the input electric field strength, and a signal path from the output end of this high frequency amplification circuit to the input end of the mixing circuit, 1. An automatic gain control circuit for a tuner, comprising: a PIN diode for gain limiting the output from the high frequency amplifier circuit in an electric field region lower than an input electric field where gain control is applied to the amplifier circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988041033U JPH01146624U (en) | 1988-03-30 | 1988-03-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988041033U JPH01146624U (en) | 1988-03-30 | 1988-03-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01146624U true JPH01146624U (en) | 1989-10-09 |
Family
ID=31267485
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988041033U Pending JPH01146624U (en) | 1988-03-30 | 1988-03-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01146624U (en) |
-
1988
- 1988-03-30 JP JP1988041033U patent/JPH01146624U/ja active Pending
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