JPS63149631U - - Google Patents
Info
- Publication number
- JPS63149631U JPS63149631U JP4277287U JP4277287U JPS63149631U JP S63149631 U JPS63149631 U JP S63149631U JP 4277287 U JP4277287 U JP 4277287U JP 4277287 U JP4277287 U JP 4277287U JP S63149631 U JPS63149631 U JP S63149631U
- Authority
- JP
- Japan
- Prior art keywords
- receiver
- input
- control circuit
- circuit
- intermediate frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006835 compression Effects 0.000 claims description 3
- 238000007906 compression Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 5
- 230000003321 amplification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Channel Selection Circuits, Automatic Tuning Circuits (AREA)
- Superheterodyne Receivers (AREA)
Description
第１図は本考案の一実施例のＡＭ受信機のブロ
ツク図、第２図は第１図の圧縮増幅器の入出力特
性図、第３図は本実施例のＩＦ信号の波形図、第
４図は従来のＡＭ受信機の一例のブロツク図、第
５図は第４図で変調度の大きい場合のＩＦ信号の
一例の波形図である。
１……アンテナ、２……高周波増幅回路（ＲＦ
）、３……混合回路（ＭＩＸ）、４……中間周波
増幅回路（ＩＦ）、６……局部発振回路（ＯＳＣ
）、７……シグナルメータ回路（ＳＭ）、８……
制御回路、９……比較回路、１０……設定回路、
１１……ゲート回路、１２……圧縮増幅回路。
Fig. 1 is a block diagram of an AM receiver according to an embodiment of the present invention, Fig. 2 is an input/output characteristic diagram of the compression amplifier of Fig. 1, Fig. 3 is a waveform diagram of the IF signal of this embodiment, and Fig. 4 The figure is a block diagram of an example of a conventional AM receiver, and FIG. 5 is a waveform diagram of an example of an IF signal when the degree of modulation is large in FIG. 4. 1...Antenna, 2...High frequency amplification circuit (RF
), 3...Mixing circuit (MIX), 4...Intermediate frequency amplifier circuit (IF), 6...Local oscillation circuit (OSC)
), 7... Signal meter circuit (SM), 8...
Control circuit, 9... Comparison circuit, 10... Setting circuit,
11...gate circuit, 12...compression amplifier circuit.
Claims (1)
の受信信号が入力された場合、制御回路に中間周
波数信号を入力してその周波数を計算して電子的
に同調を行うＡＭ受信機において、前記制御回路
に入力する前期中間周波数信号の高入力レベルを
圧縮する圧縮増幅回路を備えたことを特徴とする
ＡＭ受信機。 In an AM receiver that inputs an intermediate frequency signal to a control circuit, calculates its frequency, and performs electronic tuning when a received signal equal to or higher than a set value is input so as to electronically select a broadcast signal. An AM receiver comprising a compression amplifier circuit that compresses a high input level of an intermediate frequency signal input to a control circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4277287U JPS63149631U (en) | 1987-03-23 | 1987-03-23 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4277287U JPS63149631U (en) | 1987-03-23 | 1987-03-23 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63149631U true JPS63149631U (en) | 1988-10-03 |
Family
ID=30859002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4277287U Pending JPS63149631U (en) | 1987-03-23 | 1987-03-23 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63149631U (en) |
-
1987
- 1987-03-23 JP JP4277287U patent/JPS63149631U/ja active Pending
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