JPH01142959A - Cache memory device - Google Patents

Abstract

PURPOSE:To attain the memory access of an indirect address system at a high speed by registering the data of a data area in a memory indirectly designated into an area in a cache memory like the data designated immediately after it. CONSTITUTION:When the memory address of an indirect address system is held at an address register 11, a cache memory 40 is accessed and the contents of an address tag part 41, an effective flag part 42, a data part 43 and a data part 44 are read. A comparing deciding part 52 compares the contents of a memory address field 11b read to the register 11 and the address information read to a data line 41a. At the time of the in-consistency, the output from a multiplexer 51 is prohibited. In this case, the access to a memory 12 is executed two times, the data of the memory 12 designated indirectly are registered at the area in the data part 44. The V flag of the effective flag part 42 becomes effective.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Field of Industrial Application) The present invention relates to a cache memory device suitable for a system that performs both direct address method and indirect address method memory access.

(Prior art) In general, the memory address instruction method that is used when accessing memory is the direct address instruction method (direct address method).
There is an indirect addressing method (indirect addressing method). As shown in FIG. 2, the direct addressing method is a normal memory address instruction in which the data existing in the data area in the memory 12 pointed to by the memory address held in the address register (AR) 11 at the time of memory access is obtained as the target data. It is a method. On the other hand, the indirect addressing method, as shown in FIG. 3, uses data existing in the data fr4 area of the memory 12 pointed to by the memory address held in the address register 11 at the time of memory access as a new memory address. The target data is obtained by accessing the memory 12 again.

Now, in recent years, in order to link memory access, cache memory (high-speed backup memory) is being used as shown in Figure 4.
A cache memory device with 20 is used. This cache memory 20 is an address register (AR)
The address tag section 21, the valid flag section 22, and the data section 23 are each memory section designated by the field 11a of No. 11.

The data section 23 has the memory 1 shown in FIGS. 2 and 3.
2 is registered, a flag (V flag) indicating the validity of the data registered in the corresponding area of the data section 23 is registered in the valid flag section 22, and in the address tag section 21, Address information corresponding to the stored data area in the memory 12 of the data registered in the corresponding area of the data section 23 (here, a field 11 different from the above-mentioned field 11a of the memory address indicating the data area)
b) is registered.

When a memory address is held in the address register 11 during memory access, the cache memory 20 is referenced in the field 11a. As a result, address information is transmitted from the address tag section 21 to the data line 21a, and a ■ flag is transmitted from the valid flag section 22 to the data line 22a.
Data is then read from the data section 23 to the data lines 23a, respectively.

The comparison/judgment unit 31 compares the contents of the field 11b of the address register 11 and the address information on the data line 21a, and determines that they match and that the data line 22a is the same.
If the V flag above is in the valid display state, the data in the data area in the memory 12 pointed to by the memory address held in the address register 11 is stored in the cache memory 2.
0, and outputs the gate signal 31a to the gate (G) 32. As a result, the data being read to the data line 23a from the data section 23 of the cache memory 20 is taken out to the outside of the cache memory device.

As is clear from the above operation, if the target data exists in (the data section 23 of) the cache memory 20, the data can be retrieved directly from the cache memory 2o, so the memory 12 is accessed. Faster access is possible compared to the previous case. However, when memory access is performed using the indirect addressing method, the cache memory 20 must be accessed at least twice, which takes more than twice as long as when using the direct addressing method.

(Problems to be Solved by the Invention) As mentioned above, in the past, at least two cache memory accesses were required to perform memory access using the indirect addressing method, so it was not possible to speed up memory access using the indirect addressing method. The problem was that there was no.

The present invention has been made in view of the above-mentioned circumstances, and its object is to provide a cache memory device in which indirect addressing memory access can be performed at high speed in the same manner as direct addressing memory access.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides memory access using a direct addressing method in which data in a first data area in a memory that is directly specified by a memory address is used as target data; For indirect addressing method memory access that uses data in a second data area in memory that is indirectly specified by as target data, the data in the first data area is placed in a predetermined field of a memory address that directly specifies the same data. Two types of cache memory: a first memory means that registers data in a corresponding area, and a first memory means that registers data in the second data area in an area that corresponds to a predetermined field of a memory address that indirectly specifies the same data. If the presence of data corresponding to the memory address is determined by referring to the cache memory using the predetermined field of the memory address for memory access, the first and second memory means The present invention is characterized in that either one of the data to be read out is selectively taken out depending on whether the memory access is by direct addressing or indirect addressing.

(Operation) According to the above configuration, the data in the second data area that is indirectly specified by the memory address is specified in the predetermined field of the memory address, like the data in the first data area that is directly specified by the memory address. Since the data is registered in the cache memory area, when the memory address is used as a memory address for indirect designation, the target data can be obtained with one cache memory access.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

Note that the same parts as in FIG. 4 are given the same reference numerals and detailed explanations are omitted.

FIG. 1 shows a block configuration of a cache memory device.

In the figure, 40 is a predetermined field 11a of the memory address held in the address register (AR) 11.
It is a cache memory that is dressed by (contents of) 7. The cache memory 40 includes an address tag section 41, a J flag section 42, and two data sections 43.
．． It consists of 44 memory sections. The data section 43 is used for registering data in the data area in the memory 12 that is directly specified by the memory address used when accessing the memory, as shown in FIG. It is used for registering data in a data area in the memory 12 that is indirectly designated by a memory address used when accessing the memory. Further, the valid flag section 42 is connected to the data section 43.
．． The address tag section 41 registers a flag (V flag) indicating the validity of the data registered in the corresponding area of 43 and 44, and the address tag section 41 registers the data registered in the corresponding area of the data section 43 and 44 in the memory 12. Address information corresponding to the storage data area (here, the contents of the memory address field 11b as in FIG. 4) is registered.

41a, 42a, 43a, and 44a are address tag sections 41.4 of the cache memory 40, respectively. Valid flag section 42, data section 43. the data line of the data section 44;
51 is a multiplexer (MUX) that switches the output of data on the data lines 43a and 44a. Valid target data 52 is registered in the cache memory 4o based on the contents of the memory address field 11b held in the address register 11, the address information from the address tag section 41, and the ■ flag from the valid flag section 42. This is a comparison/determination unit that determines whether or not the The comparison/judgment unit 52 receives an addressing method designation signal Fj5 indicating whether the memory access is direct addressing (direct addressing method) or indirect addressing (indirect addressing method).
2a and the multiplexer 51 according to the above determination result.
A switching signal 52b is output for the switch.

Next, the operation of the configuration shown in FIG. 1 will be explained. First, when a memory address that involves indirect addressing memory access as shown in FIG. ．． Valid flag section 42, data section 43. Data section 4
The contents of the corresponding areas of 4 are respectively data lines 41a.
, 42a, 43a, 44a. The comparison/judgment section 52 compares the contents of the memory address field 11b held in the address register 11 with the address information read out from the 7-dress tag section 41 to the data line 41a to check for coincidence/mismatch. If they do not match, or if they match but the V flag read from the valid flag section 42 to the data line 42a is in an invalid display state, the output from the multiplexer 51 is prohibited. In this case, as shown in FIG. 2, memory access to the memory 12 is performed twice, and the address register 1
The data in the data area in the memory 12 that is indirectly specified by the memory address held in 1 is registered in the area in the data section 44 specified by the field 11a of this memory address. At this time, the contents of the field 11b of the same address are registered as address information in the address tag section 41 designated by the field 11a of the memory address, and the V flag of the valid flag section 42 is set to a valid display state.

Assume that the memory address is held in the address register 11 again in the above state. In this case, the contents of the field 11b from the address register 11 and the address information read from the address tag section 41 to the data line 41a are the same, and the V flag read from the valid flag section 42 to the data line 42a is in a valid display state. Therefore, the comparison and determination unit 52 determines that the target data is registered in the cache memory 40. When the memory address held in the address register 11 involves memory access using the indirect addressing method as described above, the comparison/judgment unit 52 receives an address method designation signal 52 indicating this.
a is supplied. Based on this signal 52a and the above determination result, the comparison/determination unit 52 selects the data line 43a.

A switching signal 52b is outputted to the multiplexer 51, which designates switching output of data on the data line 44a among the data lines 44a. As a result, the data read from the data section 44 to the data line 44a, that is, the same data as the data in the area in the memory 12 that is indirectly specified by the memory address held in the address register 11, is
The data is taken out from the multiplexer 51 to the outside of the cache memory device with only one access to the cache memory 40.

[Effects of the Invention] As detailed above, according to the present invention, data in an in-memory data area that is indirectly specified by a memory address used for memory access is like data in an in-memory data area that is directly specified. When it is registered in the cache memory area specified by the specified field of the same address and this memory address is used as a memory address for indirect specification, the above indirect specification data is selectively retrieved by cache memory access of ll111i1. Because it is done,
Memory access using indirect addressing can be performed at high speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a cache memory device according to an embodiment of the present invention, FIG. 2 is a diagram illustrating memory access using a direct addressing method, and FIG. 2 is a diagram explaining memory access using an indirect addressing method. FIG. 4 is a block diagram showing a conventional example. DESCRIPTION OF SYMBOLS 11...Address register (AR), 12...Memory, 40...Key lock memory, 41...Address tag section, 42...Valid flag section, 43.44...
Data section, 51... Multiplexer (MUX), 52
... Comparison and Judgment Department. Figure 2 3rd! ! I

Claims (1)

[Claims] A direct addressing method that uses data in a first data area in a memory specified by a memory address as target data; In a system that performs both memory accesses using an indirect addressing method, in which a second data area in the same memory in which target data is stored is used as a new memory address, the first data area is directly specified by the memory address. a first memory means for registering data in the second data area indirectly designated by the memory address in an area corresponding to the first field at the same address; and a third memory means for registering the contents of the second field of the memory address in an area corresponding to the first field of the same address; 1 field to refer to the cache memory, and based on the reference data from the third memory means in the cache memory and the contents of the second field of the memory address, the target data exists in the cache memory. a determining means for determining whether or not the first or second memory access in the cache memory is performed according to the determination result of the determining means and an addressing method designation signal indicating whether the memory access is a direct addressing method or an indirect addressing method; 1. A cache memory device comprising: selection means for selecting reference data from two memory means; and selection means for selecting reference data from two memory means.