JPH01142946A - Logical simulating method - Google Patents

Abstract

PURPOSE:To delete unnecessary processing by storing events which are not selected among events based upon an internal state temporarily and using them according to a change in the internal state. CONSTITUTION:Events stored in an event storage means 13 are added to a buffer 9. Then the events are read out in order as long as there are the events stored in the event buffer 9 and selected only at the time of a trailing edge of the clock signal. When an event is selected, connection information in a connection information memory 15 and a function evaluation selecting means 14 are used to find the identifier of a function evaluating means and transfer it to a function evaluation identifier buffer 16. When no event is selected, the event is stored in the event storage means 13. When the event buffer 9 becomes empty and there is the selected identifier of the function evaluating means in the function evaluation identifier buffer 16, an evaluating means 17 evaluates a function element or function block. Said operation is repeated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is applicable to the design of logic devices, including timing,
The present invention relates to a logic simulation method for verifying the functional and logical operation of a logic device.

Conventional technology In recent years, with the progress of integrated circuit technology, LSI or ultra-LSI
Using I, it has become possible to realize a logic device that is complex but has low production costs and high added value. However, in the development of such logic devices, reducing development and design costs, which are increasing due to their increased scale and complexity, has become a challenge. Furthermore, as the process progresses, it becomes extremely difficult to modify or change the design, so improving reliability from the initial stage of design has become an issue. Against this background, emphasis has been placed on increasing the precision and speed of logic simulations for verifying the functions and logic designs of logic devices.

In general, a logic device is expressed using a connection relationship between inputs and outputs of functional elements such as logic gates, memory elements, registers, and counters, or functional blocks that perform more complex operations. In logic simulation, the logic values of the signals in each part of the logic device are determined for each unit time by inputting the specifications of the logic device and a test pattern representing a temporal change in the input signal to the logic device. Conventional logic simulation is performed using a compilation method in which specifications of a logic device are compiled and executed, or an event-driven method. The compilation method avoids complicated processing, simplifies processing, and is fast, but it is difficult to handle delays. For this reason, recently, many event-driven methods have been adopted, which can be applied to any circuit and are suitable for timing analysis.

In the event driven system, an event indicates which wire of a logic device a signal change has occurred. Further, event-driven means to selectively evaluate the functions of functional elements and functional blocks based on the occurrence of the event and the connection relationship inside the logic device. Event-driven logic simulation focuses on changes in signal values on wiring that connects input terminals of a logic device and input/output terminals of functional elements or functional blocks. When and which wiring signal values change is stored in a schedule table. Only when the signal value on the wiring changes, the operation of the functional element or functional block to which the wiring destination is input is evaluated to determine its output value and internal state. When the output value changes, the wiring through which the output value is propagated and its signal value are stored in the schedule table based on the delay information.

A simulation is performed by repeating such processing every unit time.

FIG. 4 is a flowchart showing an example of a process for evaluating the operation of a circuit in a simulation for each unit time in the conventional event-driven method as described above. The flow of processing will be explained below using FIG. 4.

First, it is determined whether there is an event scheduled to occur in advance at the relevant time. If there is no event, the simulation is ended and the simulation proceeds to the next time (step 1).

If there are scheduled events, read the events in order from the list of scheduled events Step 2
), the internal state is updated based on the change in the corresponding signal value (step 3).

Next, the functional elements constituting the logical device, the functional elements to which the event propagates according to the connection relationships between the functional blocks, and the functional evaluation means for evaluating the functional blocks are selected (step 19).
). If no function evaluation means is selected, the next event is read out (step 5). If one or more functional evaluation means are selected, functional evaluation is performed using them (step 6).

As a result, when a new event occurs, the event is scheduled based on the delay information of the relevant functional element and functional block, and when no new event occurs,
The next event at that time is then read (step 7.8).

Problems to be Solved by the Invention The event-driven method using the method described above is an efficient method in the sense that it selects and evaluates only the operation of the part where the event occurs in the logic device. However, there are cases where it is known in advance that the internal state and output value of the functional elements or functional blocks that constitute the logic device do not change unless the control signal changes, or there are cases where the circuit is a completely synchronous circuit. In this case, even if the values of other input signals change, it is not necessary to evaluate the internal state and output value as long as the control signal or clock signal of the corresponding functional element or functional block does not change. Therefore, it is wasteful processing to evaluate these functional elements and functional blocks one by one based on events that occur in input signals other than control signals and clock signals.

Such wasteful processing is performed when the functional block to be evaluated is
This is particularly a problem when the processing time required to evaluate the motion is long when the motion is complex like u.

In contrast, a simulation control method may be considered in which functional elements and functional blocks are evaluated by focusing only on control signals or clock signals.

In this method, since it is unknown whether or not there has been a change in the input signal since the last evaluation, it is necessary to evaluate the functional element or functional block whenever the control signal or clock signal changes. This may conversely increase unnecessary processing when the frequency of the clock signal is high.

Conventional event-driven logic simulation has the above-mentioned problems.

In view of the above problems, the present invention provides an efficient logic simulation method that reduces unnecessary processing in the event-driven method.

Means for Solving the Problems In order to solve the above problems, the logical simulation method of the present invention evaluates functional elements or functional blocks driven by events with respect to events that occur every unit time. activation condition determining means for determining whether or not an internal state or an output value is likely to be updated based on the internal state of the logic device; and a functional element that receives the event as input and is driven by the event; Function evaluation selection means for selecting a function evaluation means for evaluating a functional block; and event storage means for storing the event; Selecting only the event that drives the function evaluation means from the events using the activation condition determination means, and using the selected event as input,
A set of function evaluation means to be executed is obtained using the function evaluation selection means, and the corresponding functional elements and functional blocks are evaluated, and for events that are not selected as a result of the determination by the activation condition determination means, This is a method of storing the event in the event storage means.

Operation According to the method described above, the present invention can omit evaluation of a functional element or a functional block when the control signal is off or the clock signal is not a rising edge.

When the control signal is on or when the clock signal is on the rising edge, a functional element or functional block is selected and evaluated based on the stored past event and current event. In this way, it is possible to improve the efficiency of logic simulation by performing only the minimum necessary evaluation.

Embodiment Hereinafter, as an embodiment of the present invention, a method for activating a function evaluation means for evaluating a functional block that operates in synchronization with a clock signal will be described with reference to the drawings.

FIG. 1 is a flowchart showing logical simulation processing for each unit time. FIG. 2 is a flowchart of the process of selecting the function evaluation means based on the event in step 4 of FIG. 1 and the internal state of the logic device. FIG. 3 is a configuration diagram of a simulator that implements the logic simulation of this embodiment. In FIG. 3, 9 is an event buffer that holds current events, and 10 is an internal state memory that holds the internal state of the logic device. It is assumed that the internal state memory 10 of this embodiment has an edge flag indicating whether the current state of the clock signal is a rising edge. 11 is an event/signal value schedule that schedules events and signal values after their changes in the order of occurrence; 12 is an activation that determines whether an event drives a functional element or a functional block based on the state of a clock signal; The condition determining means and 13 are event storage means. 14 is a function evaluation selection means for selecting an identifier of a function evaluation means for evaluating a functional element or a functional block driven by an event; 15 is a connection information memory for storing connection information between functional elements and functional blocks constituting a logical device; 16 is a function evaluation identifier buffer that holds the identifier of the function evaluation means; 17 is an evaluation execution means that executes evaluation by the corresponding function evaluation means according to the identifier of the function evaluation identifier buffer 16; and 18 is a function that is delayed when a new event occurs. Event and signal value schedule table 11 for events and signal values based on information
This is an event/signal value scheduling means that schedules events and signal values.

Hereinafter, the flow of the logical simulation processing for each unit time of this embodiment will be explained using the flowcharts of FIGS. 1 and 2 and the configuration diagram of FIG. 3.

First, it is determined whether an event scheduled in advance to occur at the relevant time is scheduled in the event/signal value schedule table 11.

If there is no event, the simulation is ended and the simulation proceeds to the next time (step 1).

If there is a scheduled event, read the event from the event/signal value schedule 11 and transfer it to the event buffer 9 (step 2); at the same time update the internal state memory 10 based on the signal value scheduled with the event. I do. The edge flag indicating a rising edge is reset before updating the internal state. In particular, when the logical value of the clock signal is updated from 0 to 1, an edge flag is set (step 3). Next, a function evaluation means for evaluating the functional elements and functional blocks to which the event propagates is selected according to the internal state of the logic device and the connection relationship between the functional elements and functional blocks (step 4).

This process will be explained using the flowchart shown in FIG.

First, the event stored in the event storage means 13 is added to the event buffer 9 (step 41).

It is determined whether or not there is an event in the event buffer 9 (step 42), and as long as there is an event, it is read out in order (step 43).

The edge flag in the internal state memory 10 is referred to to determine whether the clock signal is a rising edge. If the clock signal is a rising edge, select the event;
Otherwise, do not select it.

This process is performed by the activation condition determining means 12 (step 44).

If an event is selected, the connection information in the connection information memory 15 and the function evaluation selection means 14 are used to obtain the identifier of the function evaluation means activated by the event, and this is transferred to the function evaluation identifier buffer (steps 45 and 46). ).

If no event is selected, the event is stored by the event storage means 13 (step 45.47).

Subsequently, unless the event buffer 9 is empty, the next event is read (step 48).

If the function evaluation identifier buffer 16 is empty when the event buffer 9 is empty, the process ends (step 5).
.

If the function evaluation identifier buffer 16 contains the identifier of the selected function evaluation means, the corresponding function evaluation means is used to evaluate the functional element or functional block. This process is performed by the evaluation execution means 17 (step 6).

As a result, if no new event has occurred, the simulation for that unit time is ended and the simulation proceeds to the next unit time (step 7). A: If a new event occurs, the event and signal value are scheduled in the event/signal value schedule table 11 by the event/signal value scheduling means 18, and the process ends (step 8).

The activation conditions for the activation condition determining means 12 include, in addition to the rising edge of the edge trigger clock signal, the falling edge of the clock signal, the on-level state of the level trigger clock, and the on-state of the control signal.

Furthermore, in the case of a multi-phase clock, the determination is made based on activation conditions that refer to different clock signals for each event.

Effects of the Invention As described above, the present invention is an event-driven logic simulation method, which selects events based on internal states, temporarily stores unselected events, and changes them according to changes in internal states. By using this method, unnecessary processing in conventional event-driven logic simulation methods can be reduced and efficient logic simulation can be realized.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing the logic simulation processing for each unit time in the logic simulation method according to an embodiment of the present invention, and FIG. 2 shows the events and internal parts of the logic device in step 4 of FIG. FIG. 3 is a flowchart of a process for selecting a function evaluation means based on the state. FIG. 3 is a block diagram of a logic simulator that implements a logic simulation method according to an embodiment of the present invention. FIG. 3 is a flowchart showing logical simulation processing at each time in a logical simulation method. 9...Event buffer, 10...Internal state memory, 11...Event/signal value schedule, 12
...Starting condition determining means, 13...Event storage means, 14...Function evaluation selection means, 15.
... Connection information memory, 16 ... Function evaluation identifier buffer, 17 ... Evaluation execution means, 18
...Event/signal value scheduling means. Name of agent: Patent attorney Hakao Nakayashiki Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] In a method of performing logic simulation of a logic device using an event-driven method, when a functional element or a functional block driven by an event is evaluated for an event that occurs every unit time, the internal state or output value is updated. activation condition measuring means that determines whether or not there is a possibility of the event occurring based on the internal state of the logic device; and function evaluation means that receives the event as input and evaluates a functional element or functional block driven by the event. function evaluation selection means for selecting the event; and event storage means for storing the event; is used to select only the events that drive the functional evaluation means, and using the selected events as input, obtain a set of functional evaluation means using the functional evaluation selection means, and evaluate the corresponding functional elements and functional blocks. A logic simulation method characterized in that the events not selected as a result of the determination by the activation condition determination means are stored in the event storage means.