JPH01140315A - Semiconductor device - Google Patents

Abstract

PURPOSE:To realize a low transient current now being affected by dispersion in manufacturing, etc., by controlling the charge/discharge of a load capacitance by an arbitrary constant current decided in advance. CONSTITUTION:The simultaneous fast charge of data lines are performed by a driving circuit DRV connected to the common line cl of a flip-flop that is a sense amplifier formed by a pMOST, and the driving circuit DRV is constituted of a current mirror circuit and a comparator. At this time, the output voltage of the current mirror circuit is compared with a comparison voltage decided in advance by the comparator, and the current mirror circuit is controlled by the output voltage of the comparator corresponding to the above result, and also, the current value of a constant current source in the current mirror circuit is varied by a source voltage or a manufacturing condition. Since it is possible to control a charge/discharge current arbitrarily by controlling the current value of the constant current source in the current mirror circuit, the transient current can be suppressed even when the dispersion is generated in the manufacturing, and the design of a chip can be performed easily.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a circuit suitable for suppressing transient current or suppressing the amplitude of pulse voltage.

[Conventional technology]

Conventionally, when charging and discharging a large load capacity at high speed, it has been considered a problem that the transient current becomes excessive. For example, in dynamic random access memory (hereinafter referred to as DRAM) that uses dynamic memory cells, there is a problem with excessive transient current when charging and discharging a large number of data lines at once. 1986, Solid State Device Conference Digest, pp307-310.
A voltage limiter circuit system as shown in FIG. 1 has been proposed.

[Problem that the invention seeks to solve]

However, this method charges the data line using the internal power supply voltage, which is obtained by lowering the external ffl'gm voltage within the chip, so it only achieves a lower current by effectively lowering the power supply voltage. Charging was left unchecked.

Furthermore, the charging transient current, which changes in response to fluctuations in the transistor's load driving ability due to variations in the gate length or threshold voltage of MOS transistors due to manufacturing variations, is not actively controlled, so there is a limit to lowering the current. was there.

An object of the present invention is to provide a semiconductor device that charges and discharges a load capacitor at a predetermined arbitrary constant current and achieves low transient current independent of manufacturing variations. Another object of the present invention is to provide a semiconductor device with low transient current and low power consumption by combining the present invention with a voltage limiter circuit system.

[Means for solving problems]

The above object is achieved by using a current mirror circuit controlled by input pulses as a load driving circuit.

This is achieved by driving the load with a constant current corresponding to a predetermined constant current source within the current mirror circuit. Furthermore, the current value of the constant current source in the current mirror circuit is controlled by the power supply voltage and the gate length L* and Vt of the MOS to reduce the transient current.

[Effect]

The current mirror circuit is not easily affected by changes in process conditions, and the current value of the constant current source in the current mirror circuit is controlled by the power supply voltage and the Lf of the MOS.

Since it is controlled by Vt, transient current can be reduced.

Furthermore, by limiting the 'w1 pressure, it is possible to maintain a low constant voltage, thereby reducing power consumption.

〔Example〕

An embodiment of the circuit of the present invention and its operation timing will be explained below with reference to FIGS. 1(A) and 1(B).

In DRAM, one of the data pair lines is connected to pMO8T according to the read information of the memory cell (there is an example of a memory cell consisting of one MO8T and one capacitor).
Charging is done using a well-known sense amplifier formed by In this case, for example, the latest Mega Pit DR
In AM, it is necessary to simultaneously charge 1024 pairs of data lines at high speed. The total capacity of the data lines is 500 to 10
Since it reaches 00 pF, overcurrent becomes a problem. This charging is performed by a drive circuit DRV connected to the common line cQ of a flip-flop, which is a sense amplifier formed of pMO8T. In this embodiment, this drive circuit is composed of a current mirror circuit and a comparator. There are characteristics. In the current mirror circuit, when aQz, which is controlled by a kind of inverter consisting of transistors Ql and Qz, is on, Q
When t is off, a current mirror circuit is formed between Qδ, the constant current source (i/n), and the output drive transistor Qo, and when Q2 is off and Ql is on, Qo is off. The current inlet of the current source in the mirror circuit is i/n, MO8
If the gate width of T is w/n and the gate width of Qo is W, the on-current of Qo is a constant current i. Even if W, gate length, or transistor threshold voltage changes due to variations in the manufacturing process, if I/n is kept constant, Q
.

The driving constant current is almost constant. Here, the constant current source is i/n
, w/n in order to reduce the current consumption and the occupied area, and the larger n is, the better.

The comparator is connected to a predetermined internal power supply Vcc (for example, 4
V) and the output voltage Vo.

VC! When L>Vo, the output of the comparator becomes a high voltage, and conversely, when VCL>VO, it becomes a low voltage. In addition, VC
L may be generated from Vcc (externally applied power supply voltage) within the chip.

The operation will be explained based on the above preparation.

In a normal DRAM, the data pair lines are set to approximately half the value of VCL during the precharge period, which is the so-called half-p+j charge method. It is precharged to 2. When a pulse is applied to one selected word line in this state, a minute differential read signal appears on each data pair line. This situation can be seen in Figure 2.
It is representatively shown with Oy Do symmetry. Then nMO
In the sense amplifier formed of 8T and pMO8T, the low voltage side is discharged to Ov, and the high voltage side is charged to VCL. The discharge is performed by applying a low voltage pulse to the common drive line cQ' of each nMO8T.

Here, only an example in which charging is performed by a pulse applied to the common drive line CM of pMO8T will be described below. aQ is driven by applying an input pulse φ. When the input pulse φ turns on (high voltage is input), the control circuit AN
The output voltage of D becomes a high voltage, the gate voltage Va of Qo becomes the output voltage Vs of the constant current source, and Qo drives the load with a constant voltage i. As a result, the load voltage Vo is Vat, /
2 at a constant speed, but when it exceeds vCL, the comparator is activated and the output of the control circuit AND becomes a low voltage, Ql is turned on, QZ is turned off, Qo is turned off, and VO is almost clamped to VCL. It ends up. As a result, one data line of each data pair is charged from vCL/2 to approximately VCL.

According to the embodiments described above, since the data line can be charged with a substantially constant current, the data line can be charged at high speed without increasing transient current. Also, by keeping io constant,
Even if there are fluctuations in power supply voltage or manufacturing variations, the effects can be minimized. Furthermore, since the data line voltage can be kept low, power consumption is also reduced.

As described above, the drive circuit using the current mirror circuit allows the data line to be charged with a nearly constant current.

Figure 2 shows the transistors constituting the current mirror with Qδ
This is an embodiment in which a plurality of MOS transistors with +Q< are used. According to this embodiment, since the gate voltage of the QD can be increased, its dimensions can be reduced and a large output power current can be produced.

FIG. 3 shows a specific embodiment of the constant current source CC.

This embodiment uses an NPN bipolar transistor QaztQ
B2 and resistors R1 to R4. Explain the operation. A pace emitter voltage VBE (usually 0.8 V) of Qax appears at node 11, and this voltage and R
3 determines the current flowing through R2 and determines the voltage value at node 10. VBE drop of voltage at node 10
2, and the current io is determined by this voltage and R4. For example, Ω for Rz=10, Ω for Rz=4, Rs=8
and R4=4. Node 11 has VB+!
= 0.8 V appears at 8 Ω mA, and the voltage value at node 10 becomes 0.8 V + 4 Ω mA.
X0.1mA=1.2V. The voltage at node 12 is 1
．． 2V-0,8V=0.4V, and the current is 4Ω.According to this embodiment, by utilizing the VBE of the bipolar transistor with extremely small variations between wafers and between rods, the influence of fluctuations in manufacturing conditions and power supply voltage Vcc is minimized. I don't accept it. Further, since the voltage at the node 10 is determined by the resistance ratio of Rz and Rs, it becomes an extremely stable constant current source that is not affected by manufacturing variations in the resistors. In order to charge the data line with a constant current even with a current mirror circuit that has a built-in stable constant current source, MO8 in Figures 1 and 2 must be used.
TQo is in the saturated region (I Vo - Vcc l > IV
It is preferable to operate at s-Vcc VT l ). However, as shown in FIG. 4, this condition may not be satisfied over time depending on the operating conditions and the like. That is, when the potential of vO rises from Vct,/2 and becomes higher than the voltage of Vs 1Vtl, (V
t is the threshold voltage of Qo, which generally has a negative value because it is a P channel type), l Vo VCal < I Vs
-Vcc -VT l, and MO8Qo operates in the non-saturation region. As a result, the current i becomes smaller and Vo becomes V
The time to reach CL (4V) also becomes slower. These problems become noticeable when the power supply voltage is as low as 4.4■, the Qo channel length L□ is larger than the standard value, and ■ is high. ? li
When the source voltage is low, Lx is smaller than the standard value, and Vt is low, it operates in the saturation region, but due to the dependence of the drain current on the drain-source voltage, it becomes faster than necessary and causes the problem of increased transient current. may occur. This problem is particularly likely to occur in the embodiment of FIG. Therefore, as shown in FIG. 4, the current value io of the current source CC is made large when L6 is thicker than the standard value and Vt is high, and is made small when L8 is small and Vi is low. Further, the above problem can be solved by controlling the current value to become smaller as the power supply voltage increases.

FIG. 6 shows an example thereof. Power supply voltage, Lt.

■, detection circuit VD and receiving its output signal 100;
It consists of a current source C8 that outputs u.

The detection circuit VD of the power supply voltage, Lx-Vt, is the power supply voltage, Lx-Vt.
This circuit controls C8 and io by controlling the voltage value or current value of the output 100 when g and Vt fluctuate. For example, if the power supply voltage is high < Lg is thinner than the standard value, ■
, decreases, the voltage value of 100 or the current value is decreased to decrease io. In the opposite case, increase io.

According to this embodiment, it is possible to charge the data line with an optimum current in accordance with fluctuations in power supply voltage and manufacturing variations in Lg and Vt, and it is possible to reduce transient current or increase speed with the same transient current.

FIG. 7 shows another embodiment. Constant voltage circuit P channel M OS Q zoo, N channel M OS Q
It consists of VD made up of tot, NPN bipolar transistor QBIO, and C8 made up of resistor Rzo. The constant voltage circuit VL uses a voltage limiter circuit system disclosed in Japanese Patent Application No. 57-830022, etc., and its output VoL remains a constant voltage even if the power supply voltage fluctuates. The operation is at the node 100 with the drive capacity ratio of Qzoo and Qtot.
Determine the voltage value of Q B 10 base of that voltage value.
Emitter voltage VBE (0.8V) drops at node 10
Appears in 1. The current io is determined by the voltage value and Rzo. For example, let Vcc=Vc+,=4v and -Ql
If the driving capacity ratio of oo and Qtot is 1=1, the node 100 is 2V and the linode 101 is 2V-0, 8V=1
．． If the power supply voltage Vcc fluctuates with this kind of connection, Qlo
The gate voltage of t also changes, and the driving ability changes.

Rinode 100 whose driving capacity increases as Vcc increases
voltage value decreases. When Vcc decreases, the driving ability of the QIOI decreases, and the voltage at node 100 increases. As a result, if Vcc is high.

io can be small, and if it is low, it can be large.

According to this embodiment, the value of the current io can be freely set based on the drive capability ratio of Qloo and QIOI and the resistance value of Rzo.
Further, when the power supply voltage is high, the current value of io can be made small, and when the power supply voltage is low, io can be made large. As a result, the charging time of the data line can be made faster than necessary, and the transient current can be prevented from increasing.

FIG. 8 shows a concrete example of the constant voltage circuit VL of FIG. 7. In FIG. VL is composed of P-channel MO5QtozNPN bipolar transistors QBII to QBx11. The operation of this circuit is such that when Vcc is applied and the voltage rises, VCL also rises via Q102. VCL
When the voltage value of 0.8 VX5 (VBE of Qutt to Qata) = 4 V L knee, Qanx”Qaz
a becomes conductive, VCL stops rising, and is limited to a constant voltage of 4V. Other operations are the same as in FIG. 7.

According to this embodiment, the constant voltage circuit becomes more concrete and more realistic.

FIG. 9 shows MO8Qzog on the P channel in FIG.

NPN bipolar transistor QBI~Qaz, resistor R
This is an example in which z to R4 are added. QBI, Qazt
The circuit composed of R1 to R4 is the same constant current power supply circuit as in FIG. 3 and operates in the same manner. In this embodiment, the voltage value of the node 102 is determined by the driving ability of Qzoa and the current of the constant power supply. What is this voltage value?

Since the current of the constant current source has no Vcc dependence, Vcc
It fluctuates according to the Furthermore, Qloz's L g gV
It can also be changed depending on manufacturing variations in t.

That is, when Lm is thinner than the standard value and Vt is low, the voltage value of the node 102 where Q 108 has a large driving ability becomes high, and vice versa. This node 10
2 is input to the gate of Q sat, and the same operation as in FIG. 8 is performed.

According to this embodiment, not only can the current value io be controlled against fluctuations in the power supply voltage as in FIG. 8, but also the current 10 can be controlled against manufacturing variations in Lt and Vt, resulting in even more stable It becomes possible to charge the data line.

FIG. 10 shows another embodiment of the invention. constant voltage circuit v
r4. MOS Qxoo ”Qloew Qaxee
VD made up of R11 and C8 made up of Q107
Tode natte &'ru* VLQxooy Qnoty Q
ato t Rzz (7) The operation is similar to that shown in FIG.

That is, as power supply voltage Vcc increases, the value of the current flowing through node 103 decreases, and as Vcc decreases, it increases. A current mirror circuit is formed by this current source and Q1041 and Q105, and a current that is twice the driving ability of Qxos (effective gate width/effective gate length)/Q104 of the current flowing through node 103 flows through node 100. The output current io is controlled by a second current mirror circuit formed by this, Q sos, and Q107. At this time, if the channel length Lx of Q106 is designed to be so thick that manufacturing variations can be ignored, manufacturing variations in Q104 can be reflected in the current value flowing through the node 100. In other words, if Lg of Q104 is thin and ■ is low, Q1
The voltage of the linode 103 where the driving ability of 04 is large becomes high, and becomes low when Lg is thinner than the standard value and ■ is high. Since the gate length of Qlos is designed to be large enough to ignore these manufacturing variations, the current at the node 100 is small in the former and large in the latter, and the same effect as shown in FIG. 9 can be obtained. Of course, the gate length L6 of Qzofu
It goes without saying that the same effect can be obtained by making the diameter thicker.

This embodiment also provides the same effects as in FIGS. 6 and 9.

FIG. 11 shows Q108 in FIG. Instead of Qxo7, Qlos, QB17. This is an example in which QIIO and Rto are added. The other circuits are the same as in FIG. 10, except that the Lg of Qxob is the same as Q104.

The voltage at node 100 is Q sos (7) V t and QBI? VaF! It is determined by the driving ability of Qxob. Now, assume that Lg and Vt are both standard values, and Vcc is also a standard value of 5V. Q106 and Qxoa so that only the voltage of the sum of Qxos(1)Vt and QB17(7)VBE(7) is output to node 100 at this time.

Determine the driving capacity ratio of Q a 17. The voltage at node 101 at this time is Vt of QIOII since V[IE is canceled, and by this Vt and Rso, i
.

is determined. For example, when the power supply voltage Vcc becomes low, the first
0, the current flowing to the node 103 increases, and the current flowing to Qxob forming the current mirror circuit also increases. As a result, the voltage at node 100 becomes higher and io becomes larger.

Conversely, as Vcc increases, io decreases. Also QIO
The manufacturing variation in Vt of δ becomes the voltage of the node 101 as it is. That is, when Lg is thinner than the standard and Vt is low, the current 10 is small, and when it is high, it becomes large.

This embodiment also provides the same effect as in FIG. 10.

The following embodiment is an example of constant current generation using a comparator in combination with a voltage limiter. However, even when a voltage limiter is not used (when there is no output loop of the comparator), the mirror circuit can be controlled by the input pulse φ, so that a constant current is possible.

Also, as the response time of the comparator is made faster than the response time of the output VO, ■0 can be brought as close as possible to VCL, so
In some cases, the comparator may be configured with a bipolar transistor suitable for high speed. Also, n M O
Common drive line CQ of sense amplifier configured with S “L”
The idea of the present invention can also be applied to the drive of . For example, if both waveforms are made completely complementary, noise coupled from the data line to other conductors (Si substrate word line, etc.) can be completely canceled out, and a memory with a wide operating margin can be designed.

Furthermore, the present invention is not limited to application to DRAM data line charging circuits, where transient currents are particularly problematic.

If applied to the data output section of all memories with a multi-bit configuration (a configuration in which multiple data outputs are output from one chip) or the address output section of a microcomputer, etc., it is effective as a countermeasure against transient currents.

〔Effect of the invention〕

By controlling the current value of the constant current source of the current mirror circuit as described above, it is possible to arbitrarily control the charging and discharging ff1ffi current, which has conventionally been left unchecked.

Transient currents can be suppressed, and therefore noise within the LSI chip is reduced, making chip design easier, and also for the user, since noise from chips mounted on the card is reduced, card design is also easier. Furthermore, since constant voltage output pulses can be obtained at low voltage, the power consumption of the chip can also be reduced.

[Brief explanation of the drawing]

Figures 1, 3, 6 to 11 are diagrams showing embodiments of the present invention, Figure 2 is a diagram explaining the operation of Figure 1, and Figure 4 is a diagram explaining problems in operation. FIG. 5 is a diagram illustrating a solution to the problem. DRV...constant current, constant voltage drive circuit, CC...constant current source circuit, Vcc...power supply voltage, VCL...comparison voltage, Qt~Q soa...MOS...transistor, Qaz~ QB17...Bipolar transistor.

Claims (1)

[Claims] 1. A semiconductor device characterized in that at least one current mirror circuit is formed by at least one or more pulse input voltages, and the output current of the current mirror circuit is a constant current. A comparator compares the output voltage of and a predetermined comparison voltage, and controls the current mirror circuit with the output voltage of the comparator according to the result, and controls the current value of the constant current source in the current mirror circuit. A semiconductor device characterized by changing the voltage depending on the power supply voltage or manufacturing conditions.