JPH01138699A - Single chip microcomputer - Google Patents

Abstract

PURPOSE:To check the margin of an EEPROM with a simple tester by providing a margin check program means incorporated in a ROM and a D/A converter, which is connected to a EEPROM gate, on a chip. CONSTITUTION:A ROM 2 where an EEPROM margin check program 8 is incorporated and a D/A converter 7 connected to the gate of an EEPROM 3 are constituted on the chip adjacently to a RAM 1. Then, an analog voltage applied to the gate of the EEPROM 3 is generated in a chip. Write and read operations of the EEPROM are automatically performed by the program 8 in the ROM 2 without external signals. Consequently, the burden on a tester is considerably reduced by this single chip microcomputer, and the margin of the EEPROM is checked with the simple tester.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a single-chip microcomputer incorporating EEPROM, ROM, and RAM. In particular, it relates to a built-in EEPROM memory test.

(Prior technology) E built in a single-chip microcomputer
During the manufacturing process, EEPROMs are tested 2 to 3 times to ensure operating margins.
This is done for all bits. What is the Marnon test?
After writing 01# and 0'' to the EPROM, the threshold voltage is measured and compared with the standard threshold voltage to test whether there is sufficient operating margin. Yoshi,
The memory operation of the EFJPROM is guaranteed, and it is also possible to estimate the lifespan of the memory.

Here, the threshold voltage has conventionally been measured using a general-purpose tester according to the following procedure. First, the VDD and GND of a single-chip computer
Connect a general-purpose tester to terminals such as , clock, and serial I10, and send signals at a predetermined level and timing to turn the chip into an operating state and set all bits of the EEPROM to 1".
Write. Next, put the single chip computer into test mode. 7. From a general purpose tester. O
A voltage of V is generated and applied to the serial I10 terminal of the single-chip computer. Inside the chip, 7. Send a signal so that Ov is applied. Assuming that the EEFROM threshold voltage after writing is 6.75V, E
The FET of the memory cell of the EPROM is in the ON state, and a 1" state is output to the sense amplifier connected to the bit line.The single-chip micro combinator is input from the general-purpose tester through the serial I10. According to the signal, the output status of each word and each bit of the EEPROM is output to the path and transferred to the tester through the serial I10.A voltage of 7V from the general-purpose tester is applied to all cells of the EEPROM, and all After reading the bits and transferring them to the general purpose tester,
The 6.9v voltage test is then performed using a procedure similar to that described above. In this test, the voltage applied to the memory cell (r-) of the EEPROM is 7. Starting from Ov, the above-described procedure is performed at intervals of 0.1v until reaching 4.0v.

Assume now that the threshold voltage of a certain EEPROM bit on a certain word line is 6.75V. Then, for this bit, the voltage applied to the gate is 7. Ov,
At 6.9v and 6.8v, the sense amplifier outputs are both in the 1" state, and below 6.7v, they are in the "0# state. Therefore, the threshold voltage for this bit is 6.7v
It is determined that the voltage is between 6.8v and 6.8v. In the margin test, if the threshold voltage in the "1" writing state is a constant value, for example 6.5V, as the standard value, and is equal to or higher than this standard value for all bits, the chip is determined to be good.

When the 1n write state test is completed, the next step is to test the 0# write state. First, a general-purpose tester gives a signal to the chip and writes 0# to the bits of all EEFROM memory cells. Next, Similarly to above, insert the chip into E
The EPROM is placed in a read state and a voltage of Ov is applied to the dirt of the EEPROM.゛If the threshold voltage in the 0# write state is -1.5v, the FET is ON.
state and outputs "1" to the sense amplifier output. On the other hand, the threshold voltage in the “0” write state is +
When the voltage is 0.5v, the FET is in the OFF state and outputs 0'' to the sense amplifier output.In this way,
°゛0″0″ write threshold voltage of each focus is Ov
It can be determined whether it is below, and if the standard value is OV, then 01
If even one of the above bits is present, the chip is determined to be defective.

(Problems to be Solved by the Invention) However, in such a conventional BEFROM margin test, a signal must be sent from a general-purpose tester to operate a single chino 7' microcomputer, and the test program of the general-purpose tester is complicated. Become. or,
The test time is long, and it is necessary to use an expensive general-purpose tester for a long time, which increases the cost of the test. Furthermore, 11 points indicated that since the analog voltage was supplied from outside the chip, erroneous measurements due to noise were likely to occur.

Incidentally, there are methods for testing the built-in memory of a single-chip microcomputer as disclosed in Japanese Patent Laid-Open No. 145799/1982 and Japanese Patent Laid-open No. 168051/1982. The former generates a RAM test pattern inside the chip, and the latter allows the bus inside the chip to be driven directly from an external terminal, both of which lighten the burden on general-purpose testers. however,
These prior art techniques are insufficient for tests that require the application of analog voltages, such as EEPROM margin tests.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention aims to solve the problems described above.
The margin check program means built into M and the E
A D/A converter connected to the EPROM date is provided on the chip.

Further, the D/A converter generates an analog voltage by dividing a resistor by the word line of the RAM.

(Function) According to the present invention, by configuring the D/A converter and the mernon check program means in the ROM on a chip, an analog voltage to be applied to r-) of the EEPROM can be generated within the chip. Further, by using the ROM margin check program means, writing and reading operations to and from the EEPROM can be performed entirely by the operation of the microcomputer within the chip without applying any external signals. Therefore, with this single-chip microcomputer, the burden on the tester can be greatly reduced, and it is possible to perform a non-check of the EEPROM with a simple tester without using a general-purpose tester.

(Embodiment) FIG. 1 is a block diagram of a single-chip microcomputer according to an embodiment of the present invention. This is a single-chip microcomputer that integrates a 128-byte RAM 1.3, a byte ROM 2.2, a byte EEPROM 3, an ALU 4, and various registers on one chip. This chip has a serial l10 (SIO) terminal, a power supply (vD
D) terminal, reset (RES) terminal, clock (CLK
) terminal, GND terminal, etc. The high voltage generating circuit 5 is a circuit that generates a high voltage for writing into the EEPROM and a voltage for margin checking. A voltage approximately 1.8 times VDD is extracted from this high voltage generation circuit 5, and the reference voltage vREF of the D/A converter 7 is
The vREF line 6 is connected so that. D/A converter 7 is connected to the word line of EEPROM 3,
The output voltage of the D/A converter 7 is applied to the gate via the word line of the EEPROM 3. The D/A converter 7 is provided adjacent to the RAM 1 on the chip. RAM 1 is 128 words x 8 in this example.
It is composed of bits and has 64 to 128 steps.
The number of bits is appropriate for configuring a /A converter. FIG. 2 shows a D/A controller according to an embodiment of the present invention.
It is a block diagram of the evening. Here, the D register 11, word decoder 12, and RAM memory cell 13 are the constituent elements of a RAM in a single-chip microcomputer. The difference lies in that a D/A converter 7 is provided at the right end of the RAM memory cell to generate an analog voltage by dividing a resistor. FIG. 3 is a mother turn diagram of a D/A converter according to an embodiment of the present invention. The N+ diffusion layer 14 on the chip constitutes a resistor.

A current flows from vREF 15 to GND 16, forming a resistance-divided potential for each word line 17 position. In other words, if there are 128 word lines, the resistance will be 128.
A voltage divided into two is generated. When any word line 17 of the RAM is selected and becomes HIGH, FET I
& is turned ON, and the resistance-divided potential is outputted to the analog output vA20 through the aluminum wire 19. Here, RAM
As shown in FIG. 2, the word line selection is performed by the word decoder 12 of the RAM by applying a 7- to 8-bit digital signal to the D register 11, which is an address register of the RAM.

The analog voltage of the D/A converter/S-7 output is EEFR.
Applied to the word line of OM. FIG. 4 is a circuit diagram of an EEPROM according to an embodiment of the present invention. An EEPROM memory cell has a word line 22 connected to the dart of an FET 21 and a bit line 23 connected to the drain of the FET, which are formed in an matrix shape. FE
The intermediate electrode of T21 is a floating gate, in which charges or holes are stored and digital signals are stored by turning FET21 on or off. The word line 22 is connected to a decoder 24, and the - book is selected by a signal from the (BA) register. An analog voltage line 25 which is the output of the D/A converter is connected to the decoder 24, and one word line selected by the decoder has an analog voltage v
A is applied. The bit line 23 is connected to the sense antenna 76.
26 and the stored contents are read out. The ROM 2 stores an EEPROM machine check program 8 as well as application programs necessary for the operation of this chip. This margin check program writes a 1'' or 0'' signal to the FET of the EEPROM, generates an analog voltage using the D/A converter, reads the EEPROM by selecting a word line, and outputs the read signal externally from the serial I10 terminal. Procedures such as output are executed inside a single-chip micro combinator. FIG. 5 is a flowchart of a mernon check program according to one embodiment of the present invention. The operation of EEPROM margin check will be explained below according to this flowchart.

The mernon check program inserts the chip into a simple tester, applies predetermined signals to the chip's power supply V, DIGND, clock, and reset terminals, and gives a predetermined signal to the serial I10 terminal, and then inserts the chip into a simple tester, applies a predetermined signal to the serial I10 terminal, and checks the mernon check in the ROM.・
Start by starting the program. First, E
Write 01” to all bits of EPROM. Next, R
According to the address of AM, the analog voltage VA=7. OV occurs. This voltage is applied to the decoder of the gEPROM and then to the word line of the selected EEPROM and applied to the dart of FET 21. And E
The output of the sense amplifier of the EPROM is read. At this time, if the threshold voltage of the FET is 7.0V or less, the FET will be in the ON state and the sense amplifier output will be "1#".
If it is above, the FET i head becomes FF state and the sense amplifier output becomes 0". This result is compared with the standard value. For example, the standard value of the threshold voltage is 6.5V.
, the sense amplifier output is '” at vA=6.5v.
1", it means that the threshold voltage of that bit is 6.5V or less, and it is judged as "defective". If the sense amplifier output is "O#", the threshold voltage of that bit is 6.5V or less. .5v or more, and is judged as 'good'.In this way, the output of the sense amplifier is compared with the standard value and then output to a simple external tester through the serial I10. The tester records this result. All the word lines of the EEPROM are selected one after another, and a read operation is performed for each bit line. In this procedure, the EEPROM
All bits of ROM are read. Then n=n +
1 operation is performed, the analog voltage is lowered by 0.1V,
(2) The voltage is set to 6.9V and the same operation is performed. Hereafter, in this procedure, the analog voltage vA is lowered in 0.1V increments until VA=4. Measurement can be continued until OV. That’s all, °゛1”
The write margin check ends. Next, a margin check for writing "0" is performed. First, EEPRO
Write 0'' to all bits of M. Next, set vA = oV and read the sense amplifier output for all bits of all words. In this case, the threshold voltage of the FET is 0.
If it is 7 or more, the FET is turned off and the sense amplifier output becomes "O". When the threshold voltage is below OV, the sense amplifier output becomes P1#. Assuming that the standard value is OV, when the sense amplifier output is 01" in the measurement of vA=Ov, it is "good", and when it is 0", it is "defective".This result is based on the serial I10 of the chip.
The output is output through the terminal to a simple external tester, and the tester records this result. This completes the execution of the gEPROM manual check program. In the above description, the EEPROM is selected bit by bit, but it is of course possible to select the EEPROM by byte. Furthermore, it is also possible to apply an analog voltage to the gates of all word lines at once, and in this case, the measurement time is shortened, but there is a peak during which the measurement accuracy deteriorates.

(Effects of the Invention) As described above in detail, according to the single-chip microcomputer of the present invention, the EEPROM machine test can be easily performed with a simple tester without using a general-purpose tester. Can be done. In single-chip microcomputers, EEP
ROM machine tests are frequently performed before and after aging. Therefore, it is not necessary to create a complicated test program, and an expensive general-purpose tester is not used exclusively, which greatly contributes to reducing test costs. Furthermore, since the analog voltage is generated inside the chip, highly accurate measurements can be made without being affected by external noise.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a single-chip microcomputer according to an embodiment of the present invention, FIG. 2 is a block diagram of a D/A converter according to an embodiment of the present invention, and FIG. 3 is a block diagram of a D/A converter according to an embodiment of the present invention. FIG. 4 is a pattern diagram of a D/A converter, FIG. 4 is a circuit diagram of an EEPROM according to an embodiment of the present invention, and FIG. 5 is a flowchart of a manual check program according to an embodiment of the present invention. 1...RAM, 2...ROM, J...EEPRO
M, 4...ALU. 5...High voltage generation circuit, 6...VREF line, 7...
・D/A converter, 8...EEPROM check program, 9...VA line, 14...N+
Diffusion layer, 20... Analog output, 21... FET
0 Patent Applicant: Oki Electric Industry Co., Ltd. REF Pro 977 diagram of the present H1 DlA rotary collar Figure 2 ND Takaaki Obin's personal computer diagram of VA-1 Soba-7 Figure 3 The present invention EEPI? OM Descendants Closing Figure 4

Claims (2)

[Claims] (1) A single-chip microcomputer with built-in EEPROM, ROM, and RAM is equipped with an EEPROM margin check program means built into the ROM, and a D/A converter connected to the gate line of the EEPROM memory cell. Features a single-chip microcomputer. (2) The D/A converter generates an analog voltage by dividing a resistance by the word line of the RAM.
The single-chip microcomputer described in Section 1.