JPH01138679A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPH01138679A JPH01138679A JP62296863A JP29686387A JPH01138679A JP H01138679 A JPH01138679 A JP H01138679A JP 62296863 A JP62296863 A JP 62296863A JP 29686387 A JP29686387 A JP 29686387A JP H01138679 A JPH01138679 A JP H01138679A
- Authority
- JP
- Japan
- Prior art keywords
- potential
- bit line
- memory cell
- power
- cell plate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 claims description 14
- 230000008878 coupling Effects 0.000 abstract description 9
- 238000010168 coupling process Methods 0.000 abstract description 9
- 238000005859 coupling reaction Methods 0.000 abstract description 9
- 230000006641 stabilisation Effects 0.000 abstract 1
- 238000011105 stabilization Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 12
- 230000003071 parasitic effect Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000001934 delay Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Static Random-Access Memory (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Memories (AREA)
- Dram (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体記憶装置に関し、特に負の電位を有す
るP型基板上にNウェルを構成したCMO8型ダイ型ダ
イラミックメモリるものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and in particular to a CMO8 die-type dynamic memory in which an N-well is formed on a P-type substrate having a negative potential.
第4図はP型基板上にNウェルを形成したCMO8型ダ
イナミックメモリの構成図を示す。図中、1はp゛拡散
層、2はn゛拡散層、3はn型トランジスタ、4はn型
トランジスタ、5はメモリセル部、6はトランスファゲ
ート、7は第1ゲート、8は第2ゲート、9はAj2ビ
ット線、01〜C2は基板との間の結合容量、R1−R
4は寄生抵抗、’l”r、、Trtは寄生バイポーラト
ランジスタを示す。FIG. 4 shows a configuration diagram of a CMO8 type dynamic memory in which an N well is formed on a P type substrate. In the figure, 1 is a p diffusion layer, 2 is an n diffusion layer, 3 is an n-type transistor, 4 is an n-type transistor, 5 is a memory cell section, 6 is a transfer gate, 7 is a first gate, and 8 is a second gate. Gate, 9 is Aj2 bit line, 01-C2 is coupling capacitance with substrate, R1-R
4 represents a parasitic resistance, 'l''r, and Trt represent a parasitic bipolar transistor.
第5図は第4図における従来のメモリセルプレート電位
Verとビット線のプリチャージ電位VBLの発生回路
を示し、R1−R6は抵抗、Tr3はn型トランジスタ
、Tr4はn型トランジスタをそれぞれ示す。FIG. 5 shows a conventional generation circuit for the memory cell plate potential Ver and bit line precharge potential VBL in FIG. 4, where R1 to R6 are resistors, Tr3 is an n-type transistor, and Tr4 is an n-type transistor.
第6図は、第4図及び第5図の等価回路を示し、R9〜
R1tは抵抗を示している。FIG. 6 shows the equivalent circuit of FIGS. 4 and 5, and R9 to
R1t indicates resistance.
次に動作について説明する。Next, the operation will be explained.
以上のように構成されたCMO3型ダイ型ダイグミツク
メモリP型基板が負の電位になるようになっている。ま
た、メモリセルプレート電位VCP及びビット線プリチ
ャージ電位VILが1/2Vccに設定しである。電源
電圧■。、が印加された場合、第5図に示す回路によっ
てVeP及びVIILの電位が1/2Vccになる。V
((が立ち上がる時、第6図の等価回路で示されるよう
に結合容量c2〜c5によってVB11発生回路が動作
していない状態のとき、−瞬Vl11は正の電位に浮き
上がる。この様子を第7図に示す。The P-type substrate of the CMO3 type die-type dynamic memory constructed as described above has a negative potential. Further, the memory cell plate potential VCP and the bit line precharge potential VIL are set to 1/2 Vcc. Power supply voltage ■. , the potentials of VeP and VIIL become 1/2 Vcc by the circuit shown in FIG. V
(When ( rises, as shown in the equivalent circuit of FIG. 6, when the VB11 generation circuit is not operating due to the coupling capacitances c2 to c5, -instantaneous Vl11 rises to a positive potential. As shown in the figure.
従来の0MO3型ダイナミックメモリは以上のように構
成されているので、第8図に示す等価回路よりわかるよ
うに電源投入時に基板電位の浮き上がり(Vt )が大
きくなり、プロセスの変動で抵抗R2が大きく、あるい
はR1が小さくなった場合、寄生バイポーラトランジス
タTrl、Triがオンし、サイリスクとして動作する
ので、第7図の一点鎖線で示されるように基板電位は常
に正になったままになる。すなわち、電源投入時にラッ
チアップが発生するという問題点があった。Since the conventional 0MO3 type dynamic memory is configured as described above, as can be seen from the equivalent circuit shown in Figure 8, the rise in substrate potential (Vt) becomes large when the power is turned on, and the resistance R2 increases due to process fluctuations. , or when R1 becomes small, the parasitic bipolar transistors Trl and Tri turn on and operate as a silice, so the substrate potential always remains positive as shown by the dashed line in FIG. That is, there is a problem in that latch-up occurs when the power is turned on.
この発明は上記のような問題点を解消するためになされ
たもので、電源投入時のラッチアップを防ぐことができ
る0MO3型ダイナミックメモリを有する半導体記憶装
置を得ることを目的とする。The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor memory device having an OMO3 type dynamic memory that can prevent latch-up when power is turned on.
この発明に係る半導体記憶装置は、0MO3型ダイナミ
ックメモリにおいて、電源が安定するまでメモリセルプ
レート電位、ビット線プリチャージ電位のいずれか一方
あるいはその両方をGNDレベルに固定するか、または
いずれか一方の電位あるいはその両方の電位の発生を遅
らせ、電源投入時における基板とVSSとの間の結合容
量を増大させたものである。In the semiconductor memory device according to the present invention, in a 0MO3 type dynamic memory, either one or both of the memory cell plate potential and the bit line precharge potential is fixed at the GND level until the power supply becomes stable, or This delays the generation of one or both of the potentials and increases the coupling capacitance between the substrate and VSS when the power is turned on.
この発明の半導体記憶装置では、CMO5型ダイ型ダイ
ノミメモリの電源投入時の基板とVB2との間の結合容
量を増大させたので、電源投入時のランチアップを防止
できる。In the semiconductor memory device of the present invention, since the coupling capacitance between the substrate and VB2 when the power of the CMO5 die type dyno memory is turned on is increased, launch-up when the power is turned on can be prevented.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図はこの発明の一実施例による半導体記憶装置の回
路構成を示す図である。図において、R6−R11は抵
抗、Tr、はn型トランジスタ、Tr、。FIG. 1 is a diagram showing a circuit configuration of a semiconductor memory device according to an embodiment of the present invention. In the figure, R6-R11 are resistors, Tr is an n-type transistor, Tr.
Tr、はp型トランジスタ、甲は信号である。信号甲は
第2図で示されるタイミングで発生する。Tr is a p-type transistor, and A is a signal. The signal A occurs at the timing shown in Figure 2.
第3図は本実施例の電源間の等価回路を示す図である。FIG. 3 is a diagram showing an equivalent circuit between power supplies in this embodiment.
次に動作について説明する。Next, the operation will be explained.
第1図に示すように、VCFおよびVIILのノードに
p型トランジスタTrsを設け、Trsのゲート信号と
して第2図に示されるタイミング甲を用いている。即ち
、VCCが立ち上がりに伴い信号甲が立ち上がるので、
VCCが立ち上がり、信号甲がLOWレベルになるまで
Trsがオンし、VCF及び■1はGNDに接地された
状態になる。VCCが立ち上がってからVCP及び■1
が1/2■。、になる。メモリセル及びビット線の拡散
領域はチップの大部分を占めるために、基板との間の結
合容量は大きい。As shown in FIG. 1, a p-type transistor Trs is provided at the nodes of VCF and VIIL, and timing A shown in FIG. 2 is used as the gate signal of Trs. In other words, since the signal A rises as VCC rises,
When VCC rises, Trs is turned on until the signal A becomes LOW level, and VCF and 1 are grounded to GND. After VCC rises, VCP and ■1
is 1/2■. ,become. Since the memory cell and bit line diffusion regions occupy most of the chip, the coupling capacitance between them and the substrate is large.
このように、VCC投入時にVCア及び■1をGNDに
固定することによって第3図に示すように基+1 V
CC間の結合容11czに対して非常に大きな基板−V
SS間の結合容量を設けることができる。In this way, by fixing VC A and 1 to GND when VCC is turned on, the base +1 V is set as shown in FIG.
Very large substrate -V for the coupling capacitance between CC 11cz
A coupling capacitance between SSs can be provided.
すなわち第2図に示すように、VCC投入時の基板電位
浮き上がり (Vt )を小さくすることによって、従
来問題となった電源投入時のラフチアツブを防ぐことが
可能となる。That is, as shown in FIG. 2, by reducing the substrate potential rise (Vt) when VCC is turned on, it is possible to prevent the rise in the substrate potential when the power is turned on, which has been a problem in the past.
なお、上記実施例ではVCF及びVIILを電源投入時
にGNDに固定するために、信号甲及びn型トランジス
タTrsを設けたものを示したが、第9図に示すように
信号甲及びp型トランジスタTrbを設けてもよい。In the above embodiment, a signal A and an n-type transistor Trs are provided in order to fix VCF and VIIL to GND when power is turned on, but as shown in FIG. 9, a signal A and a p-type transistor Trb are provided. may be provided.
また、上記実施例では電源が安定するまでVCF及びV
IILをGNDに固定したが、VCP+ VMLのい
ずれか一方あるいはその両方の電位の発生を遅らせるよ
うに構成してもよく、この場合においても電源投入時の
ラフチアツブを防止することができる。In addition, in the above embodiment, VCF and V
Although IIL is fixed to GND, it may be configured to delay the generation of one or both of the potentials of VCP+VML, and even in this case, it is possible to prevent ruff-up when the power is turned on.
以上のようにこの発明に係る半導体記憶装置によれば、
メモリセルプレート電位VC?及びビット線プリチャー
ジ電位VIILを電源投入時に電源が安定するまでGN
Dに固定するように構成したので、電源投入時のラフチ
アツブを防止できる効果がある。As described above, according to the semiconductor memory device according to the present invention,
Memory cell plate potential VC? and bit line precharge potential VIIL to GN until the power is stabilized when the power is turned on.
Since it is configured to be fixed at D, it has the effect of preventing rough bumps when the power is turned on.
第1図は本発明の一実施例による半導体記憶装置の回路
構成図、第2図は本実施例のタイミングチャート図、第
3図は本実施例の電源間の関係を説明するための等価回
路を示す図、第4図はCMO8型ダイ型ダイラミックメ
モリ図、第5図は従来の半導体記憶装置の回路構成図、
第6図は従来例の等価回路を示す図、第7図は従来例の
タイミングチャート図、第8図は従来例の電源間の関係
を説明するための等価回路図、第9図は本発明の他の実
施例による半導体記憶装置の回路構成図である。
図において、lはp゛拡散層、2はn゛拡散層、3はn
型トランジスタ、4はn型トランジスタ、5はメモリセ
ル部、6はトランスファゲート、7は第1ゲート、8は
第2ゲート、9はAAビット線、C,−C,は基板との
間の結合容量、R1〜R1□は抵抗、T r+ 、Tr
zは寄生バイポーラトランジスタ、Tr3はn型トラン
ジスタ、Tra。
Tr、はn型トランジスタである。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is a circuit configuration diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a timing chart diagram of this embodiment, and FIG. 3 is an equivalent circuit for explaining the relationship between power supplies of this embodiment. 4 is a diagram of a CMO8 type die-type dynamic memory, and FIG. 5 is a circuit configuration diagram of a conventional semiconductor memory device.
FIG. 6 is a diagram showing an equivalent circuit of a conventional example, FIG. 7 is a timing chart diagram of a conventional example, FIG. 8 is an equivalent circuit diagram for explaining the relationship between power supplies of a conventional example, and FIG. 9 is a diagram of the present invention. FIG. 3 is a circuit configuration diagram of a semiconductor memory device according to another embodiment. In the figure, l is p'diffused layer, 2 is n'diffused layer, and 3 is n'diffused layer.
4 is an n-type transistor, 5 is a memory cell section, 6 is a transfer gate, 7 is a first gate, 8 is a second gate, 9 is an AA bit line, and C, -C, are couplings with the substrate. Capacitance, R1 to R1□ are resistances, Tr+, Tr
z is a parasitic bipolar transistor, Tr3 is an n-type transistor, Tra. Tr is an n-type transistor. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
ナミックメモリを有する半導体記憶装置において、 電源が安定するまで、メモリセルプレート電位、ビット
線プリチャージ電位のいずれか一方あるいはその両方を
GNDレベルに固定する、あるいはその電位の発生を遅
らせることを特徴とする半導体記憶装置。(1) In a semiconductor memory device having a CMOS type dynamic memory with an N-well formed on a P-type substrate, either the memory cell plate potential or the bit line precharge potential, or both, is set to the GND level until the power supply stabilizes. 1. A semiconductor memory device characterized by fixing the potential at or delaying the generation of the potential.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62296863A JPH01138679A (en) | 1987-11-25 | 1987-11-25 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62296863A JPH01138679A (en) | 1987-11-25 | 1987-11-25 | Semiconductor memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01138679A true JPH01138679A (en) | 1989-05-31 |
Family
ID=17839139
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62296863A Pending JPH01138679A (en) | 1987-11-25 | 1987-11-25 | Semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01138679A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012507107A (en) * | 2008-11-05 | 2012-03-22 | クアルコム,インコーポレイテッド | Data protection during power-up in spin transfer torque magnetoresistive random access memory |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60253090A (en) * | 1984-05-30 | 1985-12-13 | Hitachi Ltd | Semiconductor device |
JPS63182848A (en) * | 1987-01-12 | 1988-07-28 | シーメンス、アクチエンゲゼルシャフト | Integrated circuit |
-
1987
- 1987-11-25 JP JP62296863A patent/JPH01138679A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60253090A (en) * | 1984-05-30 | 1985-12-13 | Hitachi Ltd | Semiconductor device |
JPS63182848A (en) * | 1987-01-12 | 1988-07-28 | シーメンス、アクチエンゲゼルシャフト | Integrated circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012507107A (en) * | 2008-11-05 | 2012-03-22 | クアルコム,インコーポレイテッド | Data protection during power-up in spin transfer torque magnetoresistive random access memory |
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