JPH01138679A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To prevent latch up at the time of power-on by fixing the memory cell plate potential and the bit line precharge potential to the GND level till stabilization of power at the time of power-on. CONSTITUTION:A p-type transistor(TR) Tr5 is provided in the node of a memory cell plate potential VCP and a bit line precharge potential VBL, and a timing the inverse of PSI is used as the gate signal. Since a signal PSI rises in accordance with rise of a supply potential VCC, the TR Tr5 is turned on and the memory cell plate potential VCP and the bit line precharge potential VBL are earthed to GND until the supply potential VCC rises and the signal PSI goes to the low level, and the memory cell plate potential VCP and the bit line precharge potential VBL are set to 1/2VCC after the supply potential VCC rises, and a coupling capacity of substrate-earth potential VSS larger than that of substrate-supply potential VCC is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and in particular to a CMO8 die-type dynamic memory in which an N-well is formed on a P-type substrate having a negative potential.

[Conventional technology]

FIG. 4 shows a configuration diagram of a CMO8 type dynamic memory in which an N well is formed on a P type substrate. In the figure, 1 is a p diffusion layer, 2 is an n diffusion layer, 3 is an n-type transistor, 4 is an n-type transistor, 5 is a memory cell section, 6 is a transfer gate, 7 is a first gate, and 8 is a second gate. Gate, 9 is Aj2 bit line, 01-C2 is coupling capacitance with substrate, R1-R
4 represents a parasitic resistance, 'l''r, and Trt represent a parasitic bipolar transistor.

FIG. 5 shows a conventional generation circuit for the memory cell plate potential Ver and bit line precharge potential VBL in FIG. 4, where R1 to R6 are resistors, Tr3 is an n-type transistor, and Tr4 is an n-type transistor.

FIG. 6 shows the equivalent circuit of FIGS. 4 and 5, and R9 to
R1t indicates resistance.

Next, the operation will be explained.

The P-type substrate of the CMO3 type die-type dynamic memory constructed as described above has a negative potential. Further, the memory cell plate potential VCP and the bit line precharge potential VIL are set to 1/2 Vcc. Power supply voltage ■. , the potentials of VeP and VIIL become 1/2 Vcc by the circuit shown in FIG. V
(When ( rises, as shown in the equivalent circuit of FIG. 6, when the VB11 generation circuit is not operating due to the coupling capacitances c2 to c5, -instantaneous Vl11 rises to a positive potential. As shown in the figure.

[Problem that the invention seeks to solve]

Since the conventional 0MO3 type dynamic memory is configured as described above, as can be seen from the equivalent circuit shown in Figure 8, the rise in substrate potential (Vt) becomes large when the power is turned on, and the resistance R2 increases due to process fluctuations. , or when R1 becomes small, the parasitic bipolar transistors Trl and Tri turn on and operate as a silice, so the substrate potential always remains positive as shown by the dashed line in FIG. That is, there is a problem in that latch-up occurs when the power is turned on.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor memory device having an OMO3 type dynamic memory that can prevent latch-up when power is turned on.

[Means for solving problems]

In the semiconductor memory device according to the present invention, in a 0MO3 type dynamic memory, either one or both of the memory cell plate potential and the bit line precharge potential is fixed at the GND level until the power supply becomes stable, or This delays the generation of one or both of the potentials and increases the coupling capacitance between the substrate and VSS when the power is turned on.

[Effect]

In the semiconductor memory device of the present invention, since the coupling capacitance between the substrate and VB2 when the power of the CMO5 die type dyno memory is turned on is increased, launch-up when the power is turned on can be prevented.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a circuit configuration of a semiconductor memory device according to an embodiment of the present invention. In the figure, R6-R11 are resistors, Tr is an n-type transistor, Tr.

Tr is a p-type transistor, and A is a signal. The signal A occurs at the timing shown in Figure 2.

FIG. 3 is a diagram showing an equivalent circuit between power supplies in this embodiment.

Next, the operation will be explained.

As shown in FIG. 1, a p-type transistor Trs is provided at the nodes of VCF and VIIL, and timing A shown in FIG. 2 is used as the gate signal of Trs. In other words, since the signal A rises as VCC rises,
When VCC rises, Trs is turned on until the signal A becomes LOW level, and VCF and 1 are grounded to GND. After VCC rises, VCP and ■1
is 1/2■. ,become. Since the memory cell and bit line diffusion regions occupy most of the chip, the coupling capacitance between them and the substrate is large.

In this way, by fixing VC A and 1 to GND when VCC is turned on, the base +1 V is set as shown in FIG.
Very large substrate -V for the coupling capacitance between CC 11cz
A coupling capacitance between SSs can be provided.

That is, as shown in FIG. 2, by reducing the substrate potential rise (Vt) when VCC is turned on, it is possible to prevent the rise in the substrate potential when the power is turned on, which has been a problem in the past.

In the above embodiment, a signal A and an n-type transistor Trs are provided in order to fix VCF and VIIL to GND when power is turned on, but as shown in FIG. 9, a signal A and a p-type transistor Trb are provided. may be provided.

In addition, in the above embodiment, VCF and V
Although IIL is fixed to GND, it may be configured to delay the generation of one or both of the potentials of VCP+VML, and even in this case, it is possible to prevent ruff-up when the power is turned on.

〔Effect of the invention〕

As described above, according to the semiconductor memory device according to the present invention,
Memory cell plate potential VC? and bit line precharge potential VIIL to GN until the power is stabilized when the power is turned on.
Since it is configured to be fixed at D, it has the effect of preventing rough bumps when the power is turned on.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a timing chart diagram of this embodiment, and FIG. 3 is an equivalent circuit for explaining the relationship between power supplies of this embodiment. 4 is a diagram of a CMO8 type die-type dynamic memory, and FIG. 5 is a circuit configuration diagram of a conventional semiconductor memory device.
FIG. 6 is a diagram showing an equivalent circuit of a conventional example, FIG. 7 is a timing chart diagram of a conventional example, FIG. 8 is an equivalent circuit diagram for explaining the relationship between power supplies of a conventional example, and FIG. 9 is a diagram of the present invention. FIG. 3 is a circuit configuration diagram of a semiconductor memory device according to another embodiment. In the figure, l is p'diffused layer, 2 is n'diffused layer, and 3 is n'diffused layer.
4 is an n-type transistor, 5 is a memory cell section, 6 is a transfer gate, 7 is a first gate, 8 is a second gate, 9 is an AA bit line, and C, -C, are couplings with the substrate. Capacitance, R1 to R1□ are resistances, Tr+, Tr
z is a parasitic bipolar transistor, Tr3 is an n-type transistor, Tra. Tr is an n-type transistor. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a semiconductor memory device having a CMOS type dynamic memory with an N-well formed on a P-type substrate, either the memory cell plate potential or the bit line precharge potential, or both, is set to the GND level until the power supply stabilizes. 1. A semiconductor memory device characterized by fixing the potential at or delaying the generation of the potential.