JPH01137371A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To improve logical designing efficiency by searching an input variable group including an intermediate terminal and an input variable group of the intermediate terminal for each output variable. CONSTITUTION:A logic circuit is expressed in plural logical formulas and with use of the Boolean function and a middle member of a logical formula is extracted as an intermediate terminal. The input variable groups including the intermediate terminals are sorted for each product term of each logical formula and set opposite to the output variables. Then, the input variable groups of the intermediate terminals are sorted into plural groups for each product member of each logical formula. The search is carried out for each output variable based on both input variable groups for detection of the presence or absence of a loop of logical formulas. Based on this detecting result, a logic circuit is logically designed. Therefore, a logical formula is expressed in the numerical data and can be processed by a computer. After the same time, the number of coding steps is extremely decreased.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Prior Art (Fig. 3) Problems to be Solved by the Invention Means for Solving the Problems Examples of Actions (1) Effects of the Invention First embodiment (Figure 1.2) (2)
Effects of the invention according to the second embodiment of the present invention [Summary] Regarding the method of manufacturing and using a semiconductor device, the number of coding steps when performing a loop check can be significantly reduced, and processing can be performed efficiently on a computer. The purpose of the present invention is to provide a method for manufacturing a semiconductor device in which a logic circuit that performs various logical operations is expressed by a plurality of logical expressions using Boolean functions, and is logically designed. The middle term of the formula is extracted as an intermediate terminal, the input variable group including the intermediate terminal is classified for each product term of each logical formula, and the input variable group of the intermediate terminal is classified into the product terms of each logical formula. Classify each term into multiple groups, search for each output variable based on the input variable group and the input variable group of the intermediate terminal to detect the presence or absence of a loop in the logical formula, and create a logical circuit based on the detection result. Configure to logically design.

[Industrial application field]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device that automatically detects loops in a logic circuit and improves workability when performing logic design.

A logic circuit is a circuit whose object is to determine which of the discrete states the input and output are in, and what series the states become at discrete points in time. Broadly speaking, circuits can be divided into combinational logic circuits (CO) whose output is determined only by the input at the current moment.
mbnational I.

gic circuit), and sequential circuits in which the output is not determined solely by the current input, but is influenced by the current state of the circuit and past inputs.
circuit).

In general, digital logic circuits can be considered that are composed of basic logic circuits whose input/output states are multivalued, and they are known to be efficient for various digital operations, but they are simple and have low performance. Since it is not always easy to obtain a good basic multi-valued logic circuit, digital logic circuits usually refer to binary ones. The duality of the input and output values of a binary normal digital logic circuit,
Since it completely corresponds to the duality of variables in Boolean algebra, the input/output relationship of a digital logic circuit or the state of the circuit can be expressed by Boolean algebra.

[Conventional technology]

Generally, as integrated circuits become larger, the number of elements increases, so the number of circuit changes due to design changes increases, and the lifespan of each type tends to be shortened. P L A (P
A programmable logic array (ROM) is a writable integrated circuit similar to a ROM, and is expected to be a way to reduce such problems in large-scale integrated circuits. PLA was developed in the late 1970s, and it constructs a logic circuit by programming each grid point of a circuit configured in a two-dimensional grid.
It can be seen as a type of ROM. Usually, it consists of an AND array and an OR array, and a logic circuit is realized by a two-stage AND-OR configuration. That is, all arbitrary logic circuits are achieved by transforming the logic into a product-sum type (AND-OR type). Demand for PLA is increasing because it allows electronic device designers to create their own ICs with the necessary logic functions at the development site. PLA is superior to TTL in terms of integration and flexibility, and has advantages over gate arrays in terms of development costs, development time, and design risk avoidance. It is an IC that fills the Furthermore, the development of programmers (writers) essential to PLA is progressing, and software that automates everything from expressing logical design specifications to creating written data using a personal computer is also being developed.

By the way, in order to design the above-mentioned LSI without errors in a short period of time, it is necessary to use CAD (such as logic simulation).
Computer aided design (computer aided design) is essential, and logic tests such as loop checks that take into account the ease of failure testing from the beginning are also important.

An example of a conventional logic design method for this type of LSI is shown in FIG. When using a PLA CAD tool to express the relationship between the input and output of a logic circuit (hereinafter simply referred to as a circuit) using a logical formula, the input xI + xl + x31x4 and the output Vr, V as shown in Figure 3 are used.
A very simple circuit called t can be expressed as the following equation (■).

'J+=X+　　　Xz　+X, -x3・・・・・・■ 3'z=X+　　　　　Xz　　+X, 　+x.

However, ・:AND (hereinafter the same) +:OR (hereinafter the same) If the logical expression is extremely simple as shown in equation 0, it can be expressed as an expression of output = input, but in reality is more complex and requires intermediate variables (hereafter referred to as intermediate terminals). For example, if X, x2 is represented by an intermediate terminal T, the above equation 0 becomes the following equation 〇.

)'+ =T+ +xl -x3 y2=T, +x3+X, ・−・・■T, =x
, -x.

By the way, if a circuit is designed in this format, as the circuit becomes large-scale, it will become a series of complicated mathematical formulas, and the designer may unintentionally create a loop.

It is not necessarily bad if a loop occurs, but
There may be a design error, resulting in problems such as no output. Therefore, a CAD tool is required to have a function to check whether there is a loop or not based on a logical expression.

[Problem that the invention seeks to solve]

However, in a semiconductor device manufacturing method using such a conventional logic circuit loop check method, L
When the scale of the SI becomes larger, the logic circuit becomes more complex, and the amount of data increases, there is a problem in that the processing becomes complicated and the effort and time required to check the loop increases.

In other words, there are several ways for humans to discover loops, one of which is through simulation. This is to input a data pattern and see what kind of output is produced when a loop occurs inside.
It is difficult to create patterns for input data one by one. Also, as a second method, there is a method of substituting the intermediate terminal into the logical expression as described above, but since this method depends on characters, it is necessary to judge the characters. In addition, since the process is done manually, it is not suitable for computer processing, and the intermediate terminal introduced to streamline the process loses its meaning. In any case, as the circuit becomes more complex and the amount of data increases, processing becomes more complicated, making it difficult to discover loops.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can significantly reduce the number of coding steps when performing a loop check and can be efficiently processed on a computer.

[Means for solving problems]

In order to achieve the above object, the method for manufacturing a semiconductor device according to the present invention includes a method for manufacturing a semiconductor device in which a logic circuit that performs various logical operations is expressed by a plurality of logical expressions using Boolean functions, and the method for manufacturing a semiconductor device is logically designed. The middle term of is extracted as an intermediate terminal, the input variable group including the intermediate terminal is classified for each product term of each logical formula, and it is made to correspond to the output variable, and the input variable group of the intermediate terminal is classified as the product term of each logical formula. The presence or absence of a loop in the logical formula is detected by searching for each output variable based on the input variable group and the input variable group of the intermediate terminal, and the logic circuit is configured based on the detection result. I try to design it.

[For production]

In the present invention, the input variable group including the intermediate terminal and the input variable group of the intermediate terminal are searched for each output variable.

Therefore, logical expressions can be expressed as numerical data and processed on a computer, and the number of coding steps can be significantly reduced.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

Figure 1.2 shows the first method of manufacturing a semiconductor device according to the present invention.
1 is a diagram illustrating an embodiment, and the present invention proposes a method for automatically detecting loops in logical expressions using large-scale intermediate terminals. To compensate for this problem, it is necessary to express logical expressions in another way. Therefore, the logical formula is expressed using a so-called cube expression technique in which the logical product is expressed as an n-dimensional hypercube. for example,
All input variables are placed in one horizontal column, and each logical formula is divided into product terms and corresponds to the one horizontal column (cover). Those that appear in that term are set as 1 or 0 (negation), those that do not output are set as 2, and the If the output where the term appears is 5 and the output where the term does not appear is 4, then
The logical formula (0th formula) of the logic circuit shown in FIG.
Shown as a table. In this case, the input cube and output cube are divided into two-dimensional arrays on the computer.

The method for detecting loops in Table 1 is to first divide them into the same output cube and sequentially examine them. In other words, as shown in Table 2, the input cube for a certain output cube is (1, 1) →
(1, 2)→・・・・・・→(x +%.

xn), and if "1" or "O" is found, check whether it is an intermediate terminal, and if it is an intermediate terminal, search from the left for a large power cube that has that intermediate terminal as an output using the same method as above. Also, the intermediate terminal is “
1" or "θ"; if 2", skip) Search the input cube of the intermediate terminal. Repeat this until no intermediate terminals appear. Intermediate terminals that appear along the way are memorized separately, and if the same terminal appears twice, it is recognized as a loop and a warning is issued. When there is no loop,
The input cube for the first stage is. Repeat until finished.

(This page, margins below) Table 2 Xl　Xzo”−−−−−−−−−−0−X.

(1,1) (1,2)・・・・・・・・・(1,X,
)(2,1) (2,2) ・・−”・(2,X, )
(x,, 1) (x,, 2) ”・・・・・・・・・(
x, , X, ) Next, the effect will be explained.

FIG. 1 is a flowchart showing a program for a loop check method for a logic circuit, and in FIG. 1, Pn (n=
1.2. ...) indicates each step of the program.

When the program starts, first, P+ converts the logical expression into cube representation, and P2 clears the AP array to O. When the intermediate terminal appears once, it sets "1", so initially clear it to O. Then, P searches for input cubes for the output cube in the order shown in Table 2. That is, the second output Y is YK (Y In Y t in this embodiment), the number of terms (vertical number in Table 1) is i, and the number of intermediate terminals (“l” in this embodiment) is
) is j, then in P3 it is determined whether YK (i, J+number of inputs) is "0" or "l". For example, when Yl (1, 4), look at the item marked * in Table 1, and if it is “O” or “1”, P
4, AP (j) (in this case, AP (1)) = 1,
Perform a loop check with P. This loop check method is explained in the subroutine (LOOP) shown in Figure 2.
-CHK) will be described later.

YK (i, j ten people) j number) = 0 or ye (
If it J + number of inputs) is not 1, it is determined that there is no corresponding item and the process directly proceeds to Ph. In P6, the number of intermediate terminals j (in this example, intermediate terminal j = 1)
It is determined whether or not processing has been performed for j times. If the process has not been processed j times, the process returns to P. Next, in P7, it is determined whether or not the number of terms i (the vertical number shown in Table 1) of the output Y has been processed. Time returns to P again. Next, in P8, it is determined whether or not the number of outputs Y (in this example, two, Y l and Y z) has been processed, and when the process has been performed K times, the current processing is finished, and When the process is not completed, the process returns to P again.

Figure 2 shows the loop check subroutine (LOOP-C
This is a flowchart showing the intermediate terminal j
is passed as an argument (arg-+n.

W) is initiated by First, P, sets the argument Tno
(Here, Tno-shi1), it is determined whether the intermediate terminal Tnow (in j ten input number) is "0" or "1", and Tnow(i.

When j 10 inputs) - 〇 or Tnow (t, j 10 inputs) = 1, AP (j) = 0 in PI2 (,:
, knee, it is determined whether AP (1)=O). At P4 above, AP (j) = 1 and “
1", so when AP (j) ≠ 0, the designer is alerted to the occurrence of a routine error with an alarm, etc., and the process ends. On the other hand, when AP (j) = O at P+□, Set AP (j) = 1 in PI4 and proceed to PIS, but if there are more intermediate terminals and intermediate terminal "1" is still standing among the intermediate terminals, pu
This routine is called again with s, and the same process is repeated to deeply check one after another. In PI&, it is determined whether or not the number of intermediate terminals has been processed. If the process has been performed j times, the process proceeds to PI7, and if the process has not been performed j times, the process returns to pH again. Next, PI? and the intermediate terminal argument T
Determine whether processing has been performed for the number of terms (here, only "1") of now (Tno katsuo = 1 in this embodiment),
When the number of terms of Tno− has been processed, proceed to PIl+ and T
If processing has not been completed for the number of nowO terms, the process returns to P again. At pH+, AP (nov)=Q, this routine ends, and the process returns to the main routine shown in FIG.

This is cleared here because there is no problem even if the same intermediate terminal appears multiple times in the same output variable and same intermediate terminal term (see No. 2, Equation 0).

)'+ ”'X+ ・Xz +T+ ・Xl
+T+ -Xs No problem......■ y=x, -x, +T, -x, +T, ・
X=T=x, -x2 ・T.

oop ・・・・・・■ Therefore, in this embodiment, by expressing the logical formula as numerical data, it is easy to express on a computer, and the loop check of the logic circuit is freed from manual work and realized by computer processing. be able to. Furthermore, for the same reason, subroutines can be used recursively when performing a loop check, and the number of coding steps can be significantly reduced. As a result, even when the logic circuit becomes complex and the amount of data increases, the effort and time required to check the loops can be significantly reduced.
Logic design can be made more efficient.

Although this embodiment shows an example in which the present invention is applied to a PLA CAD tool, the present invention is of course not limited to this, and as long as a logical formula is expressed using Boolean algebra, it is not limited to PLA. Needless to say.

Let us consider the case of loop checking the logical formula shown in the following formula.

3'+ -Tt x, txt 'X3 +xl
*) (, 9X3'It =X+ "Xz'
)C+ txt ・x2'x3・xju・xzlx3
+ x11
g s X3 , Tt), as shown in Table 3.

Table 3 01120012 yr l 0 1 2 1 0 0”
)'1 Here, pay attention to y and check the loop. y, input cube)'l (3,4
), it will look like the left side of Table 4. y
.

Focusing on (1, 4), if we search for an input cube that has the intermediate terminal T1 as an output from the "1" length, we can find "input" and "2" (undefined) as shown on the right side of Table 4. Therefore, it can be seen that there is no intermediate terminal here.

(This page, blank space below) Table 4 (1,1)→2 (1,2)→2 (1,3)-2 (1,4)-1-Intermediate terminal-T+ (1,1)
-1-Manpower T, TI(1,2)-1-Manpower T,
(1,3)→2 TI (1,4) −2 , °, there is no intermediate terminal.

)'+ (2,1) -0 y, (3,4)→2 Furthermore, as the loop check progresses, yl(2,1
) and subsequent ones are input and “2” (undefined), so no intermediate terminal appears. Also, check y2 in the same way to confirm that there is no loop. For example, if T1 (1, 4) shown on the right side of Table 4 is 0" or 1", the intermediate terminal T appears twice, so a loop exists and a warning is issued.

〔effect〕

According to the present invention, since the input variable group including the intermediate terminal and the input variable group of the intermediate terminal are searched for each output variable, it is possible to express the logical formula with numerical data and process it on a computer. At the same time, the number of coding steps can be significantly reduced, and logic design can be made more efficient.

[Brief explanation of the drawing]

Figure 1.2 shows the first method of manufacturing a semiconductor device according to the present invention.
FIG. 1 is a flowchart showing a program for a loop check method of a logic circuit, FIG. 2 is a flowchart showing a subroutine of the loop check, and FIG. 3 is a flowchart showing a conventional method for manufacturing a semiconductor device. FIG. 3 is a diagram showing a logic circuit. Figure 3 shows a conventional logic circuit.

Claims (1)

[Claims] A method for manufacturing a semiconductor device in which a logic circuit that performs various logical operations is expressed by a plurality of logical formulas using Boolean functions, and a logic design is performed, comprising: extracting a term in the middle of the logical formula as an intermediate terminal; The input variable group including the intermediate terminal is classified for each product term of each logical formula and made to correspond to the output variable, and the input variable group of the intermediate terminal is classified into a plurality of groups for each product term of each logical formula, The present invention is characterized in that the presence or absence of a loop in a logical expression is detected by searching for each output variable based on the variable group and the input variable group of the intermediate terminal, and the logic circuit is logically designed based on the detection result. A method for manufacturing a semiconductor device.