JPH01137316A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To simplify the constitution of a data distributing circuit for selection of internal buses, a data multiplexer circuit, etc., by using the dynamic buses to the internal buses and securing the OR connection among these buses by the negative logic. CONSTITUTION:The internal output buses dx00-0m and dx30-3m undergo the AND arithmetic with the reverse timing signal and the negative logic through a NOR gate circuit NOG1 corresponding to the unit circuits UMX of unit data multiplexers MX0-3 and then undergo the OR arithmetic with the negative logic for each bit via the connection logic of the output terminal of the circuit NOG1. A data output buffer DOB sends the inverted internal output data supplied from a data multiplexer DMX to a CPU via a data bus. Thus, it is possible to simplify the constitution of a data distributing circuit for selection of the register groups and the internal buses, the data multiplexer circuit, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, for example, a DMA (Direct
The present invention relates to a technology that is particularly effective when used in memory access (Memory Access) controllers and the like.

[Conventional technology]

In combinator systems and the like, there is a DMA controller that directly controls the transfer of data, etc. between an input/output device and a storage device without going through a central processing unit.

The DMA controller is provided with a plurality of channels that each independently perform a transfer operation, and is also provided with a plurality of register groups for specifying an address where data etc. are stored, a transfer amount, etc. corresponding to each channel.

For DMA controllers, see e.g.
March, ■rHitachi microcomputer published by Hitachi, Ltd.
Data book 8 bit/16 bit multichip J
It is described on pages 406 to 439.

[Problem that the invention seeks to solve]

A conventional DMA controller as described above is
For example, as shown in FIG. 3, four register groups REGGO-REGG3 are provided corresponding to each channel.
including. Each register group includes p+1 registers REGOO to REGOp to registers REG30 to R.
EG3p, and each of these registers includes a plurality of unit circuits.The input terminal and output terminal of each unit circuit are connected to a corresponding internal input bus dsoO for each pin, as exemplarily shown in FIG. ~dsQm or ds30
=ds3m and internal output buses dx00 to dxOm to dx30 to dx3m, respectively. The unit circuits of each register are supplied with register selection signals 5iOQ to aiOp to 5i supplied from the register selection circuit R3L.
Bus input circuits that are selectively activated according to 3Q to 5i3p are provided, and a register selection signal 5
Bus output circuits that are selectively activated according to o00 to 5oop to 5o3Q to 5o3p are provided, respectively.

Internal input bus dsoo~dsOm or ds30~d
s3m are respectively coupled to corresponding bus drive circuits of the data distribution circuit DDS. These bus drive circuits receive a bus selection signal si supplied from the register selection circuit R3L.
It is selectively brought into operation according to Q~si3. The input data diO~dim supplied via the input bus is
Through these bus driving circuits, the corresponding bits of all channels are transferred to the internal human power bus.

On the other hand, internal output bus dx00=dxQm to dx30
~dx3m are each coupled to a corresponding bus receiving circuit of the data multiplexer DMX. These bus receiving circuits are selectively brought into operation according to bus selection signals soQ to so3 supplied from the register selection circuit R3L. Internal output buses dxoO to dxom from the selected register of each register group Ldx30 to dx3m
The data output to is output data doo to d.

m, and is transmitted to the corresponding output bus.

However, the MA controller described above has the following problems. That is, the address signal aOxa
As described above, the register specified by i is first selected by register selection signals aio~5iQp~5i30~
5i3p or 5ooO~5oOp or 5o3Qxso
After being selectively coupled to the corresponding internal input bus or internal output bus by 3p, the bus selection signal sio-w
It is selectively coupled to the input bus or the output bus by si3 or 5oO=so3. In addition, each register unit circuit has a driving capacity capable of driving a relatively large load capacitance of the corresponding internal output bus.
Data distribution circuit DDS, data multiplexer DMX, and register selection surface 1i! As the number of 3R3L circuit elements increases, the area required for the layout of the bus and each selection signal line increases, which limits the ability to reduce the cost of the DMA controller and also limits the ability to reduce its power consumption.

An object of the present invention is to provide a semiconductor integrated circuit device such as a DMA controller that efficiently connects internal buses and register groups. Another object of this invention is to
The objective is to promote lower costs and lower power consumption of semiconductor S-product circuit devices including A controllers and the like.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

Measures for Solving Problems c] A brief overview of typical inventions disclosed in this application is as follows.

In other words, the internal bus is normally precharged to a predetermined level and then selectively and alternatively discharged according to data transmitted at a predetermined timing. This is a logical OR combination.

(Function) According to the above-mentioned means, it is possible to simplify the circuit configuration of the data distribution circuit, data multiplexer, etc. for selecting the internal bus, reduce the required layout area of the internal bus and selection signal line, and also reduce the layout area of the internal bus and selection signal line. By using the Guinami Soku bus, the bus drive current can be significantly reduced, so the DMA
It is possible to reduce the cost and power consumption of controllers and the like and semiconductor integrated circuit devices including them.

〔Example〕

FIG. 2 shows a block diagram of an embodiment of a DMA controller (DMAC) to which the present invention is applied.

FIG. 1 also shows the data distribution circuit DDS of the DMA controller in FIG. 2 and the register groups REGGO to REGG3.
A circuit diagram of one embodiment of the data multiplexer DMX and the data multiplexer DMX is shown.

An overview of the configuration and operation of the DMA controller of this embodiment will be explained based on these figures.

Although not particularly limited, the DMA controller of this embodiment is built in a one-chip microcomputer and has four
channels CHO to CH3. The DMA controller independently and in parallel controls data transfer between the four types of input/output devices IOE coupled to these channels and the main memory device MM. Note that the circuit elements constituting each block in FIGS. 1 and 2, together with other circuit elements not shown in the microcomputer,
Although not particularly limited, it is formed on one semiconductor substrate such as single crystal silicon. In addition, in FIG. 1, MOSFETs with arrows added to the channel (bank gate) section
ET is a P-channel type, and is displayed to distinguish it from an N-channel MO3FET, which is not marked with an arrow.

The DMA controller of this embodiment is coupled to the central processing bag 2CPU via a data bus DB, an address bus AB, and a control bus, although this is not particularly limited. The control bus includes a read/write signal R/W and an address strobe signal τ, and the DMA controller includes:
In addition to these system buses, it is also coupled to the main memory device MM via a plurality of transfer control signals (not shown). D
The MA controller includes four sets of register groups REGGO to REGG3 provided corresponding to each channel, each register group having p+1 registers REGOO.
~REGOp to REG30 to REG3p. Although these registers are not particularly layered, they hold the start address on the main memory device MM where transfer data is stored, the amount of data transfer, the control status of each channel, and the like.

Also, at the start or end of transfer, the central processing unit CP
It is arbitrarily accessed by U, and the above address, control status, etc. are input/output. At this time, the DMA controller is activated by the address strobe signal XS being set to low level, and is selectively put into the input mode or output mode according to the read/write signal R/W. The register groups and the registers in each register group are selectively determined by address signals aO to ai supplied via the lower bits of the address bus AB, although this is not particularly limited. Input/output data such as addresses and control status for each register are transmitted via the data bus DB.

In FIG. 2, the read/write signal R/W and address strobe signal AS are coupled to the bus control circuit BCTL of the DMA controller. Address bus AB is DM
coupled to the address buffer ADB of the A controller;
The data bus DB is coupled to a data manual buffer DIB and a data output buffer DOB.

The bus control circuit BCTL has an address strobe signal As.
is activated when the DMA controller is set to a low level, and forms various timing signals for controlling each circuit of the DMA controller and supplies them to each circuit. At this time, if the read/write signal R/W is at a low level, the DMA controller is placed in the input mode, and data supplied from the central processing unit cPU is input to the register specified by the address signals aO to ai. On the other hand, if the read/write signal R/W is at a high level at this time, the DMA:12 controller is set to output mode, data such as control status is read from the register specified by the address signals aO to at, and the central It is output to the processing device CPU. The bus control circuit BCTL further has a function of occupying the system bus using a bus control signal (not shown).
The bus control path BCTL performs control for directly transferring data to and from the main memory device MM.

The present invention relates to input/output operations such as addresses and control status performed between a register group of a DMA controller and a central processing unit CPU, that is, register access. Therefore, in the following description, descriptions of the configurations and operations of blocks related to data transfer control between the input/output device IOE and the main memory device MM will be omitted.

Address buffer ADB takes in and holds a register address signal transmitted via the lower bits of address bus AB in the register access mode of the DMA controller. Furthermore, these address signals are made complementary signals and are supplied as internal address signals aO to ai to a register selection circuit R3L, which will be described later. Address buffer A
DB has a uA function that sends the address signal supplied from the address increase/decrease circuit ¥&A ID to the address bus AB when the DMA controller accesses the main memory device MM.

The register selection circuit R3L is connected to the address buffer AD.
The internal address signals aO to ai supplied from B are decoded. At this time, if the DMA controller is in input mode, 1. The register selection circuit R3L sends register selection signals 5ioO to 5iQp to one corresponding register.
5i30 to 5i3p are alternatively supplied. Also,
At this time, if the DMA controller is in output mode,
The register selection circuit R3L sends register selection signals 5olo to 5oQp to so3 to one corresponding register.
0wso3p is alternatively supplied.

The data input cover sofa DIB receives control data such as data transfer amount supplied from the central processing unit CPU via the data bus DB, and receives inverted internal input data diQ-wdim.
The data is transmitted to the data distribution circuit DO3, which will be described later. These inverted internal input data diO-dim are normally set to a high level, and are selectively set to a low level when input data supplied via a corresponding pin of the data bus DB is set to logic "1".

As exemplarily shown in FIG. 1, the data distribution circuit DDS includes four unit data distribution circuits DSO to DS3 provided corresponding to channels CHO to CH3. Each unit circuit UDS, including m+1 unit circuits UDS, includes, but is not particularly limited to, a P-channel MO3FET QII and an N-channel MOSFET Q1 and N-channel MOSFET QII provided in series between the power supply voltage of the circuit and the ground potential. and an AND gate circuit AGI.

One input terminal of the AND gate circuit AGl of the unit circuit UDS of the corresponding bit of each unit data distribution circuit DSO to DS3 is commonly coupled for each pin 1-, and the corresponding inverted internal input data The other input terminals of the AND gate circuits AGI of all the unit circuits UDS are commonly coupled, and the timing signal φis is commonly supplied from the lotus control circuit BCTL. Although not particularly limited, φi8 is normally set to a low level, and set to a high level at a predetermined timing when the DMA controller is in the register access mode and selected state in the input mode.The AND gate of each unit circuit UDS The output signals of the circuits AGI are respectively supplied to the gates of the corresponding MO3FETQl.The gates of the MO3FETQII are commonly supplied with the timing signal φpc of No. 18 φpc from the bus control circuit !&BCTL. When it is in a non-selected state, it is set to low level, and the DMA
When the controller is in a selected state in register access mode, it is set to high level at a predetermined timing. The commonly coupled drains of MO3FET QI 1 and Ql of each noon cycle &UDS are connected to the corresponding internal input bus d s
OO to ds Qwn to ds3Q to ds3m, respectively.

When the DMA controller is in the non-selected state, as described above, both timing signals φ1S and φpc are set to low level. Therefore, the AND gate circuit 1AG1 of each unit circuit UDS is in a non-transmission state, and MO3FF,
TQll is turned on. This allows all internal power buses ds00 to dsQm to ds3 (Lwds3
m is precharged to a high level, like the voltage a of the circuit, through the corresponding MO3FET QII.

When the DMA controller is selected in the register access mode, the timing signal φpC is first set to a high level, and the timing signal φis is set to a high level when the inverted internal input data di0-dim is established. In each unit circuit UDS, when the timing signal φpc is set to high level, the MO3FETQI 1 are turned off all at once, and the precharging operation of the internal input buses d·s00 to dsQm to ds30 to da3m is stopped.

Further, by setting the timing signal φis to a high level, the AND gate circuit AGI enters a transmission state, and its output signal is selectively set to a high level in accordance with the inverted internal input data τ˜dim. Therefore, if the output signal of the corresponding AND gate circuit AGI is at a high level, that is, the corresponding inverted internal input data diO~dim is at a high level, the input data of the corresponding bit is at a logic "0" level.
"MO3FE'l'Ql of the unit circuit UDS is selectively turned on. As a result, internal input buses ds00-dsQm to ds3Q to ds3m corresponding to input data of logic "0" are turned on. MO3FETQI
It is selectively discharged through the circuit and set to a low level like the ground potential of a circuit. At this time, internal input buses ds00 to dsQm corresponding to input data of logic “L”
or ds30 to ds3m are the corresponding MOS F E
Since TQ1 is turned off, it remains at the precharge level, that is, the one-in high level.

As exemplarily shown in FIG. 1, the register group REGGO to REGG3 includes p+1 registers REGOO to R.
EGOp or REG30~I? These registers, each containing EG3p, are connected to the internal power bus dsoO~
dsQm or ds3Q ~d! 131TI and internal output buses dx00 to dxQm to dx30xdx3m
4m+1 unit circuits [including JRG, the unit circuits URG of each register are provided in a latch form by having their input terminals and output terminals cross-connected to each other, although this is not particularly limited. The basic configuration includes two CMOS inverter circuits N1 and N2. Impark circuit N
1 is coupled to the output terminal of the corresponding inverter EBN2, and the corresponding Nant gate circuit N
Output terminal of AG1 and corresponding AND gate circuit AG2
are commonly coupled to one input terminal of each. Needless to say, when the latch of each unit circuit 09G is set to the corresponding input data diO to d1mi (logic "0"), the input terminal of the inverter circuit N1, that is, the inverter circuit N2
A latched state is established in which the level of the output terminal of is set to high level.

One input terminal of the Nantes gate circuit N A G l of the degree circuit URG of the corresponding bit of each register is connected in common for each bit, and the above internal input bus ds corresponds to the input terminal of each unit plane @U RG. .

(1 to dsQm or da3Q to ds3m, respectively. Also, the other input terminal of the Nantes gate circuit NAG1 of each unit circuit URG is commonly coupled for each register, and is connected to the corresponding L-nosister selection circuit R3L. /
Register selection signal 5iOO~3i0p or 5i30~5
i3p is commonly supplied to each. The register selection signals 5iOO-310p to 5130-5i3p are normally at a low level, and when the DMA controller is in the register access mode and in the selected state in the input mode,
At a predetermined timing, the internal address signals aO to at
According to this, it is considered to be alternatively high level.

Corresponding register selection signal 3100-5iop-3
When 130 to 5i3p are alternatively set to high level, the internal input buses dsoo to dsQm or ds30 to ds3m by the Nantes gate circuit NAG1 of each unit circuit URG
A level determination operation is performed. As a result, input data transmitted all at once via these internal input buses is input to one register designated by address signals aO to ai.

On the other hand, the other input terminal of the AND gate circuit AG2 of each unit circuit URG is commonly coupled for each register, and the corresponding register selection signal 3 is sent from the register selection circuit R3L.
000-5oop 1t) Lso30-5o3p are each commonly supplied.

These register selection signals are normally at low level,
When the DMA controller is in the register access mode and in the selected state in the output mode, the internal address signals aO to ai are selectively set to a high level at a predetermined timing. AND gate circuit A of each unit circuit URG
The output terminal of G2 is the corresponding N-channel MO3FET
are respectively coupled to the gates of Q2. MOSFETQ2
The source of is coupled to circuit ground potential. Also, the MO3FE of the unit circuit URG of the corresponding bit of each register
The drains of TQ2 are commonly coupled and further connected to corresponding internal output buses dx00 to dxOm to dx30.
-dx3m, respectively. As described later, these internal output buses are connected to the internal input bus ds00.
Similarly to dsOm to ds30 to ds3m, it is precharged to a high level like the power supply voltage of a normal circuit. Corresponding register selection signal 5ooO=so.

p to 5030 to 5o3pf)
The G AND gate circuits AG2 are all set to a transmitting state. In other words, the AND gate circuit AG2 of each unit circuit URG
The output signal indicates that the data held in the corresponding latch is logic “0”.
”, the corresponding MO3FETQ2 is selectively turned on, the corresponding internal output buses dx00~dxom or dx30~dx3m are selectively discharged, and the circuit As a result, the data held in one register specified by address signals aO to ai is transferred to the corresponding internal output bus dxQO.
-dxQm to dx30 to dx3m are alternatively output to the data multiplexer DMX.

The data multiplexer DMX includes four unit data multiplexers MXO to MX3 provided corresponding to channels CHO to CH3, as exemplarily shown in FIG.
Each unit data multiplexer includes m+1 unit circuits υMX provided corresponding to the internal output data doO-dom.These unit circuits are not particularly limited, but are connected to the corresponding internal output bus dx00 to
P-channel type precharge MO3 provided between dxQm or dx30 to dx3m and the power supply voltage of the circuit
FETQ12 and NOR gate circuit N0G1 for level determination
Includes each.

The gates of MO3FETQI2 of each unit circuit υMX of unit data multiplexers MXO to MX3 are all commonly coupled, and the timing signal φpc is commonly supplied from the bus control circuit BCTL.

As mentioned above, the timing signal φpc is set to a low level when the DMA controller is in the non-selected state, and
When the MA controller is brought into a selected state in register access mode, it is set to a high level at a predetermined timing.

By setting the DMA controller to a non-selected state and setting the timing signal φpc to a low level, each unit circuit UMX
MO3FETQ12 are all turned on. This allows internal output buses dxoO to dxOm to dx30
~dx3m is precharged to a level such as the power supply voltage of the circuit.

One input terminal of the NOR gate circuit N0G1 of each unit circuit UMX is coupled to the drain of the corresponding MOSFET Q12, that is, the corresponding internal output bus dx00 to dxQm to dx30 to dx3m, respectively. Further, all the other input terminals are commonly coupled, and the inverted timing signal φO3 is commonly supplied from the bus control circuit BCTL.

The inverted timing signal φO8 is normally at a high level,
When the DMA controller is in register access mode and output mode, it is set to low level at a predetermined timing. NOR gate circuit N0 of unit circuit UMX of corresponding bit of unit data multiplexers MXO to MX3
The output terminals of G1 are commonly coupled, and their levels are supplied to the data output buffer DOB as inverted internal output data doQ-dom. In other words, the internal output buses dxoO to dxom to dX30 to dx3m are logically ANDed with the inverted timing signal φ03 by the corresponding NOR gate circuit N0G1, and are logically ANDed bit by bit by the connection logic of the output terminal of the NOR gate circuit N0G1. Logical OR operation is performed.

By setting the inversion timing signal φos to a low level, the NOR gate circuits N0CI of each unit circuit UMX are simultaneously put into the transmission state, and the corresponding internal output buses dx00 to d
Level determination operations from xOm to dx30 to dx3m are performed. As mentioned above, the internal output buses dxoO to dxo
m to dx30 to dx3m are precharged to a high level like the voltage of a normal circuit, and are specified by address signals aO to ai when the DMA controller is in the register access mode and selected state in the output mode. Only the internal output bus corresponding to a register group including one register is selectively discharged according to the data held in that register. Therefore, the output signal of the NOR gate circuit N0GI of each unit circuit UMX is generated when the inverted timing signal φ03 is set to a low level and the corresponding internal output bus dx00 to dxOm to dx3
It is selectively set to high level only when 0 to dx3m are discharged to low level. As a result, the inverted internal output data doQ to don are converted to the address signal aO.
It is selectively set to high level according to the data held in one register specified by ~ai.

The data output buffer DOB sends the inverted internal output data ττ] to Ding Ding Hyaku supplied from the data multiplexer DMX to the central processing unit C via the data bus DB.
Send to PU.

As described above, the DMA controller of this embodiment has four sets of internal input buses dsQQxdsQm to d330 to ds provided corresponding to channels C10 to CH3.
3m and internal output bus dxOQ to dxQm to dx3
Including 0~dx3m.

These internal buses have a corresponding register group REGGO.
~p+1 registers REGOO included in REGG3
The input terminals and output terminals of the unit circuits UMX of corresponding bits of ~REGOP to REG30 to REG3p are commonly coupled, respectively.

Internal output bus dx00~dxom or dx30~dx
3m is coupled to the corresponding unit circuit UMX of the data multiplexer DMX, and is logically ORed with negative logic for each bit, thereby generating the inverted internal output data doQ to do
m is formed. Each internal power bus and internal output bus are
When the DMA controller is in a non-selected state, it is precharged to a high level like the circuit power supply voltage, and the DMA
It is selectively discharged according to the data transmitted when the controller is selected in register access mode. For these reasons, in the DMA controller of this embodiment, although a relatively large number of register groups are provided, the register groups REGGO to REGG3 .
Data distribution circuit DDS and data multiplexer DMX
−? ) The required layout area for selection signal lines, etc. is reduced, and the drive current for the internal bus is significantly reduced.

This makes it possible to reduce the cost and power consumption of a microcomputer including a DMA controller.

As shown in the above embodiment, when the present invention is applied to a DMA controller built in a one-chip micro combinator, the following effects can be obtained. That is, (1) a so-called dynamic bus in which a plurality of internal buses included in a DMA controller etc. are normally precharged to a predetermined level and then selectively and alternatively discharged according to data transmitted at a predetermined timing; By using negative logic to perform OR combinations without selecting according to the bus selection signal, the circuit configuration of register groups, data distribution circuits, data multiplexers, etc. can be simplified, and the layout area required for internal buses and selection signal lines can be reduced. You can get the effect that you can.

(2) In item (1) above, each internal bus is normally precharged to a high level such as the power supply voltage of the circuit, and is selectively discharged to a low level such as the ground potential of the circuit at a predetermined timing. This has the effect of significantly reducing the drive current.

+31 The above items (1) and (2) have the effect that it is possible to reduce the cost and power consumption of a DMA controller and a microcomputer including the DMA controller.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in FIG. 1, the AND gate circuit AGI of the data distribution circuit DDS may be provided in common for four channels, and the NOR gate circuit N0G1 of the data multiplexer DMX may be provided as a logical OR of four people in the previous stage. By providing a circuit, it can be shared by four channels as well.

Furthermore, the discharge MOSFETs provided in the data distribution circuit DDS and the unit circuits of each register group may use, for example, open collector bipolar transistors. Internal input bus dsOO~ds
Om to ds 30 to ds3m and internal output bus d
x00 to dxOm to dx30 to dx3m may be integrated into one as an input/output bus. The specific circuit configuration of each unit circuit of the data distribution circuit DDS, the register groups REGGO to REGG3, and the data multiplexer DMX can take various embodiments. In Figure 2, DM
The number of channels provided in the A controller may be arbitrary, and an internal high-power bus and an internal output bus may be provided corresponding to each bit of data. DM
The block configuration of the A controller and the combination of control signals and address signals can take various embodiments.

In the above explanation, the invention made by the present inventor was mainly applied to a DMA controller built in a microcomputer, which is a field of application that has become popular, but the present invention is not limited to this, for example. The present invention can also be applied to devices used semi-independently as DMA controllers and other various combinator peripheral devices having similar internal buses. Alternatively, the present invention can be widely applied to digital devices having a plurality of internal buses logically coupled to a plurality of buses, and semiconductor integrated circuit devices including such digital devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, a plurality of internal buses included in a DMA controller, etc. are usually precharged to a predetermined level and then selectively and alternatively discharged according to data transmitted at a predetermined timing. By ORing with negative logic without selecting according to the signal, [・Simplifies the circuit configuration of data distribution circuits and data multiplexers for selecting register groups and internal buses, and improves the layout of internal buses and selection signal lines. The required area can be reduced.

In addition, by making the internal bus a dynamic bus,
The driving current can be significantly reduced. This allows the DMA
It is possible to reduce the cost and power consumption of microcomputers including controllers.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a data distribution circuit, register group, and data multiplexer of a DMA controller to which the present invention is applied, and FIG. 2 is a circuit diagram showing an embodiment of the data distribution circuit, register group, and data multiplexer of FIG. 1. D containing
Block Diagram Showing One Embodiment of MA Controller FIG. 3 is a circuit block diagram showing an example of a DMA controller developed by the present inventors prior to the present invention. DOS...data distribution circuit, DSO~DS3...unit data distribution circuit, UDS...data distribution port VB unit circuit, REGGO~REGG3...L/register group R
EGO~REGp...Register, URG...Register unit circuit, DMX...Data multiplexer, MX
O-MX3...Unit data multiplexer, υMX・
...Data multiplexer unit circuit, Q1-Q2...
N-channel MO3FET, Ql 1~Q12...P
Channel MOS FET%N1~N2...Inverter circuit, ACI~AG2...And gate circuit, N
AGl...Nand gate circuit, N0G1...Nor gate circuit. To DM8...DMA controller, BCTL...
・Bus control circuit, DIB... data manual buffer, D
OB...Data output cover sofa, RSL...Register 7.
selection circuit, 8 DB...address buffer, A;D-
-・Address increase/decrease circuit, CHO-CH3...Chin δ
CF'U...Central processing unit, MM...Main memory, 70E...I/O device.

Claims (1)

[Claims] 1. Usually precharged to a predetermined level, selectively and alternatively discharged according to data transmitted at a predetermined timing, and finally 1. A semiconductor integrated circuit device comprising a plurality of internal output buses that are connected to one output bus. 2. Each of the internal output buses has outputs from a plurality of unit circuits that are selectively activated according to a predetermined selection signal and selectively and alternatively discharge the corresponding internal output bus according to the data. 2. The semiconductor integrated circuit device according to claim 1, wherein the terminals are commonly coupled. 3. The semiconductor integrated circuit device further includes a plurality of internal input buses which are in the form of a dynamic bus similar to the internal output bus and to which the input terminals of the plurality of unit circuits are commonly coupled. The semiconductor integrated circuit device according to the range 1 or 2. 4. The semiconductor integrated circuit device according to claim 1, 2, or 3, wherein the unit circuit is a register unit circuit. 5. Claims 1, 2, 3 or 5, wherein the semiconductor integrated circuit device includes a DMA controller, and the register is included in the DMA controller. 4. The semiconductor integrated circuit device according to item 4.