JPH01136487A - Square wave quantizing circuit - Google Patents

Abstract

PURPOSE:To attain simple and inexpensive digital vertical synchronizing detection by quantizing a square signal such as a composite synchronizing signal through the provision of plural latch circuits and outputting a digital signal of the set bit number. CONSTITUTION:Two FFs 25a, 25b are provided to quantize a composite synchronizing signal into two bits as two latch circuits and the FF 25a, 25b fetch periodically the composite synchronizing signal based on the sampling pulse at an input terminal 24. The output signal at a Q output terminal (q) of the FF 25a, 25b changes as a binary level in response to the high/low level of the composite synchronizing signal as shown in figures (d), (e) representing bits B1, B2. Then two bits B0, B3 of the LSB, MSB in the 4-bit B0-B3 go always to a level of logic 0 as shown in figures (c), (f). Thus, a simple and inexpensive quantization circuit 28 provided with the two FFs 25a, 25b is provided to output a digital signal of 4 bits B0-B3 of the preset bet arrangement.

Description

[Detailed description of the invention] [Industrial application field] This invention provides a horizontal signal that is reproduced and separated from the video signal.

The present invention relates to a square quantization circuit that quantizes a square wave signal such as a vertical composite synchronization signal and outputs a digital signal of a predetermined number of bits.

[Conventional technology]

Conventionally, a liquid crystal display type television receiver, which is an example of a television receiver, has a configuration approximately as shown in FIG.
Based on the reception selection of the tuner (2) connected to antenna +11, the video intermediate frequency amplifier,
In other words, the video detection circuit (
4), the video intermediate frequency signal of the received channel is output, and the signal is sent from the detection circuit (4) to the sync separation circuit (5), the video amplifier (6), the chroma amplifier (7), and the audio intermediate frequency amplifier, that is, the SIF amplifier ( 8), a video signal in a composite signal format is output.

Note that the receiving gain of the tuner (2) is automatically controlled by an automatic gain control circuit, that is, an AGC circuit (9) based on the detection level of the detection circuit (4).

Then, the audio intermediate frequency signal is extracted by the amplifier (8), and the extracted audio intermediate frequency signal is detected by the audio detection circuit (lO), and is transmitted from the detection circuit (lO) to the speaker via the audio amplifier (11). (The received audio signal is output in one step.

On the other hand, the synchronization separation circuit (5) separates and extracts a horizontal and vertical composite synchronization signal from the input video signal, for example, a square wave signal with a horizontal scanning period Th shown in FIG. Regenerates a vertical synchronization signal from the signal,
The vertical synchronization signal is transmitted to the liquid crystal display panel (PLL provided for AC drive control in circuit (13), phase detection circuit (16) in circuit (14)
).

At this time, the oscillation signal of the voltage controlled oscillator of the PLL circuit (I4), that is, the VCO (+6), is divided by the counter 07), and the polarity switching circuit (X, Y, which drives the display panel θ4) A timing pulse is output to each of the direction (horizontal, vertical) registers (19) and (20), as well as a specific branch signal of the counter (17).

That is, a branch signal consisting of a -timing pulse with a vertical scanning period (1/60 sec) outputted to the polarity switching circuit (181) is inputted to the detection circuit (+5).

Then, a voltage signal proportional to the phase difference between the vertical synchronization signal of the synchronization separation circuit (5) and the branch signal of the counter Oη is output from the detection circuit (15) to the VCO (+61), and the voltage signal proportional to the phase difference between the vertical synchronization signal of the synchronization separation circuit (5) and the branch signal of the counter
The oscillation frequency of +61 is controlled to synchronize with the received video signal.

In addition, the amplifier fs+ # [7] connects the detection circuit (4
), the luminance and chroma components of the video signal are separated,
At the same time, the luminance component and chroma component signals of the amplifier +611 [71 are input to the three primary color demodulation circuit (21), and the three primary color signals of the received video signal are demodulated and formed by the demodulation circuit @l).

Incidentally, the phase shift of the chroma component signal of the amplifier (7) is corrected by an automatic phase control circuit, that is, an APC circuit (b).

The three primary color signals of the demodulation circuit (21) are then transferred to the switching circuit (21).
The display control switch circuit for each horizontal line of the panel (13) is switched (
23) supplied to each.

At this time, the shift register (19) e h+ receives, for example, 15.75KH output from the synchronous separation circuit (6).
z, 60Hz horizontal and vertical scanning period signals and a counter (one timing pulse), each switch circuit 1'8 is turned on sequentially at the timing of each pixel in the horizontal direction, , each horizontal line of the panel (!(
Display the video received from (to).

In addition, Japanese Patent Application Laid-open No. 62-31278 (HO4N 5/
66) also describes a liquid crystal display type television and John receiver that operates in the same manner as in FIG.

By the way, not only the liquid crystal display type television receiver, but also the CR1 display type television receiver.

Alternatively, the video tape recorder may receive a composite synchronization signal separated and extracted from the received video signal, that is, a composite synchronization signal as shown in FIG.
In order to reproduce and form a vertical synchronization signal from a square wave signal such as ), vertical synchronization detection is performed by a synchronization separation circuit (5).

The vertical synchronous detection of the synchronous detection circuit (6) is often performed by integral processing using an analog filter.

Therefore, when circuits are integrated in order to make the receiver smaller, a large number of resistors and capacitors are required as external components, and external components require a large area and are expensive. .

On the other hand, with recent advances in digital processing technology, it has been proposed to perform vertical synchronization detection digitally using digital filters such as transversal filters; Therefore, the above-mentioned inconvenience is solved.

By the way, since the square wave signal such as the above-mentioned composite synchronization signal is a signal that converts into binary levels, basically the high level and low level of the signal are regarded as a 1-bit level change.
The composite synchronization signal can be processed as is by a digital filter as a 1-bit quantized signal.

However, when a square wave signal such as a composite synchronization signal is quantized by one bit, the quantization error becomes very large (for example, a vertical synchronization signal cannot be accurately detected).

Therefore, when vertical synchronization detection is performed digitally, a square wave signal such as a composite synchronization signal is usually converted into a square wave signal such as a composite synchronization signal based on sampling pulses at minute sampling intervals as shown in FIG. As shown, a digital signal of preset bits is sampled, quantized, and supplied to a digital filter.

The above-mentioned sampling and quantization are performed, for example, by an A/D conversion circuit equipped with a sample hold circuit and a bit comparison for quantization.

Note that all bits mentioned above do not necessarily change to logic 1 or 0 due to quantization, but may be set taking into account the number of input bits of the digital filter in the subsequent stage, etc. In this case, the R bit Some of the bits are always fixed to logic 0 or 1 regardless of quantization.

[Problem that the invention seeks to solve]

By the way, when a square wave signal such as a composite synchronization signal is quantized using an A/D conversion circuit and converted into a K-bit digital signal, the A/D conversion circuit uses a sample hold circuit and a large number of circuits as described above. This method requires a complicated circuit including a comparator and a reference signal generator for each comparator, and has the problem that a complicated and expensive circuit is required to quantize the square wave signal.

A technical object of the present invention is to enable quantization of a square wave signal using a simple and inexpensive circuit.

[Means for solving problems]

In order to solve the above problem, in a square wave quantization circuit that quantizes a square wave signal and outputs a digital signal of a predetermined number of bits, the square wave signal is taken in at a predetermined sampling period. Seven lip-flops (25a) function as multiple latch circuits that output value level signals.
), (25b) are provided for each bit whose contents change due to a change in the binary level of the square wave signal.

[Effect]

Therefore, according to this invention, the flip-flop (2
The square wave signal is quantized by 5a) and (25b), and 7 lips and 70 bits (25a) and (25b) form each one bit of the quantized square wave signal.

Therefore, with a simple and inexpensive configuration in which flip-flops (25a) and (25b) are provided instead of the A/D conversion circuit, square wave signals can be quantized, and the technical problem can be solved.

[Embodiment] Next, this invention will be explained in detail with reference to FIGS. 1 and 2 showing one embodiment thereof.

Figure 1 shows how the composite synchronization signal used for vertical synchronization detection is quantized into 2 bits, and the 4-bit digital signal with K=4 is converted into 4 bits.
This shows the case of outputting to a bit input digital filter.
In the figure, (23) is the input terminal for the composite synchronization signal shown in FIG. 2(a), (24) is the input terminal for the sampling pulse at the sampling period shown in FIG. 2(b), and (25)
a) and (25b) are two D-type flip 70 tubes (hereinafter referred to as FF), and the data input terminal (d) and clock terminal (ck) are connected to the input terminal (to), respectively, and the latch Form each circuit.

side is an input terminal fixed to logic 0 ground level, (2
7a), (27b), (27c), and (27d) are the 4 bits BO, Bl, B in order from the LSB of the square wave quantization circuit.
2. This is the output terminal of B3, and the LSB and MSB bits 13o whose contents do not change due to quantization.The output terminals (27a) and (27d) of B3 are the respective q output terminals (Q).
It is connected to the.

Reference numeral 9) is a 4-bit input digital filter, which performs low-pass filter processing on the 4-bit Bo-B3 digital signal and outputs a vertical synchronizing signal.

In this embodiment, in order to quantize the composite synchronization signal to 2 bits as described above, two FFs (25a) are used.
, (25b) are provided as two latch circuits, and the input terminal FF (2) is connected to the sampling pulse of input terminal 4).
5a) and (25b) periodically capture the composite synchronization signal,
At this time, F F (25a), (25b) (7)
The output signal of the Q output terminal (q) is bit B1. As shown in FIGS. 2(d) and 2(e) showing B2, the binary level changes depending on the high level and low level of the composite synchronizing signal.

On the other hand, the number of input bits of the filter array 9) is set to 4 bits, and the 4 bits Bo to B3 starting from the LSB are marked, 1, 1. Oj, ro, 0. When the input signal becomes O or OJ, the filter screen processes the input signal as a logic 1 or 0 signal, respectively.

Then, of the 4 bits BO to B3, 2 of the LSB and MSB
As bits BO and B3 are always at the logic O level as shown in Figure 2 (C) and (f), 2 bits Bo
The signals at the output terminals (27a) and (27d) of , B3 consist of the logic O signal of the input terminal □□□, and the signals of the composite synchronization signal 2
2 bits Bl, B whose contents change depending on the value level change
Only the signals of output terminals (27b) and (27c) of 2 are F.
It consists of the output signal of the Q output terminal (q) of F (25a) and (25b).

Therefore, in the case of the above embodiment, the sampling circuit 4
It is possible to quantize a complicated and expensive synchronization signal having multiple comparators, etc., and output a 4-hit digital signal of BO to B3 with a preset bit arrangement.

By the way, in the above embodiment, depending on the number of input bits of the filter (29), 4 bits BO~B! However, if a 2-bit input digital filter is used instead of the filter (2υ), F F (25a)
.

Only 2 bits B1 and B2 consisting of the output signal (25b) need to be output from the quantization circuit (28).

Note that the number of latch circuits such as FFs should correspond to the number of quantization bits, and the number of quantization bits to the number of bits K depends on the number of input bits of the digital filter in the subsequent stage. Of course, it is also possible to set .

Of course, the present invention can be applied not only to vertical synchronous detection but also to quantization Gζ of various square wave signals.

〔Effect of the invention〕

As described above, according to the square wave quantization circuit of the present invention,
Instead of a conventional A/D conversion circuit, multiple latch circuits can be installed to quantize a square wave signal such as a composite synchronization signal and output a digital signal with a set number of bits. It is possible to perform synchronous detection easily and inexpensively.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the square wave quantization circuit of the present invention, FIGS. 2(a) to (f) are timing charts for explaining the operation of FIG. 1, and FIG. 3 is a liquid crystal display type guchiard. It is. (23)...Composite synchronization signal input terminal, C4)...
Sampling pulse input terminals, (25a), (25b
)···flip flop.

Claims (1)

[Claims] (1) In a square wave quantization circuit that quantizes a square wave signal such as a composite synchronization signal separated and reproduced from a video signal and outputs a digital signal with a predetermined number of bits, the square wave signal is captured at a predetermined sampling period. A square wave quantization circuit characterized in that a plurality of latch circuits that output binary level signals are provided for each bit whose contents change depending on a change in the binary level of the square wave signal.