JPH01135882U - - Google Patents

Info

Publication number
JPH01135882U
JPH01135882U JP1988135789U JP13578988U JPH01135882U JP H01135882 U JPH01135882 U JP H01135882U JP 1988135789 U JP1988135789 U JP 1988135789U JP 13578988 U JP13578988 U JP 13578988U JP H01135882 U JPH01135882 U JP H01135882U
Authority
JP
Japan
Prior art keywords
vtr
receiver
receiving
switch means
scrambled broadcasting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1988135789U
Other languages
Japanese (ja)
Other versions
JPH0713326Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988135789U priority Critical patent/JPH0713326Y2/en
Publication of JPH01135882U publication Critical patent/JPH01135882U/ja
Application granted granted Critical
Publication of JPH0713326Y2 publication Critical patent/JPH0713326Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例のブロツク図、第2図
はロジツク回路の回路図、第3図、第4図は従来
例のブロツク図、第5図は従来例のための説明図
である。第6図は他の実施例の回路図である。 10……VTR、S……スイツチ手段、50
……ロツク回路、70……デコーダ、72……T
V受信機。
Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a circuit diagram of a logic circuit, Figs. 3 and 4 are block diagrams of a conventional example, and Fig. 5 is an explanatory diagram for the conventional example. . FIG. 6 is a circuit diagram of another embodiment. 10...VTR, S4 ...Switch means, 50
...Lock circuit, 70...Decoder, 72...T
V receiver.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] スクランブルデコーダとTV受信機とに接続さ
れるスクランブル放送受信用VTRにおいて、前
記スクランブルデコーダの入力として、前記TV
受信機のチユーナ出力と、前記スクランブル放送
受信用VTRのチユーナ出力を選択するスイツチ
手段と、前記スクランブル放送受信用VTRの電
源オフ状態には前記スイツチ手段をTV受信機側
に制御するロジツク回路を備えることを特徴とす
るスクランブル放送受信用VTR。
In a scrambled broadcast receiving VTR connected to a scramble decoder and a TV receiver, the TV
A switch means for selecting a tuner output of the receiver and a tuner output of the VTR for receiving scrambled broadcasting, and a logic circuit for controlling the switch means to the TV receiver side when the power of the VTR for receiving scrambled broadcasting is turned off. A VTR for receiving scrambled broadcasting, which is characterized by the following.
JP1988135789U 1987-10-20 1988-10-18 VCR for receiving scrambled broadcast Expired - Lifetime JPH0713326Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988135789U JPH0713326Y2 (en) 1987-10-20 1988-10-18 VCR for receiving scrambled broadcast

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP16011187 1987-10-20
JP62-160111 1987-10-20
JP1988135789U JPH0713326Y2 (en) 1987-10-20 1988-10-18 VCR for receiving scrambled broadcast

Publications (2)

Publication Number Publication Date
JPH01135882U true JPH01135882U (en) 1989-09-18
JPH0713326Y2 JPH0713326Y2 (en) 1995-03-29

Family

ID=31718969

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988135789U Expired - Lifetime JPH0713326Y2 (en) 1987-10-20 1988-10-18 VCR for receiving scrambled broadcast

Country Status (1)

Country Link
JP (1) JPH0713326Y2 (en)

Also Published As

Publication number Publication date
JPH0713326Y2 (en) 1995-03-29

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