JPH01135037A - Pattern inspection device - Google Patents

Abstract

PURPOSE:To reliably extract the features of various patterns by preparing a plurality of kinds of means for extracting any defect and providing means for selecting one among said defect extracting means. CONSTITUTION:An image as an object 11 to be measured such as a photomask is imaged on a sensor 13 after passage of a focusing lens 12. The image information obtained by the sensor 13 is converted into binary data through a binary circuit 14, and inputted into a feature extracting circuit 15. A plurality of kinds of templates for feature extraction are prepared in the feature extracting circuit 15, and an optimum one for the defect detector of the object 11 to be measured is selected, whose output is a defect signal. The template 17 is selected by an output from a parameter setting circuit 16. Since a template shape is properly selected in response to the shape of a pattern to be inspected, false information is reduced to form reliability. In addition, the general-purpose property of the title pattern inspection device is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pattern inspection device for printed circuit boards, LSI photomasks, etc., and particularly to a pattern inspection device with high versatility and reliability.

[Conventional technology]

The pattern inspection device has a percentage of the binary pattern to be measured.
Some methods employ a method of overlapping image extraction templates to extract pattern features and detect pattern defects. Related to this device is, for example, ``Automation of LSI photomask pattern outer metal inspection by feature comparison'' in Proceedings of the Society of Instrument and Control Engineers, Vol. 19, No. 11, pages 903 to 908.

FIG. 8 is a diagram showing the superposition of the binarization pattern and the template in this device. The hatched part of the binarized pattern 24 is @1', and the outside thereof is 10'. The template is peripheral tfls 22-
a, 22-b and a central portion 23.

As shown in FIG. 8, all the pixels of the binarized pattern in the peripheral parts 22-a and 22-b are @0'', and all the rows 25-a and 25-b+25-c in the central part 23 If the "1" part of one or more pixels is blank, the binarization pattern 24
If there is a protrusion on the surface, it will be beneficial.

FIG. 9 is an implementation circuit diagram of the above template in the delivery technology. The input binarization pattern is transferred to the shift register array 31 and the image cutting circuit 6? The pixel signals are taken out as pixel signals according to the location of the pattern from the cutout terminals 53 arranged pixel by pixel.

Out of the cutout terminal 35, the peripheral portion 22-”v 2 of the tensile plate
All those corresponding to pixels 2-b are input to the gate 36, and the gate 36 outputs 1'' when all of the inputs are 10''. In addition, the template center portion 25 of the cutout terminal 53
The gates 37-a and 57 corresponding to the pixels in each row are
-b.

57-C. Gates 57-a, 37-be
57-c outputs "1" on gate 6th when the input of one or more pixels is @1". Gate 36.37-a
, 57-b, 37-c, the gate 38 inputs the outputs of ``0'' when all the pixels in the peripheral part of the ten-rate are ``0'' and there is one or more pixels 11'' in all the rows in the center.
Outputs 1”.

[Problem that the invention seeks to solve]

In the above-mentioned prior art, the shape of the template, which is a rounding means for extracting the features of the binarized pattern, is fixed to the peripheral parts 22-a, 22-b and the central part 23 as shown in FIG. The problem is that only specific features of the binarized pattern can be detected, and when trying to extract other features, there are many false alarms and lack of robustness.

The purpose of the present invention is to provide a versatile pattern loss device that can reliably extract the characteristics of various patterns. It is about providing.

[Means for solving problems]

The purpose of the above is to provide means for appropriately selecting pixels constituting a template shape, and to provide a method for selecting multiple types of template shapes preset from the outside. Q can be achieved by appropriately configuring the optimal template shape.

[Effect]

Since the shape of the tensile rate is appropriately selected according to the shape of the pattern to be attacked, there are fewer false alarms (reliability is improved), and the versatility of the pattern surveillance device is also increased.

〔Example〕

Below is an example of the book @ Ming? Figures 1 to 7? Refer to and explain.

'$J1 is a block diagram showing one embodiment of the present invention. An image of a measurement object 11 such as a photomask is formed on a sensor 15 after passing through a condenser lens 12 . The image information obtained by the sensor 13 is converted into binary data by the binarization circuit 14,
It is input to the feature extraction circuit 15. A plurality of templates 17 for feature extraction are prepared in the feature extraction circuit 15, and the one most suitable for detecting a defect in the object to be measured 11 is selected, and its output is used as a defect signal. The template 17 is selected by the output of the parameter setting circuit 16.

FIG. 2 shows an example of the shape of a template for feature extraction.

In this embodiment, templates 17 having 54 shapes from cL to 4 are prepared. The tensile rate shape explained in FIG. 8 is the tensile rate α in FIG. 2. The parameter setting circuit 16 appropriately selects one of the SFI-class tensile rates α to 4.

FIG. 3 is a detailed configuration diagram of the feature extraction circuit. Note that in FIG. 3, circuit elements denoted by the same reference numerals as in FIG. 9 are the same as those explained in FIG.

The binarized pattern input to the feature extraction circuit 12 according to this embodiment is extracted from the cutout terminals 33 arranged pixel by pixel by the shift register array and the image cutout circuit 52. The output of the cutting terminal 33 is input to the template peripheral pixel selection circuits 56-Q, 56-b and the center pixel selection circuit 56-C. Broken lines 50-a, 50-b,
The part indicated by 50'-c is a collection of pixels representing the shape of the template shown in FIG. The signals 511-522 are pixel signals from all cutout terminals 36 within the broken line 50-a. In addition, the signal 500.
507, 508, etc. are pixel signals not included in the broken line 50-4, and the signal 510 is a pixel signal not included in the broken line 50-C.

The selection circuits 56-a, 56-b, and 56-C input pixel signals from the cutout terminals 33 at all positions that may be used as pixels in the peripheral and central parts of the template,
Template shape parameter decoder 57-a*5
A pixel is selected according to the control signals from 7 b and 57 c, and the determination result is output to the gate 59 .

The decoder 57-a inputs a parameter representing the shape of the peripheral part of the template (the shape of both ends of each template shown in FIG. 2) from the terminal 58-a, and sends a signal corresponding to the parameter to the selection circuit of the peripheral part of the template. 56-L,
56-b. The decoder 57-b has a terminal 58
A parameter representing the number of pixels in the direction of the length of the template center (the length of the center of each template shown in FIG. 2) is input from -b to the center selection circuit 56-C. Since the position of the pixels in the peripheral part of the template also depends on the number of pixels in the longitudinal direction of the central part, it is also output to the peripheral part selection circuit 56-6, 56-b.

The decoder 57-C inputs a parameter representing the number of pixels in the width direction of the center of the template (vertical direction of the center of each template shown in FIG. 2) from the terminal 5-Cρ), and according to the parameter. The selected signal is sent to the central selection circuit 56-C.
Output to.

As the decoders 57-a, 57-b, and 57-c, a ROM is used in which the parameter input is connected to the address and the output is connected to the data.The decoders 57-a, 57-b, and 57-c are programmed to obtain output logic according to the input parameters. has been done. Furthermore, R
Needless to say, it can be constructed not only from an OM but also from a PLD (programmable logic e-device), a gate array, or a set of general-purpose logic elements. The internal circuits of the selection circuits 5s-a, 56-b and 56-C will be explained below.

FIG. 4 is a diagram showing the basic configuration of the selection circuit. When the signal selection circuit is configured by a logic circuit, as shown in FIG. 4, by inputting an n-bit parameter signal 92 to the signal selection circuit 91, one of the 21 input signals 95 is selected, and the output signal is Output as 94. A pixel selection circuit is configured by associating pixels 95 with input signals 96, respectively.

FIG. 5 is a specific configuration diagram of the selection circuit 56-a. The input pixel signal 61 is input to the data selector 62 according to the arrangement of pixels. Signal 50 N5 shown in FIG.
08 corresponds to the signal 50aB in FIG. The data selector 62 receives a signal and a control signal according to the number of pixels in the length direction of the central portion of the tensile rate through a terminal 64 from the decoder 57-b (FIG. 3), and selects a signal from the input terminal 63-b based on the control signal. 4.63-b, 65-
Select either one of c or 65-d and connect output terminal 6.
Output to 5-C. In the case of the template shown in FIG. 2), the input terminal 63-C is selected and the pixel signal 50
6 is output, but the pixel signal 50s 508 is the dashed line 50
It is not output because it is outside of -a.

The signal from the output terminal 66-e is sent to the gates 65 and 650~
656 input terminal 66-4. The gate 65 transmits a signal corresponding to the shape of the peripheral portion of the template from the decoder 57-2 through the terminal 67fc to the enable terminal 66-b.
, and based on the signal, the intermittent connection between the plow input terminal 66-4 and the output terminal 66-C is controlled. This makes the dashed line 50
651-656 are input to the gate 68. However, input terminals of the gate 650 that are outside the dashed line 50-a, that is, the pixel signal 500, are not input to the gate 68. Gate 68 outputs @1'' to output terminal 69 when all input signals are @0''.

Since the selection circuit 56-b is the same as the pixel arrangement of the selection circuit 56-a shown in FIG. 5 except that it is laterally symmetrical, illustration and description thereof will be omitted.

FIG. 6 is a configuration diagram of the selection circuit 56-C. terminal 71
Pixel No. 11 inputted from the input terminal 7 of the gate 72
5-4. Signals 511)-52 shown in FIG.
2 corresponds to the signal 51 (h-622) in FIG.

The gate 72 inputs a signal from the decoder 58-b through all the terminals 74 to the gold enable terminal 73-b according to the number of pixels in the direction of the center of the template, and based on the signal, inputs a signal from the input terminal 73-α It is output to the gate 75 through the output terminal 73-cf. Here, the pixel numbers 511-522 within the dashed line 50-C are output to the gate 75;
Pixel No. 15 510 that is not within ○-C is not output. As a result, the gate 75 is connected to one or more pixels in one row of central pixels.
If 1" exists, the output will be 11". The gate 75 transmits a signal from the decoder 58-C through the terminal 77 to the enable terminal 7 according to the number of pixels in the width direction of the central portion of the ten-rate.
6, and only the output of the gate 75 in the row selected as the center of the template is output to the gold gate 78. As a result, when one or more @1'' is input in each line in all lines in the center of the template note as shown in the example of 5o-c, the output of all gates 75 will be @1. "@1" is output from the gate 78 to the output terminal 79.

FIG. 7 is a configuration diagram of a pattern inspection apparatus according to a second embodiment of the present invention. In FIG. 7, the same reference numerals as in FIG. 1 indicate the same parts. In this example, the condenser lens 12.8
2 and sensor 15. B5, two sets each of a binarization circuit 14.84 and a feature extraction circuit 15.85 are provided. Then, the same type of measurement object 1181 is inspected at the same time, and the output of the feature extraction circuit 15.85 is input to the comparison circuit 87 as a pattern defect candidate, and the comparison result is determined as a defect. The parameter setting circuit 86 has the same operating principle as the parameter setting circuit 16 shown in FIG. 1, but is capable of outputting the same or different parameters to the two feature extraction circuits 15 and 18 as appropriate. This configuration enables highly accurate pattern inspection with fewer false alarms.

According to each of the above embodiments, it is possible to change the template shape of the feature extraction circuit without operating the pattern inspection device, so the template shape can be changed while checking the inspection output to make it most suitable for the inspection of the measurement target. understand and use templates.

〔Effect of the invention〕

According to the present invention, the optimal defect detection number Nr can be selected according to the shape of the pattern to be inspected, so that a highly accurate pattern inspection apparatus jii can be provided.

[Brief explanation of the drawing]

FIG. 1 shows the a factor of the pattern inspection apparatus according to the first embodiment of the present invention, FIG. 2 shows the template metal of each shape, and FIG.
The figure is a detailed configuration diagram of the feature extraction circuit shown in Figure 1, Figure 4 is a principle configuration diagram of the selection circuit, Figure 5 is a specific configuration diagram of the peripheral selection circuit shown in Figure 5, and Figure 6 is the 7 is a configuration diagram of a pattern inspection device according to a second embodiment of the present invention, FIG. 8 is an explanatory diagram of a binarized pattern and a template, and FIG. 9 is a detailed diagram of the center selection circuit shown in the figure. 1 is a configuration diagram of a conventional feature extraction circuit. 15... Feature extraction circuit, 16... Parameter setting circuit (selection circuit), 56-4.56-b... Template peripheral pixel selection circuit, 56-C... Template center pixel selection circuit. 2nd violent attack 40 8th flash r-11ゝ----□)

Claims (1)

[Claims] 1. Means for two-dimensionally scanning a circuit pattern and photoelectrically converting the binary pattern information to detect it as an electrical signal, and means for extracting pattern defects from the characteristics of the electrical signal. 1. A pattern inspection apparatus comprising: a plurality of types of means for extracting the defects; and a means for appropriately selecting one of the plurality of types of defect extraction means. 2. The pattern inspection apparatus according to claim 1, wherein the selection means electrically performs selection control.