JPH01134758A - Integrated circuit for reproducing cd - Google Patents

Abstract

PURPOSE:To search even the data of a next tune only in designating the data of one tune by storing the data of the tunes recorded onto a CD in a circuit beforehand. CONSTITUTION:When an R/W control circuit 15 detects the track number '00' of the second area of a subcode Q fetched in a first shift register, a storage circuit is made into a writing condition, an address control circuit 14 impresses the track number data of a third area to the storage circuit, and the data of a first area are stored. Consequently, all the data of the tunes recorded onto the CD are stored into the storage circuit. On the other hand, a data requesting signal is impressed from an external part, the R/W control circuit 15 makes the storage circuit into a reading condition, the data are read, and they are transferring-held in a first latch circuit 24. Further, for the address data, +1 is executed by an adding means, next designating address data are prepared, the data stored into the next address are read, and they are transferring-held in a second latch circuit 25. Thus, by designating the data of a certain tune, the data of the next tune can be simultaneously obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to an integrated circuit for reproducing a CD (compact disc), and particularly to an integrated circuit for reproducing a subcode Q read from a disc.
This is related to the processing of

(b) In the conventional CD, an 8-bit subcode is attached to a total of 32 symbols, 24 information symbols (8 bits) and 8 parity symbols (8 bits), and these are
M(8-14) modulation is performed and it can be recorded on the disk as one frame of 588 channel bits together with a 24-bit frame synchronization signal. The subcodes are P, Q, and R.

Channels S, T, U, V, and W are assigned, and channels P and Q are used for program functions such as finding the beginning of a song and playing it in a preset order. Each channel of these subcodes is composed of 98 frames, that is, 98 bits, and in particular, the format of the subcode Q is as follows:
2 bits of S, 4 bits of control data, 4 bits of address data, 72 bits of data, and 16 bits of CRC (Cyclic Redunda).
ncy Code).

FIG. 2 shows the data format of the subcode Q. As shown in FIG. 2, the subcode Q includes, in addition to control data and address data, the track number, index, and time (seconds) of the song in the A-I area represented by an 8-bit BCD code. (minutes), frames in the song, cumulative time (seconds) (minutes), and cumulative number of frames are assigned. Normally, this subcode Q is used to display the number of the track being played, the playing time, etc., but it is recorded in the lead-in area provided on the inner circumference of the CD for the purpose of finding the beginning of the song and programming functions. The subcode Q is assigned the data of the song recorded on the CD and the data of the lead-out area provided on the outer periphery of the CD. That is, in the case of the subcode Q in the lead-in area, as shown in FIG. 3, area A is ``roo'' and area B is
is assigned the track number of the recorded song, areas G and H are assigned the start time of the song corresponding to the track number, and area engineering is assigned the number of frames from the start of the track to the beginning of the song. Furthermore, in area B, ' A
There are indexes OJ, 'AIJ, and 'A2J.' In 'AO', the track number of the first song is recorded in area G, and in area G of 'A1', the track number of the last song is recorded. '', the start time of the lead-out area is recorded in areas G and H, and the number of frames until the start of the lead-out area is recorded in area I. Furthermore, in the case of a CD, the maximum number of songs that can be recorded is 99, ie, n-99, so the number of subcodes Q in the lead-in area is 102 at most. A circuit for extracting such a subcode Q is usually built into a CD playback integrated circuit. The subcode output circuit of a conventional CD playback integrated circuit detects a frame synchronization signal from the EFM signal read from the disc, and demodulates the EFM signal following the frame synchronization signal to obtain an 8-bit subcode. , the data of the Q channel in the subcode is applied to the shift register, and the data of the subcode Q is completed by accumulating the subfood Q for each frame. It was outputting to . The microcomputer uses the serially transferred subfood Q to display the song number, time, etc., and also uses it as data for moving the optical pickup to the target value.

A technique similar to that described above is described in detail in Japanese Patent Laid-Open No. 60-83261.

(c) Problems to be solved by the invention When using the above-mentioned CD playback integrated circuit, a control microcomputer that can be connected to the outside can display the number of songs,
In order to display the time or select a program, the subcode Q in the lead-in area must be retrieved and stored in the memory circuit in advance. However, as mentioned above, the subcode Q of the lead-in area is 102 at maximum, and the number of bits of the data is 8X3X102=2448.
It's a bit. On the other hand, the memory circuit (RAM) in the microcomputer is limited to IK pin 1 at most, and data necessary for other processing must also be stored in the RAM, so it is impossible to store all of the subfood Q. I couldn't do it, so I had to use external RAM. Also, when using the subcode Q in the lead-in area to find out the playing time of a song, it is necessary to obtain the start time of the song and the start time of the next song, so the subcode Q Since the RAM in which the information is stored must be accessed twice, the program load on the microcomputer becomes heavy.

(d) Means for solving the problems The present invention was created in view of the above points,
The first one takes in the subcode Q converted from the EFM signal.
a shift register, a storage circuit connected to the first shift register via a data bus for storing data recorded in the first area of the subcode Q, and a second shift register of the subcode Q. an R/W control circuit that controls writing and reading of the memory circuit based on the data recorded in the area and a signal applied from the outside, and a write address for the data recorded in the third area of the subcode Q. an address control circuit for applying address data permitted to be applied from the outside to the storage circuit as a read address; an addition means for incrementing the address data applied from the outside; a first latch circuit that latches the read data, a second latch circuit that latches the data read using the incremented address data, and an output of the first shift register and the first latch circuit. and a second shift register to which the output of the selector is applied and which sends the input data to the outside with a clock applied from the outside. The present invention provides a CD reproducing integrated circuit which stores a subcode Q recorded in a lead-in area in advance in the storage circuit and simultaneously outputs two types of data based on an external address.

(Reference) Operation According to the above-mentioned means, the track number recorded in the second area of the sub-food Q taken into the first shift register is 'oo, (s bit BCD).
When the W control circuit detects the detection output, the storage circuit enters a writing state, and the address control circuit receives the track number data recorded in the third area of the sub-hood Q and applies it to the storage circuit. As a result, the data recorded in the first area of the subcode Q is stored in the area of the storage circuit whose address is the track number.

Therefore, when the optical pickup reads the lead-in area of the CD, all the data of the songs recorded on the CD are stored in the storage circuit. On the other hand, when a data request signal and address data are applied from the outside, the R/W control circuit puts the storage circuit in a read state and the address control circuit applies the applied address data to the storage circuit, so that the data is stored at that address. The data is read out and transferred and held in the first latch circuit. Furthermore, the address data applied from the outside is incremented by +1 by the adding means, and address data specifying the next address is created. Since this address data is applied from the address control circuit to the memory circuit number, the data stored at the next address is read from the memory circuit and transferred and held in the second latch circuit.

The two data held in the first latch circuit and the second latch circuit are applied to the second shift register via the selector, and serially output from the second shift register to the outside. Therefore, if you specify data for one song, you can simultaneously obtain data for the next song.

(f) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention. 22
The bit shift register (1) inputs the EFM signal read from the disk using an EFM synchronization pulse PLCK of 4,3218 MHz generated by a PLL circuit (not shown). The frame synchronization signal detection circuit (2) detects that the EFM signal input to the shift register (1) is a frame synchronization signal, that is, the front and rear 11 bits are each a continuous value, and is a frame synchronization signal. When detected, a detection output FSD is generated. The 14-bit latch circuit (3) is connected to the shift register (1
) are applied from the 9th bit to the 22nd bit,
It holds the 14 bits of one symbol following the frame synchronization signal, and the output of the 14-bit latch circuit (3) is applied to the EFM decoder (4) that converts the 14-bit EFM signal into an 8-bit symbol. 1.
The signal is applied to a subcode synchronization signal detection circuit (5) that detects whether the 4-bit symbol indicates a subcode synchronization signal. The subcode synchronization signal detection circuit (5) detects the synchronization signal 5. (0010000000 for a 14-bit pattern
0001) and synchronization signal 5. (00000000010010 in the 14-bit pattern) is detected, and the detection output S
Generate SD.

On the other hand, the 8-bit output of the EFM decoder (4) can be applied to the data bus (7) via the buffer (6), and the audio information symbols and parity symbols can be applied to the data bus (7) through the buffer (6).
7) in a RAM (not shown). Also,
The output of the EFM decoder (4) is sent to the subcode register (8).
), and when the output data is a subcode, it is held in this subcode register (8). Furthermore, the bit indicating the Qf-v channel of the subcode is applied to the data input of the first shift register (9>).

The first shift register (9) is composed of 80 bits, and sequentially shifts and stores the applied data in response to a shift clock 5UBCLK applied from the shift control circuit (10). The shift control circuit (10) has a detection output SS
Shift clock 5UBC based on D and detection output FSD
After subcode synchronization signals S6 and SI are detected, every time the detection output FSD is output, the frame synchronization signal is shift clock 5UBC
Generate 80 LKs. Therefore, the first shift register (9) receives the subcode synchronization signal S. , 8 following 51
The data of the subcode Q of the 0 frame period, that is, 4 bits of control data, 4 bits of address data, and 72 bits of information data are stored.

The latch circuit (11) is a sub-hood Q shown in FIG.
24 to temporarily hold areas G, H, and I, which are the first areas of
It is a bit latch and outputs the lower 24 bits of the first shift register (9), that is, areas G and H of subcode Q.
, I, and the latch circuit (1
The output of 1) is connected to the data bus (12). The storage circuit (RAM) (13) is a static memory with a capacity of 3 bits, and is addressed with 8-bit BCD data indicating the track number in order to store the subcode Q taken out from the lead-in area. , the addressed area consists of 25 bits (24 bits + 1 check bit). Therefore, all of the song information read from the lead-in area as shown in FIG. 3 can be stored using the track number as an address. The data input/output of this RAM (13) ~D0 is connected to the 25-bit data bus (12), and the address input A0
~A, are connected to the output of the address control circuit (14),
The write control input WE and the read control manual input OE are connected to the R/W control circuit (15).

The R/W control circuit (15) includes a latch circuit (16), a track number zero detection circuit (17), a data request reception circuit (18), a NAND gate (19), and an OR gate (
20), and the address control circuit (14) is composed of a latch circuit (21), an address switching circuit (22), and a read address input circuit (23).

The latch circuit (16) is connected to the 8-bit output of the first shift register (9) corresponding to area A (shown in Figure 2), which is the second area for storing the track number of subcode Q. , its output is applied to a track number zero detection circuit (17).

That is, the track number of subfood Q taken into the first shift register (9) is '00. (BCD), and if it is 00yo, it recognizes that the track currently being read is the lead-in area and
A write control signal TNO is output to AM (13>).The latch circuit (21) also outputs the first shift signal TNO corresponding to area B (FIG. 2), which is the third area in which the index of subcode Q is recorded. It is connected to the 8-bit output of register (9) and takes in data indicating the track number recorded in area B as the address of RAM (13).-
On the other hand, the data request receiving circuit (18) sends read timing signals WDI, W to the RAM (13) based on a data request signal REQ from an external device, for example, a microcomputer.
N controlled by the applied OR gate (20) of D33
A read control signal ME is applied via an AND gate (19) and an address switching circuit (22) is controlled.

Further, the read address input circuit (14) receives and holds the data indicating the track number sent from the microcomputer following the data request signal REQ, and uses the data as an address in the RAM (13) to receive and hold the data in the address switching circuit (22). ). Furthermore, the read address input circuit (23) has a built-in means for adding +1 to the input address data, and is specifically composed of a presettable register having an increment function, and is configured to input the first read timing signal WDI. and the next read timing signal WD33.
Increment is performed in D16. The output of this read address input circuit (23) is the address switching circuit (23).
2) is applied. The address switching circuit (22) switches the output of the latch circuit (21) to RA when the read control signal ME is not output from the data request reception circuit (18).
The data held in the read address input circuit (23) is applied to the address inputs A0 to A7 when the read control signal ME is fully output.

On the other hand, the data bus (12) has a first latch circuit (24) and a second latch circuit (24) each configured with 24 bits.
25> is connected, the latch operation of the first latch circuit (24) is controlled by the read timing signal WDI, and the second
The latch operation of the latch circuit (25) is controlled by a read timing signal WD2. The outputs of the first latch circuit (24) and the second latch circuit (25) are applied to the selector (26).

The selector (26) can be controlled by the read control signal ME from the data request reception circuit (18), and when the read control signal ME is not output, that is, when there is no external data request, the first shift register ( 9) is transferred to the second shift register (27).
), and when the read control signal ME is output due to an external data request, the first latch circuit (
24) in place of the bit output of the first shift register (9) that captures regions G, H, and I of subcode Q, and outputs the output of the second latch circuit (25) as
It outputs to the second shift register (27) in place of the bit output of the first shift register (9) which takes in areas C, D, and E of subcode Q. Second shift register (27
) consists of 80 bits, holds the data output from the selector (26), and serially outputs the held data from the data output terminal Dout in response to a shift clock SCK applied from an external microcomputer or the like.

In FIG. 1, subcode Q is stored in the first shift register (9) every 98 frames by the optical pickup reading the EFM signal in the CD glue-in area. Area A of subcode Q in this lead-in area
The track number recorded on is 100'', so
This is detected by the track number zero detection circuit (17), a write control signal TNO is output, and the RAM
(13) is in the writing state. At the same time, as shown in FIG. 3, the track number recorded in area B of subcode Q is applied as address data to the RAM (13) via the latch circuit (21) and address switching circuit (22). Therefore, the areas G, H, and I of subcode Q shown in FIG.
The time (seconds) (minutes) data and frame data of the song recorded in the song are stored. By repeating this storage operation, all the data shown in FIG. 3 are stored in the RAM <13) using the track number and indexes AO, Al, and A2 as addresses.

1-b, the microcomputer sends the data request signal REQ
When the track number is applied, the data request reception circuit (18) outputs the read control signal ME, so the RAM (13) enters the read state at the timing signal WD1, and the address is input from the read address input circuit (23). The RAM (13) is accessed by the track number applied from the microcomputer via the switching circuit (22), and data at that address is read out.

This read data is transferred to the first latch circuit (12) controlled by the timing signal WDI via the data bus (12).
24). Furthermore, when the timing signal WD16 is generated, +1 is added to the track number previously input from the microcomputer in the read address input circuit (23) to create data for the next track number. Then, due to the generation of the timing signal WD33, RAM (13) enters the read state again, and the data accessed by the data of the next track number is read out. This read data is held in a second latch circuit (25) controlled by a timing signal WD33 via a data bus (12). The two types of data held in the first latch circuit (24) and the second latch circuit (25) are applied to the second shift register (27) via the selector (26), and are applied to the second shift register (27). It is serially output from the register (27) to the outside.

Therefore, by giving one track number from the microcomputer, it is possible to retrieve not only the data corresponding to that track number but also the data corresponding to the next track number.

(g) Effects of the Invention As described above, according to the present invention, the data of the song recorded on the CD is stored in advance in the CD playback integrated circuit from the subcode Q recorded in the lead-in area. There is no need to use an external storage circuit, and there is an advantage that a microcomputer with a small storage capacity can also be used.

In addition, simply by specifying one track number, the microcomputer can retrieve the data for the next track number, so programs such as program selection, cueing, performance time display, and search can be shortened. This has the advantage of reducing the program load.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention.
The data allocation of the subcode Q is shown in the figure, and FIG. 3 is a diagram showing the data recorded in the subcode Q in the lead-in area. (1)...Shift register, (2)...Frame synchronization signal detection circuit, (3)...Latch circuit, (4)
... EFM decoder, (5> ... Subcode synchronization signal detection circuit, (6) ... Buffer, (7) ... Data bus, (8) ... Subcode register, (9)
...first shift register, (10)...shift control circuit, (11)...latch circuit, (12)...
・Data bus, (13)...RAM, (14
)...address control circuit, (15)...R/W control circuit, (16)...latch circuit, (17)...
...Track number zero detection circuit, (18)...
Data request reception circuit, (21)... latch circuit,
(22)...address switching circuit, (23)...
Read address input circuit, (24)...first latch circuit, (25)...second latch circuit, (26)
...Selector, (27)...Second shift register. Figure 2/'158 LsB Figure 3

Claims (1)

[Claims] (1) An EFM decoder that converts the EFM signal read from the disk into an 8-bit symbol, a first shift register that takes in the subcode output from the EFM decoder, and a first shift register that takes in the subcode output from the EFM decoder; A storage circuit connected to the first shift register via a data bus for storing recorded data, and a storage circuit based on the data recorded in the second area of the subcode and a signal applied from outside an R/W control circuit that controls writing and reading of the memory circuit; and an R/W control circuit that uses the data recorded in the third area of the subcode as a write address and uses externally applied address data as a read address. an address control circuit that increments the address data applied from the outside; a first latch circuit that latches the data read out using the address data applied from the outside; a second latch circuit that latches data read out using address data; a selector that switches and outputs the output of the first shift register and the outputs of the first latch circuit and the second latch circuit; It is equipped with a second shift register to which the output of the selector is applied and sends out the input data with a clock applied from the outside, and the subcode recorded in the lead-in area of the CD is stored in the storage circuit in advance. , a CD characterized by outputting two types of data at the same time using external addresses.
Integrated circuit for reproduction.