JPH01134757A - Integrated circuit for reproducing cd - Google Patents

Abstract

PURPOSE:To eliminate a necessity to use an external-added storage circuit by storing the data of tunes recorded onto a CD in the circuit beforehand. CONSTITUTION:By reading the lead-in area of the CD by means of a light pick-up, all the data of the tunes recorded onto the CD are stored into the storage circuit. On the other hand, when a data requesting signal is impressed from an external part, an R/W control circuit 15 makes the storage circuit into a reading condition, the data are read, and they are transferring-held in a first latch circuit 25. Further, for the address data, +1 is executed by an adding means, next designating address data are prepared, the data stored in the next address are read, and they are transferring-held in a second latch circuit 26. A third latch circuit 28 is composed of 8 bits, the 8 bits output of a first shift register 9 to fetch an area G of a subcode Q is connected to an input, and an output is impressed to a coincidence detecting circuit 29 along with the output of reading address input circuit 23. Thus, an external-added RAM may not be used.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Industrial Application Field The present invention relates to an integrated circuit for reproducing a CD (Funbakuto Disc), and in particular, to an integrated circuit for reproducing a subcode Q read from a disc.
This is related to the processing of

(b) In the conventional CD, an 8-bit subcode is attached to a total of 32 symbols, 24 information symbols (8 bits) and 8 parity symbols (8 bits), and these are
The signal is M(8-14) modulated and recorded on the disk as one frame of 588 channel bits together with a 24-bit frame synchronization signal. Subcode 1 Ma, P, Q,
R.

Channels S, T, U, V, and W are assigned, and channels P and Q are used for program functions such as finding the beginning of a song and playing it in a preset order. Each channel of these subcodes is composed of 98 frames, that is, 98 bits, and in particular, the format of the subcode Q is as follows:
S, 02 bit, 4-bit control data, 4-bit/7-bit address data, 72-bit data, 16-bit CRC (Cyclic Redundant)
ancy Code).

FIG. 2 shows the data format of the subcode Q. As shown in FIG. 2, the subcode Q includes, in addition to control data and address data, the track number, index, and time (seconds) of the song in the A-I area represented by an 8-bit BCD code. (minutes), frames in the song, cumulative time (seconds) (minutes), and cumulative number of frames are assigned. Normally, this subcode Q is used to display the number of the track being played, the playing time, etc., but it is recorded in the lead-in area provided on the inner circumference of the CD for the purpose of finding the beginning of the song and programming functions. The subcode Q is assigned the data of the song recorded on the CD and the data of the lead-out area provided on the outer periphery of the CD. That is, in the case of subcode Q in the lead-in area, area A is "00." and area B is "00." as shown in FIG.
The track number 7 of the recorded songs, areas G and H
is the start time of the song with that track number, area I
is assigned the number of frames from the start of the track to the beginning of the song. Furthermore, in area B'
A OJ, 'A1,,'A2. There is an index such as 'A2.In AOl, the track number of the first song is recorded in area G, and in area G of rAl', the track number of the last song is recorded. The start time of the lead-out area is recorded in areas G and H, and the number of frames until the start of the lead-out area is recorded in area I. Furthermore, in the case of a CD, the maximum number of songs that can be recorded is 99, that is, n=99, so the number of subcodes Q in the lead-in area is 102 at most. Such a circuit for taking out the sub-hood Q is usually built into a CD playback integrated circuit. The subcode output circuit of a conventional CD playback integrated circuit detects a frame synchronization signal from the EFM signal read from the disc, demodulates the EFM signal after the frame synchronization signal, and generates an 8-bit subcode. After the data of the subcode Q is completed by applying the data of the Q channel in the subcode to the shift register and accumulating the subcode Q for each frame, the data of the subcode Q is serially transmitted from the shift register to an external device, for example. It was output to a microcomputer. The microcomputer uses the serially transferred subcode Q to display the track number, time, etc., and also uses it as data for moving the optical pickup to the target value.

A technique similar to that described above is described in detail in Japanese Patent Laid-Open No. 60-83261.

(c) Problems to be solved by the invention When the above CD playback integrated circuit is used, the control microcomputer connected externally can display the number of songs,
In order to display the time or select a program, the subcode Q in the lead-in area must be retrieved and stored in the memory circuit in advance. However, as mentioned above, the subcode Q of the lead-in area is 102 at maximum, and the number of bits of the data is 8X3X102=2448.
It's a bit. On the other hand, the memory circuit (RAM) in a microcomputer is about IK bits at most, and
Since the RAM must also store data necessary for other processing, it is not possible to store all of the subcode Q, and an external RAM must be used. Also, when using the subcode Q in the lead-in area to know the playing time of a song, it is necessary to obtain the start time of the song and the start time of the next song, so the subcode Q is memorized. Since the RAM must be accessed twice, the program load on the microcomputer increases.

(d) Means for solving interlayer points The present invention was created in view of the above points,
The first one takes in the subcode Q converted from the EFM signal.
a shift register, a storage circuit connected to the first shift register via a data buzz for storing data recorded in the first area of the subcode Q, and a second area of the subcode Q. an R/W control circuit that controls writing and reading of the memory circuit based on the data recorded in the storage circuit and a signal applied from the outside; and a write address that is the data recorded in the third area of the sub-hood Q; an address control circuit that applies externally applied address data as a read address to the memory circuit; an addition means that increments the externally applied address data; and data read using the externally applied address data. a first latch circuit that latches the data read out using the incremented address data; a second latch circuit that latches the data read out using the incremented address data; a selector that switches between and outputs the output of the lug circuit; a second shift register that outputs data inputted with an externally applied clock when the output of the selector is no longer applied; and the first shift register. a third latch circuit that holds predetermined data in the first area when the data in the third area of the subcode taken in is specific data; and the address data applied from the outside and the third latch circuit. a coincidence detection circuit that detects that the data latched in the circuit match; and a coincidence detection circuit that outputs predetermined address data to the address control circuit in place of the incremented address data based on the detection output of the coincidence detection circuit. To provide an integrated circuit for reproducing a CD, which is equipped with an address switching circuit, stores a subcode Q recorded in a lead-in area of a CD in the storage circuit in advance, and outputs two types of data at the same time based on an external address. It is.

(e) Effect: According to the above-mentioned means, it is possible to detect that the track number recorded in the second area of the subcode Q taken into the first shift register is '0OJC8 bits BCD).
When the W control circuit detects, the detection output puts the storage circuit into a write state, and the address control circuit receives the track number data recorded in the third area of the subcode Q and applies it to the storage circuit. As a result, the data recorded in the first area of the subcode Q is stored in the area of the storage circuit whose address is the track number.

Therefore, when the optical pickup reads the lead-in area of the CD, all the data of the songs recorded on the CD are stored in the storage circuit. On the other hand, when a data request signal and address data are applied from the outside, the R/W control circuit puts the storage circuit in a read state and the address control circuit applies the applied address data to the storage circuit, so that the data is stored at that address. The data is read out and transferred and held in the first latch circuit. Furthermore, the address data applied from the outside is incremented by 1 by the adding means to create address data specifying the next address. Since this address data is applied from the address control circuit to the storage circuit, the data stored at the next address is read from the storage circuit and transferred and held in the second latch circuit.

The two data held in the first latch circuit and the second latch circuit are applied to the second shift register via the selector, and serially output from the second shift register to the outside. On the other hand, when the area B of the subcode Q taken into the first shift register is "A1.," the track number of the last song recorded in the area G of the subcode Q is transferred to the third latch circuit. Therefore, if the externally applied address indicates the last song, a detection output is output from the coincidence detection circuit, and the address switching circuit selects the track number 1A2. instead of the incremented data. Send it to RAM as an address.'The data stored at the address of A2J is
This data is the time and frame number of the lead-out area, and is held in the second latch circuit. Therefore, the data taken out from the second shift register becomes the data of the final song and lead-out area.

(F) Embodiment FIG. 1 is a block diagram showing an embodiment of the present invention.22
The bit shift register (1) inputs the EFM signal read from the disk using an EFM synchronization pulse PLCK of 4,3218 MHz generated by a PLL circuit (not shown). The frame synchronization signal detection circuit 2) detects that the EFM signal input to the shift register (1) is a frame synchronization signal, that is, the front and rear 11 bits are each a continuous value, and is a frame synchronization signal. When detected, a detection output FSD is generated. The 14-bit latch circuit 3) is a shift register (1
) are applied from the 9th bit to the 22nd bit,
It holds the 14 bits of one symbol following the frame synchronization signal, and the output of the 14-bit latch circuit (3) is applied to the EFM decoder (4) that converts the 14-bit EFM signal into an 8-bit symbol. 1.
The signal is applied to a subcode synchronization signal detection circuit (5) that detects whether the 4-bit symbol indicates a subcode synchronization signal. The subcode synchronization signal detection circuit 5) detects the synchronization signal 5. (0010000000 for a 14-bit pattern
0001) and synchronization signal 5. (00000000010010 in the 14-bit pattern) is detected, and the detection output S
Generate SD.

On the other hand, the 8-bit output of the EFM decoder <4) is applied to the data bus (7) via the buffer (6), and the audio information symbols and parity symbols are applied to the data bus (7) through the buffer (6).
7) in a RAM (not shown). Also,
The output of the EFM decoder (4) is sent to the subcode register (8).
), and when the output data is a subcode, it is held in this subcode register (8). Furthermore, the bit indicating the Q channel of the subcode is
Applied to the data input of the first shift register (9).

The first shift register (9) is composed of 80 bits, and sequentially shifts and stores the applied data in response to a shift clock 5UBCLK applied from the shift control circuit (10). The shift control circuit (10) has a detection output SS
Shift clock 5UBC based on D and detection output FSD
LK, and every time the detection output FSD is output after subcode synchronization signals S and Sl are detected, the frame synchronization signal is followed by synchronization with the completion of input of the 14-bit symbol of the EFM signal. and shift clock 5UBC
Generate 80 LKs. Therefore, the first shift register (9) receives subcode synchronization signals S, , S.

Data of the subcode Q for a total of 80 frame periods, that is, 4-bit control data, 4-bit address data, and 72-bit information data are stored.

The latch circuit (11) is a subcode Q shown in FIG.
24 to temporarily hold areas G, H, and I, which are the first areas of
It is a bit latch, and the lower 24 bits output of the first shift register (9), that is, the areas G and H of subcode Q.
, I, and the latch circuit (1
The output of 1) is connected to the data bus (12). The storage circuit (RAM) (13) is a static memory with a capacity of 3 bits, and is addressed with 8-bit BCD data indicating the track number in order to store the subcode Q taken out from the lead-in area. , the addressed area consists of 25 bits (24 bits + 1 check bit). Therefore, all of the song information read from the lead-in area as shown in FIG. 3 can be stored using the track number as an address. Data input/output 00-D of this RAM (13), 4 is 2
It is connected to a 5-bit data bus (12), address inputs A0 to A are connected to the output of the address control circuit (14), and write control input W1 and read control input σ1 are connected to the R/W control circuit (14). 15).

The R/W control circuit (15) includes a latch circuit (16), a track number zero detection circuit (17), a data request reception circuit (18), a NAND gate (19), and an OR gate (
20>, and the address control circuit (14) is composed of a latch circuit (21), an address switching circuit (22), and a read address input circuit (23).

The latch circuit (16) is connected to the 8-bit output of the first shift register 9) corresponding to area A (shown in Figure 2), which is the second area for storing the track number of subcode Q. , its output is applied to a track number zero detection circuit (17).

That is, it is detected whether the track number of the subcode Q taken into the first shift register (9>) is '00. (BCD), and if it is '00', the track currently being read is Recognize it as a lead-in area and press R.
A write control signal TNO is output to AM (13). Further, the latch circuit (21) is connected to the 8-bit output of the first shift register (9>) corresponding to area B (FIG. 2), which is the third area for recording the index of subcode Q, and is connected to the 8-bit output of the first shift register (9>). Take in the data indicating the track number recorded in B as the address of RAM (13).
The data request receiving circuit (18) receives a data request signal REQ from an external device, for example, a microcomputer.
Read timing signals WDI, WD3 to AM (13)
3 applied OR game 1-(20) NA that is out of control
A read control signal ME is applied via an ND gate (19), and the address switching circuit (22>) is controlled.The read address input circuit (23) also receives data sent from the microcomputer following the data request signal REQ. The receiver receives and holds the data indicating the coming track number, and applies it to the address switching circuit (24) as an address in the RAM (13).Furthermore, the read address input circuit (23) adds +1 to the input address data. It has built-in means for adding, specifically, it is composed of a presettable register with an increment function, and the timing signal WD is generated between the first read timing signal WDI and the next read timing signal WD33.
Increment is performed at 16. The output of this read address input circuit (23) is the address switching circuit (24).
) is applied to The address switching circuit (22) transfers the output of the latch circuit (21) to the RAM when the read control signal ME is not output from the data request reception circuit (18>).
The read address input circuit (2
3) Apply the data held in address A, ~A.

On the other hand, the data bus (12) has a first latch circuit (25) and a second latch circuit (25) each composed of 24 bits.
26> is connected, the latch operation of the first latch circuit (25) is controlled by the read timing signal WDI, and the second
The latch operation of the latch circuit (26) is controlled by a read timing signal WD2. The outputs of the first latch circuit (25) and the second latch circuit (26) are applied to the selector (27).

Further, the third latch circuit (28) is composed of 8 bits, and the 8-bit output of the first shift register (9) that takes in the area G of the subcode Q is connected to the input, and the output is the read address input. It is applied to the coincidence detection circuit (29) together with the output of the circuit (23). Third latch circuit (28
The latch operation of ) detects that the data latched in the latch circuit (21) is index "A1".
The track number n (Fig. 3) indicating the last song recorded in the area G in the subcode Q where 'Al' is recorded is controlled by the output of the 'A1' detection circuit (30), and the third latch circuit (30) 28). The coincidence detection circuit (29) is
A matching circuit (31) that detects whether the data of the read address input circuit (23) and the data of the third latch circuit (28) match, and a D-FF (3) that takes in the scattered output.
2), and the clock of D-FF (32) serves as a timing signal WD16 for incrementing the read address input circuit (23). Therefore, the match detection result between the data before incrementing in the read address input circuit (23), that is, the address data applied from the outside, and the data in the third latch circuit (28) is detected after the timing signal WD16 is generated. -FF (32)
The signal is outputted from the output Q of , and applied to the address switching circuit (24). The address switching circuit (24) switches and outputs the output of the read address input circuit (23) and data indicating address "A2", and is connected to the D-FF (32).
Outputs address "A2" when a -dissipated output from is applied.

The selector (27) is controlled by the read control signal ME from the data request receiving circuit (18), and when the read control signal ME is not output, that is, when there is no external data request, the selector (27) operates the first shift register ( 9) is transferred to the second shift register (33).
), and when the read control signal ME is output due to an external data request, the first latch circuit (
25) in place of the bit output of the first shift register (9) that captures the regions G, H, and I of the sub-hood Q, and outputs the output of the second latch circuit (26) as
It is output to the second shift register (33) in place of the bit output of the first shift register (9) which takes in areas C, D, and E of subcode Q. Second shift register (33
) consists of 80 bits, holds the data output from the selector (27), and serially outputs the held data from the data output terminal Dout in response to a shift clock SCK applied from an external microcomputer or the like.

In FIG. 1, subcode Q is stored in the first shift register (9) every 98 frames by the optical pickup reading the EFM signal in the CD glue-in area. Area A of subcode Q in this lead-in area
The track number recorded on is ``00no'', so
This is detected by the track number zero detection circuit (17), the write control signal TNO is output, and the RAM
(13) is in the writing state. At the same time, as shown in FIG. 3, the track number recorded in area B of the subcode Q is applied as address data to the RAM (13) via the latch circuit (21) and the address switching circuit (22). Therefore, the areas G, H, and I of subcode Q shown in FIG.
The time (seconds) (minutes) data and frame data of the song recorded in the song are stored. By repeating this storage operation, all the data shown in FIG. 3 are stored in the RAM (13) using the track number and indexes AO, AI, and A2 as addresses.

On the other hand, when the microcomputer applies the data request signal REQ and the track number, the data request receiving circuit (
18> outputs the read control signal ME, the RAM (13) enters the read state in the timing signal WDI, and is applied from the read address input circuit (23) via the address switching circuits (24) and (22). RA with the track number from the microcomputer
M (13) is accessed and data at that address is read. This read data is transferred to the data bus (
12) controlled by timing signal WDI via
is held in the latch circuit (25). Furthermore, when the timing signal WD16 is generated, the read address input circuit (
At step 23>, +1 is added to the track number previously input from the microcomputer to create data for the next track number. Then, due to the generation of the timing signal WD33, the RAM (13) enters the read state again, and the data accessed by the data of the next track number is read out. This read data is sent to the timing signal WD3 via the data bus (12).
The signal is held in the second latch circuit (26) controlled by 3. On the other hand, the track number applied from the outside to the read address input circuit (23) is applied to the third latch circuit (28).
), the timing signal WDI reads out the data of the final song from the RAM (13) using the track number of the final song as an address, and the first latch circuit (25) , and the timing signal WD33 is latched to D-F F (32
), the address "A2" is accessed instead of the incremented address, and the start time and frame number of the lead-out area stored at the address "A2." are stored in the RAM (13). The second latch circuit (26) is transferred to the first latch circuit (26).
The two types of data held in the second latch circuit (25) and the second latch circuit (26) are applied to the second shift register (33) via the selector (27).
33) is serially output to the outside.

Therefore, by giving one track number from the microcomputer, it is possible to retrieve not only the data corresponding to that track number but also the data corresponding to the next track number. Furthermore, when the track number of the final song is specified, the start time and frame number of the lead-out area can be extracted together with the data of the final song, so the performance time of the final song can be obtained by simple subtraction.

(g) Effects of the Invention As described above, according to the present invention, the data of the song recorded on the CD is stored in advance in the CD playback integrated circuit from the subcode Q recorded in the lead-in area. There is no need to use an external storage circuit, and there is an advantage that a microcomputer with a small storage capacity can also be used.

In addition, simply by specifying one track number, the microcomputer can retrieve the data for the next track number, so programs such as program selection, cueing, performance time display, and search can be shortened. This has the advantage of reducing the program load.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention.
The data allocation of the subcode Q is shown in the figure, and FIG. 3 is a diagram showing the data recorded in the subcode Q of the lead-in area. (1)...Shift register, (2)...Frame synchronization signal detection circuit, (3)...Latch circuit, (4)
... EFM decoder, (5) ... Subcode synchronization signal detection circuit, (6) ... Buffer, (7) ... Data bus, (8) ... Subcode register, (9)
...first shift register, (10)...shift control circuit, (11)...latch circuit, (12)...
・Data bus, (13)...RAM, (14)・
... Address control circuit, (15) ... R/W control circuit, (16) ... Latch circuit, (17) ...
Track number zero detection circuit, (18)...Data request reception circuit, (21)...Latch circuit, (
22)... Address switching circuit, (23)... Read address input circuit, (25)... First latch circuit, (26)... Second latch circuit, (27)...
・Selector, (28)...Third latch circuit, (
29)...Coincidence detection circuit, (30)..."A1"
Detection circuit, <24)...Address switching circuit, (3
3)...Second shift register.

Claims (1)

[Claims] (1) An EFM decoder that converts the EFM signal read from the disk into an 8-bit symbol, a first shift register that takes in the subcode output from the EFM decoder, and a first shift register that takes in the subcode output from the EFM decoder; A storage circuit connected to the first shift register via a data bus for storing recorded data, and a storage circuit based on the data recorded in the second area of the subcode and a signal applied from outside an R/W control circuit that controls writing and reading of the memory circuit; and an R/W control circuit that uses the data recorded in the third area of the subcode as a write address and uses externally applied address data as a read address. an address control circuit that increments the address data applied from the outside; a first latch circuit that latches the data read out using the address data applied from the outside; a second latch circuit that latches data read out using address data; a selector that switches and outputs the output of the first shift register and the outputs of the first latch circuit and the second latch circuit; A second shift register to which the output of the selector is applied and sends out the input data with an externally applied clock, and a third region of the subcode taken into the first shift register is specified. a third latch circuit that holds predetermined data in the first area when the data is data; and a coincidence detection that detects that the address data applied from the outside matches the data latched in the third latch circuit. and an address switching circuit that outputs predetermined address data to the address control circuit in place of the incremented address data based on the detection output of the coincidence detection circuit.