JPH01134280A - Gate array - Google Patents

Abstract

PURPOSE:To enable fault detection without an increase in integration degree nor an increase in the number of test terminals by providing a storing means which stores the output of a RAM and is so constituted as to perform scan path operation is addition to a general transistor (TR) element group. CONSTITUTION:The gate array consists of an internal area and four input/output buffer parts 3 provided on a base 1. The internal area 2 includes the general TR element group 4 and the RAM part 6, and a dedicated TR area 5 which constitutes a scan path FF circuit is provided nearby the RAM 6. Consequently, the gate array which easily detects a fault is obtained without the increase in the integration degree and the increase in the number of test terminals.

Description

TECHNICAL FIELD The present invention relates to gate arrays, and more particularly to gate arrays including RAM.

Prior Art In this type of conventional gate array, an additional circuit was provided to physically or logically separate the RAM section from the other random logic section when performing a failure test. Then, the RAM section was tested using a memory tester, and the random logic section was tested with the RAM section disconnected or with the RAM section logically set to data through to detect failures.

However, since the additional circuit for separating the RAM section and the random logic section must be constructed from a cell array (general-purpose transistor) of the random logic section, there is a drawback that the degree of integration is actually reduced. Ta.

In addition, since there is a physical limit to the number of terminals used in the gate array, there is also a disadvantage in that the increase in the number of test terminals puts pressure on the functional specifications.

An object of the present invention is to provide a gate array having a structure that allows easy detection of failures without reducing the degree of integration or increasing the number of test terminals.

Structure of the Invention The gate array of the present invention includes a group of general-purpose transistor elements and a RAM, and the gate array includes a group of general-purpose transistor elements and a RAM.
The present invention is characterized in that a storage means configured to store the output of and perform a scan canvas operation is provided outside the general-purpose transistor element group.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a schematic diagram showing the configuration of an embodiment of a gate array according to the present invention. In the figure, a gate array according to an embodiment of the present invention includes an internal region 2 provided on a base 1;
It is composed of four human output buffer sections 3.

The internal area 2 includes a RAM section 6 and a cell row 4 in which cells, which are basic units of various function blocks, are arranged in an orderly manner. Further, in the internal region til12, a dedicated transistor region 5 constituting a scanvase type flip 70 tube circuit is provided near the RAM section 6.

The dedicated transistor region 5 has a higher degree of integration than the cell row 4 made up of general-purpose transistor elements, and can be provided in a small space. Furthermore, in terms of the manufacturing process, it is possible to create it by the same process as the cell row 4 and the RAM section 6, and it has almost no effect on the chip size of the master slice.

In addition, the dedicated transistor area 5 is provided with a scan scan type flip 7 having a number of bits equivalent to one word in the RAM section 6.
The data is read from the RAM section 6 one word at a time and stored, and then by performing a shift operation, the data is read out one bit at a time from one output terminal (not shown) via the input/output cover sofa section 3. It is designed to output data.

For example, if one word is made up of 32 bits, a 7-scanvase lip flop is configured to be able to store 32 bits. And first of all, 32
If bits are stored and then 32 clock pulses are input, one word of data will be outputted from one output terminal (not shown) through the human output buffer section 3 by a shift operation. By inputting all words of data output from the RAM section 6 to a memory tester or the like, the RAM section 6 can be easily tested for failure.

In other words, by slightly increasing the space in the dedicated transistor region 5, it is possible to effectively utilize a part of the cell array that was conventionally used as an additional circuit.

Note that in this embodiment, the dedicated transistor region 5 is
Although they are arranged in an orderly manner near the AM section 6, they do not need to be arranged in an orderly manner and may be provided in any available space.

In addition, in this embodiment, the dedicated transistor region 5 has 1
Although a scanvase type seven flip-flop for one word is constructed, it is clear that a scancanse type flip-flop for multiple words may be constructed. However, in this case, it is not advisable in terms of the degree of integration, and in the end, it is best to have a structure for one word.

Furthermore, in this embodiment, a failure test of a single gate array was explained, but even if a failure occurs after it is incorporated into a device, the state of the RAM can be observed, so failure detection is possible. It can be done easily.

DETAILED DESCRIPTION OF THE INVENTION As described above, the present invention comprises a scanvase type flip-flop using dedicated transistors.
This has the effect that failures can be easily detected without reducing the degree of integration or increasing the number of test terminals.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing the configuration of a gate array according to an embodiment of the present invention. Explanation of symbols of main parts 4...Cell row 5...Dedicated transistor area 6...RAM section

Claims (1)

[Claims] A gate array including a group of general-purpose transistor elements and a RAM, wherein storage means configured to store the output of the RAM and perform a scan canvas operation is provided in addition to the group of general-purpose transistor elements. A gate array characterized by: