JPH0113259B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a packet communication transmission system that converts input data into packets and transmits the packets to the receiving side via a half-duplex communication transmission line, and particularly relates to a packet communication transmission system that converts input data into packets and transmits the packets to the receiving side through a transmission path of half-duplex communication. This invention relates to a packet division transmission method that minimizes the transmission delay due to packetization.

(b) Prior art and problems In the conventional data packet communication transmission system, two buffer memories 4 and 4' are prepared for packetization, and one buffer memory 4 is used as shown in FIG.
While a packet is being sent from buffer memory 4' (or 4'), the other buffer memory 4' (or 4) is storing data to be sent next. In this system, the data stored in the buffer memory 4 is not terminated as a packet until it is completed, and therefore, the data packets in the buffer memory 4 cannot begin to be sent to the transmission path 18 until the buffer memory 4 completes data storage. Therefore, a time lag occurs between the time of data input and the time of data transmission (therefore, data arrival at the destination). In order to reduce this time lag, there is no choice but to shorten the packet length, but this method has the disadvantage that even consecutively transmitted packets, which would be better if they were longer, are shortened, which deteriorates the transmission efficiency as a whole.

(c) Purpose of the Invention The purpose of the present invention is to shorten the time difference between the time of data input and the time of transmission of packetized data, and to shorten the transmission path of half-duplex communication without shortening the normal packet length. The object of the present invention is to provide a substantially high-speed and efficient packet transmission method that increases usage efficiency.

(d) Structure of the invention In the present invention, there is no received data on the transmission path;
The circuit is configured to separate the data that is being stored in the buffer memory and send it out as independent packets by detecting that a part of the input data to be transmitted is already stored in the buffer memory.

(e) Embodiments of the invention Examples of the invention will be described with reference to the drawings. FIG. 1 is a block diagram for explaining the configuration and operation of an embodiment according to the present invention, and FIG. 2 is a conventional example corresponding thereto. In the figure, 1 is input data to be transmitted, 4 and 4' are buffer memories, 2 is a buffer memory input changeover switch, 6 is a buffer memory output changeover switch, 5, 5', and 7 are buffer changeover gates, and 8 is a buffer changeover switch. T-type flip-flop that holds state, 9 is a transmitter, 10
is a receiver, 11 is a transmit/receive switch, 12,1
3 is a transmission request gate, 14 is a transmission enable determination gate, 15 is received data, 16, 16' is an input data end signal, 17, 17' is a buffer full signal,
18, 18' are buffer data detection signals, 19
2 is a transmission connection completion signal, and 20 is a transmission path.

The difference between FIG. 1 of the embodiment of the present invention and FIG. 2 of the conventional example is that the transmitter/receiver switch 11 is
The transmission connection completion signal 19 informing that the transmission line 20 has been connected to the transmission path 20 is guided to the gate 7, and there is no gate 12 requesting transmission.

Input data 1 is guided to buffer memory 4 (or 4') depending on the state of changeover switch 2, and is accumulated in units of a fixed number of bits of data, and is stored as a packet. When the buffer memory 4 (or 4') is full and the data ends and the packet is completed, the gate is activated by the end signal 16 (or 16') or the full signal 17 (or 17') from the data end detection section 3 (or 3'). 5. Changeover switch 2 and changeover switch 6 are inverted via gate 7 and flip-flop 8. Input data 1 is guided to buffer memory 4' (or 4) by changeover switch 2, and writing of the next packet begins. The output of the buffer memory 4 is directed to the transmitter 9 by the changeover switch 6 as a completed packet. The above is the same for both FIG. 1 of the system according to the present invention and FIG. 2 of the conventional system. However, the present invention adds the following functions.

Even if data writing in the buffer memory 4 is incomplete and not completed as a packet, a signal 18 (or 18') for detecting the presence of data within itself is sent to the gate 13 and further inputted to the gate 14. At the gate 14, the transmission line 20 is connected to the transmission/reception switch 1.
After confirming that there is no received data 15 to the receiver 10 via the transmitter 1, the transmitter/receiver switch 11 is requested to switch to the transmitter side. The transmission/reception changeover switch 11 sends a transmission connection completion signal 19 to the gate 7, which informs that the transmitter 9 is connected to the transmission line 20. The output of gate 7 inverts T-type flip-flop 8, inverting the states of both input selector switch 2 and output selector switch 6. The input changeover switch 2 separates the data in the middle of accumulation in the buffer 4 (or 4') by switching the input data from the buffer 4 (or 4') to 4' (or 4), and separates the data in the middle of storage into an independent one.
Packet. Further, the output changeover switch 6 connects the output of a newly generated packet that is separated in the middle of the buffer 4 (or 4') to the transmitter 9, and inputs the packet to the transmitter. In this way, data packets that are being stored in the buffer 4 (or 4') are automatically separated by the transmission connection completion signal 19, and sent as new packets to the transmitter 9, and sent out to the transmission line 20 through the transmission/reception changeover switch 11.

The above is the configuration and operation of the present invention, but as a matter of course, in the embodiment of the present invention, even after the transmitter 9 has finished transmitting the first packet after being connected to the transmission path 20, it continues to transmit the next packet. Since it can be sent in sections, wasted free time can be eliminated.

(f) Effects of the Invention As detailed in the embodiments above, according to the present invention, if there is no received data on the transmission path and even a portion of the input data to be transmitted is in the buffer memory, the accumulated data is immediately transmitted. This is very effective because it can minimize the time difference between the time of data input and the start of data transmission.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a system according to the present invention, and FIG. 2 is a block diagram of a conventional system. In the figure, 1 is input data, 2 is an input switch for buffer memory, 3 and 3' are data end detection sections, 4 and 4' are buffer memories, 6 is an output switch for buffer memory, 5 and 7 are gates,
8 is a T-type flip-flop, 9 is a transmitter, 10 is a receiver, 11 is a transmit/receive switch, 12, 13
is a transmission request gate, 14 is a transmission possible determination gate,
15 is received data, 19 is a transmission connection completion signal, 2
0 is the transmission path.

Claims (1)

[Claims] 1. Temporarily store the input data in buffer memory,
In a packet communication system that converts data into packets and sends them to a transmission line for half-duplex communication, there is a first detection unit that detects the absence of received data from the transmission line, and a buffer memory in which a portion of the input data to be transmitted has already been accumulated. a second detection unit that detects that the
A data packet division transmission method characterized in that data packets that are being stored in a buffer memory are divided into sections based on the outputs of the first and second detection sections and transmission is started as one packet.