JPH01131950A - Interconnecting network and its cross bar switch - Google Patents

Abstract

PURPOSE:To prevent the contention for another relay path from being generated at the time of relaying and to completely eliminate the risk of dead lock b using a cross bar switch as a relay means annexed to an element processor. CONSTITUTION:An arbitrary element processor P(i,j,k) arranged logically at each lattice point corresponding to the inner point of a rectangular parallelopiped of (LXMXK) on a three-dimensional grid space is connected to three cross bar switches 9-1-9-3. Each cross bar switch is provided with a function to communicate with the element processor having a number in which the coordinate value of one specific dimension of a three-dimensional coordinate constituting a processor number is substituted by another coordinate value. Therefore, it is possible to communicate with the element processor having any number by relaying three coordinate transform cross bar switches, and the dead lock can be prevented from being generated completely by using a relay cross bar switch.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a method for mutually coupling element processors of a parallel computer, and in particular, since a high coupling capacity is required and the number of processors is large, it is difficult to couple all of them with a full crossbar switch. This invention relates to a switch configuration suitable for cases where this is not possible.

[Conventional technology]

Conventional devices include the general method of coupling each element processor to one or several buses, as well as the
68, a method for connecting adjacent element processors arranged in a grid, JP-A-59-10
All element processors (full) as described in 9966
Method of coupling with a crossbar switch, JP-A-62-235
Typical examples include a system in which all element processors are connected using multi-stage switches as described in Reference 1, and a system in which hypercube coupling is performed as described in Reference 1.

Literature 1 Nigi L. Sign “The Cosmic Cube”, Communications of the ACM, 2
Volume 8, No. 1, pp. 22-33, 1985 (C, L, 5a
itz “The Co5m1c Cube”.

com+nunicationN of theA
CM, vol1, 28. no, 1, pp,
22-33.1985) [Problems to be Solved by the Invention] Among the above-mentioned conventional technologies, the bus coupling method has the advantage of requiring a small amount of hardware. There is a problem that performance decreases due to competition between processors, and the number of processors is limited to a dozen or so.6 Lattice joins (also known as mesh joins) also require a small amount of hardware, but are capable of combining a large number of element processors. However, since it can only communicate with neighboring processors, its communication performance depends largely on the nature of the problem being handled. Solving Partial Differential Equations Suitable for Neighborhood Calculations 9 Image processing is good, but communication overhead becomes significant in finite element method, fast Fourier transform (FFT), logic/circuit simulation, etc.

A full crossbar switch connection is one in which all element processors are completely connected by a matrix switch. Therefore, in terms of performance, it is the best of all combinations, but
Since the amount of hardware is proportional to the square of the number of element processors, the limit for coupling is generally about several dozen processors.

Multi-stage switches have been considered as a coupling method suitable for massively parallel computers including a large number of element processors because the amount of hardware can be suppressed to approximately L logz L, where L is the number of element processors, and complete coupling is possible. However, the length of the communication path (number of relay stages) is approximately 1 ogz L, resulting in a large transfer delay, and when many element processors attempt to access the same shared conversion, multiple access buses compete for the communication path in between. Problems have been pointed out, such as the occurrence of a total paralysis of the network called hotspot contention (paralysis affects all accesses), and even if hotspot contention does not occur, access contention is large and performance is poor. ing.

A hypercube connection is known as a connection that allows relatively efficient communication, but the communication partner must be specified in the program, making programming complicated. In order to avoid this, if an automatic relay mechanism is provided for each element processor, the amount of hardware will increase. Additionally, there is a problem in that the wiring connections intersect, making implementation troublesome.

It is known that in parallel processing of large-scale numerical calculations, specific inter-processor communication buttons often appear. Typical examples include lattice coupling, ring coupling, and butterfly coupling.

Therefore, if these specific patterns of communication can be processed at high speed, the effectiveness of the network can be said to be great. Among the above conventional techniques, lattice coupling.

It includes ring coupling and butterfly coupling as its own coupling topology, and only full crossbar switches and hypercube couplings can communicate using these patterns without requiring relay operations. Bus coupling.

Neither lattice coupling nor multistage switches can process all of these specific patterns of communication at high speed.As a special example, Reference 2 describes a two-configuration hypercube based on the coupling of two processors. Spanning B, which expands the combination to a configuration based on the combination of multiple processors
US) lypercuba has been introduced, but since multiple processors are connected via a bus, only two processors can communicate at a time, and it cannot be considered to include the above-mentioned connection topology.

Reference 2: Dharma P. Agrawal et al. "Evaluating the Performance of Multicomputer Configurations".

I.E.E.Computer, May.

1986.28-29, 1986 (Dharma P, Agrawal e1, a1
,' Evaluating thePerforma
nce of Multicon+puter Con
figurationN”.

May 1986. (pp, 28-29, 1986) Among the above problems, the problem of constraints on the number of connected devices in bus connection cannot be solved when the number of element processors is large. Furthermore, the performance varies greatly depending on the nature of the problem being handled in lattice coupling, and the problem of hot spot contention in multi-stage switches are both fundamental and essential problems that have not been solved at present. moreover.

Along with the Spanning Bus Hypercube, there is a problem of performance degradation in major application problems due to the fact that these couplings do not include all of the lattice coupling, ring coupling, and butterfly coupling.

The remaining two networks that do not have such fundamental difficulties:
Among (full) crossbar switches and hypercube connections, the former requires too much hardware and cannot connect multiple element processors, while the latter can connect multiple processors, but programming and implementation are difficult, and the number of connected processors is too large. As , increases, performance also decreases. Furthermore, in hypercube coupling, when communicating between two element processors that are not directly coupled, it is necessary to relay the communication to another element processor. The communication method in which an information packet is once taken into one element processor and then transferred to another element processor is called the store-and-forward method, but the store-and-forward method is not limited to hypercube coupling. , multiple element processors P1゜Pa, Pa... form a communication path in a loop and try to perform a relay operation on it, Pl becomes ready to receive after P2 completes its sending operation. P2 cannot finish the sending operation until P3 finishes the sending operation and becomes ready to receive.
There is a problem that a deadlock situation may occur where the two systems become stuck together and cannot move.

Performance is evaluated by the number of basic changeover switches (crosspoints) that a unit of transmitted information passes through before reaching its final destination, and the amount of hardware is evaluated by the total number of crosspoints that make up the network.

Usually, there is a trade-off relationship between hardware amount and performance, and the total number of crosspoints cannot be increased, but the number of crosspoints through which one unit of transmission information passes decreases.

The present invention is an interconnected network that does not have any theoretical difficulties in the above sense, and when the upper limit of the amount of hardware (technical and economical) and the number of element processors are arbitrarily given, these processors can be To provide a system configuration that provides a high coupling capacity (fewer switching stages) close to that of a full crossbar switch (few switching stages), and provides an optimal coupling in terms of communication performance and hardware amount, especially with the minimum or optimal amount of switch hardware. The purpose is to provide technology for variably configuring networks6.
In other words, in the conventional technology, when the number of processors is small, a full crossbar switch is used, and when the number of processors exceeds a certain level, the network has to be configured using hypercube coupling. However, according to the present invention, an intermediate between these recombination methods is used. If it has an automatic relay function that eliminates the risk of deadlock, it is possible to construct many types of connection networks that require less switch hardware than hypercube connections. In addition, since the unit switches can be mounted on a chip, module, board, casing, between casings, etc., it is suitable for performance balance and maintenance.

[Means for solving problems]

The above purpose is basically L = n I X n2
In a parallel computer in which the number of element processors is L, which can be factorized as ! 4 (i1, iz+..., IN)To
≦i1≦nz1, O≦12≦nz-1, -0≦iN≦
nN-1 is given as the processor number of each element processor, and for any k, a group of element processors having processor numbers that differ only in the coordinates of the th dimension, that is, processor numbers (11+12y..., or..., 1s) (11,1
2? ..., 1, ..., i*) (11112y "'
A group of n element processors with HnK 1 r ''t iN) is interconnected by one nK input nK output crossbar switch, and the connection is expressed as the coordinate ( Ill 12?”'r n
K-1r nK+1+ ”'t IN) all (
L/ng set), and further all K (1≦
≦N), the total LX
Element processors are connected by (1/nz+1/nz+-+1/nN) crossbar switches, and furthermore, in this connection, the relay means attached to the transmitting processor has its own processor number (i-work, izt...txh). Select (i≠jx) as one of the dimensions that do not match with the destination processor number F1+J2y..., jN), and select N crossbar switches (hereinafter referred to as Select a crossbar switch (referred to as a coordinate conversion crossbar switch) that connects a group of element processors with processor numbers that differ only in dimensional coordinates (referred to as a dimensional coordinate conversion crossbar switch), and assign the destination processor number to this crossbar switch. Inputting the communication information packet configured as a pair with the transmission data, each coordinate conversion crossbar switch decodes the coordinate part of the first dimension of the destination processor number, and converts the coordinates of the first dimension into the first dimension of the destination processor number. It is transmitted and relayed to a processor with a processor number equal to the coordinates, i.e., the destination processor itself or a processor on the route to the destination processor; in the latter case,
This problem can be solved by repeating this process until there are no unmatched coordinates, thereby transmitting an information packet to the destination processor. Furthermore, by using a crossbar switch as a relay means attached to an element processor, there is no conflict with other relay paths during relaying, so the risk of deadlock can be completely eliminated.

[Effect]

It will be described that communication can be performed between arbitrary element processors using the mutual coupling method of the present invention. Processor number (ixgx
z+...txN) to the processor number F tt x 2. ..., iN) 6 If the first coordinates iz of the source processor and the first coordinates jz of the destination processor are not equal, then the element processors with all other coordinates equal are Since it is connected to one crossbar switch (first-order coordinate conversion crossbar switch), this crossbar switch allows the processor number F1y ig,...tx
The information can be sent to an element processor with N) or a relay crossbar switch attached to the element processor.

Next, the element processor that has just received the information, or the relay crossbar switch attached to the element processor,
Since the coordinates other than the next coordinate are all connected by the same element processor and one coordinate conversion crossbar switch,
If 12≠j2, this switch will change the processor number C.
jsv jzt ia, . . . iN) or a relay crossbar switch attached to the element processor. By selecting such a route and transmitting it one after another to the element processor whose corresponding coordinates have been replaced by the crossbar switch, or to the relay crossbar switch attached to the element processor, the processor number F1+ is finally obtained.]2. ...W jS).

Furthermore, in many cases, by appropriately factorizing L, the number of connected element processors in each dimension can be limited to a certain range. This allows coordinate transformation of each dimension to convert the crossbar switch within a defined mounting unit, for example, within a chip or within a module.

It is possible to store it inside a board, inside a stand, between boxes, etc. This property cannot be fully satisfied under the condition that all factors take the same value: L=mN, and the decomposition of the present invention: L=nIXn2X...XnN becomes a necessary condition.

If a relay crossbar switch is not used, element processor P1 attempts to relay the packet to element processor P2, and at the same time element processor P2 also tries to relay the packet to element processor P1.
A deadlock will occur if you try to relay a packet to However, if a relay crossbar switch is used, the flow of packets from Pl to Pl can be set independently of the flow of packets from Pl to Pl, so no putlock occurs.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First Embodiment (1) Structure of Mutual Coupling Network FIG. 1 is an explanatory diagram exemplifying a three-dimensional coupling method according to the first embodiment of the present invention, but the same applies when expanded to N dimensions. As shown in Figure 2.

An arbitrary (with processor number (1*, 1*k)) element processor P (1t
As k) is connected to three crossbar switches 9-1, 9-2, and 9-3, as shown in FIG. Here, the crossbar switch 9-1 has a processor p (i, J
, k) and the element processor P that differs only in the coordinates of the first dimension.
(Ow j+ k)+ P(1+ j+ k)+...
..., P(L-1, jtk) are completely connected.

Similarly, the crossbar switch 9-2 is an element processor P(i, O, k) that differs only in the coordinates of the second dimension.

P (1+ 1+ k)+..., P (i, M
-1,k), and the crossbar switch 9-3 is an element processor P(1+j+0) that differs only in the coordinates of the third dimension.
t P (le jv 1) t..., P (1
+ , -1) is perfectly combined with )+.

Each crossbar switch has a function of communicating with an element processor having a number in which the coordinate value of one specific dimension of the three-dimensional coordinates constituting the processor number is replaced with another coordinate value. Therefore, this crossbar switch is hereinafter referred to as a coordinate conversion crossbar switch. A switch that performs coordinate transformation to a specific dimension is called a dimensional coordinate transformation crossbar switch. As will be shown later, any number of element processors can be communicated with by relaying the three coordinate transformation crossbar switches.

(2) Structure of element processor FIG. 3 shows the structure of an element processor.

The element processor p (i, j+k) is composed of a relay device 1 and a processing device 2 which is a normal computer having a program counter and sequentially executing instructions. The relay device 1 has a built-in microprogram, decodes the communication packet transmission destination processor number input from the processing device 2 or the input port register 5, and based on the result, specifies the coordinate conversion crossbar switches 9-1 to 9-3, Alternatively, a communication control device 3 having a function of selecting the processing device 2 and sending communication packets thereto, and an input port register 5 and an output port register 6 that temporarily store communication packets.
, a selector 7 that selects one of the input communication paths from the three coordinate conversion crossbar switches, and a distributor that selects one of the N coordinate conversion crossbar switches as the destination of the communication packet in the output port. It consists of 8. Here, the communication packet consists of a destination processor number and transmission data.

(3) Communication method Next, in the three-dimensional example shown in FIG.
) - origin processor to processor P (0, O,
O) - The mechanism for transmitting to the destination processor will be explained using Figures 1 and 3.4. First, the origin processor P(i.

The processing bag W2 of j, k) inputs a communication packet to the communication control device 3 and instructs its transmission. The destination information (processor number) of the communication packet is 3 coordinates (0, O, O)
The coordinate values are compared in order from the first coordinate with the three coordinate values (i, jt k) that constitute the own processor number in the microprogram of the communication control device 3, and the first one is determined to be a mismatch. Regarding the first coordinate i that has become, an element processor p (0,
j+k), the corresponding first coordinate conversion crossbar switch 9-1 is selected. The communication packet is placed in the output port register 6, and the number "1" of the selected crossbar switch 9-1 is input to the distributor via the signal line 12. The distributor 8 uses this number 111 IF to connect the data line 13 and the control signal line 12 to one input channel 101, 102 of the first coordinate conversion crossbar switch 9-1. The communication control device 3 uses the control signal lines 12 and 101 and the data lines 13 and 102 to send out communication packets in the output ports to the first coordinate conversion crossbar switch 9-1. The structure and operation of the coordinate conversion crossbar switch will be described later.

The element processor P (0°j, k) to which this communication packet is sent via the crossbar switch 9-1 selects a plurality of processors whose selector 7-2 outputs a transmission request signal 0REQ (described later). When the crossbar switch 9-1 is selected from among the crossbar switches, the output channel lines 103 and 104 of the crossbar switch are connected to the control signal line 10-2 and the data line 11-2 (the logic of selection is not claimed in the present invention). It is connected, and a communication packet is taken into the communication control device 3-2 via the input port register 5-2. At this time, the selector 7-2 also transmits the number 111 #l of the receiving crossbar switch 9-1 selected by the selection logic through the control signal line 10-2. Element processor P (0* j
+k) communication control bag [in 3-2, the corresponding switch number Jl
In the second example, the coordinates converted from I I + are known, and the destination processor's coordinate values (umbrella, 0°0) are calculated sequentially from the coordinates after that (first coordinate) - the umbrella is the converted coordinates. - indicates that the coordinate value of the own processor (0, j,
k), and for the first second-dimensional coordinate j that does not match, the second-dimensional coordinate transformation is performed in order to send this coordinate value to the element processor P (0, O, k) whose coordinate value is replaced with 0. Crossbar switch 9-4 is selected and communication packets are sent to input channel lines 201 and 202. The processor P (0, O, k) which receives the packet from the output channel lines 203 and 204 performs the same relay operation and sends the packet to the input channel lines 301 and 302 of the third-dimensional coordinate transformation crossbar switch 9-5. and the output channel line 30 to the destination processor P (0, O, O)
Communication packets can be delivered via 3,304. The destination processor P (0, O, O) selects the destination (processor number) (0, O, O) of the packet stored in the input port 5-4 via the selector 7-4 from the communication control device 3- 4 is decoded and matches the own processor number (0, 0, 0) in the microprogram, so the processing device 2-4 is notified of the arrival of the packet.

Similarly, in the general N-dimensional case, by relaying the mismatched coordinates one after another to the element processor whose coordinates have been replaced with the coordinates of the destination processor using the coordinate transformation crossbar switch, the destination processor is finally reached. Can send information to the processor. Since the conversion of mismatched coordinates is completed in at most N times, the maximum communication path length of this combination method is N.

In the three-dimensional example of FIG. 1, the maximum communication path length is three. However, lattice bonds and ring bonds.

Regarding butterfly coupling, communication packets can be transferred to the destination processor in one transmission without any relay operation, resulting in communication performance equivalent to that of a full crossbar switch. Fourth
The figure shows the relay operation logic of the communication control device 3 described above.

(4) Structure and operation of coordinate conversion crossbar switch FIG. 5 shows an external interface of the crossbar switch 9 with one L input/output. - a set of input channels consists of two control signal lines IREQ and IACK and a data line IDATA;
It consists of IREQ is for transmitting a signal to notify the crossbar switch that the communication element processor has stored the data it wants to transmit in the output port register 6 and is waiting for transmission. This is to carry a signal to notify the element processor that it is OK to write the data into the output port register 6. Transmission data is loaded on IDATA. Similarly, the − set of output channels has two control signals g
It consists of OREQ, 0AcK, and output data line 0DATA. 0REQ is for the crossbar switch to load a signal requesting transmission data transfer to the input port register 5 of the receiving side element processor, and OA
C is for carrying a signal that the element processor on the receiving side has completed. Transmission data is placed in 0DATA. In the above interface, the control signal line IR
EQ and IACK are connected to the communication control device 3 of the element processor via the distributor 8 as shown in FIG. 3, and also to the control signal line 0REQ.

0AGK is connected to the communication control device 3 of the element processor via the selector 7. In addition, the data line IDATA
is connected to the output port register 6 of the element processor via the distributor 8, and the data line 0DATA is connected to the input port register 5 of the element processor via the selector 7.

The crossbar switch also includes a mask register write control signal line W and a mask button signal line MASK for setting the contents of a mask register (mask button) for masking a processor number, which will be described later.

An example of the structure of a crossbar switch is shown in FIG. In this example, a 3-input, 6-output crossbar switch is taken up, but the same applies to a general L-input and L-output case.

The communication control device 3 of the element processor that attempts to transmit, for example, processor p (21jt k) when i=2 in FIG. Send the number “1” to select and connect a specific crossbar switch 9-1,
Control signal of input channel 2 via signal line 12, [1
01, that is, outputs a transmission request signal to IREQ2. The crossbar switch is a processor P (01j, k),
P (1°j, k)r P (2w j−k) are connected by crowd channels 0, 1, and 2, respectively. Line I
When the request signal on REQZ is input to the decoder 20-3 of the crossbar switch, the part corresponding to the first dimension coordinates of the destination processor number in the transmission information packet on the output portro is decoded to find the destination. , destination channel, e.g. destination processor P (0,O,O)
For the channel corresponding to (output channel O), 1 is output, and for the other channels, O is output to the signal line 26-3 and transmitted to all priority control circuits 21-1 to 21-3. Only a part of the bit string of the processor number to be decoded needs to be input to the decoder 20-3. Therefore, a processor number consists of three fields representing coordinates in a three-dimensional grid space, and a coordinate conversion crossbar switch for each dimension requires a mechanism for extracting one field corresponding to the relevant dimension from among these fields. The range of coordinate values in each dimension is generally not equal, and accordingly, the position and length of the coordinate field in each dimension vary. In this embodiment, in order to variably select this field, mask registers 24-1 to 24-3 are provided in each decoder, and a mechanism is adopted in which a part of the processor number is masked and only the remaining bit string is decoded. There is.

FIG. 11 describes the function and structure of the mask register. Although the figure assumes a 16x16 crossbar switch, the same applies to crossbar switches of other sizes. The mask register 24 works as a kind of matrix switch, and the ID
A bit string do indicating the destination processor number in the ATA.

dz,...d211, the partial bit string didJdhd indicating the coordinates of a specific dimension is selected and sent to the decoder (ROM
) Input to 2o (address) Output as AtAzAaA4. For that, data line dsd as shown in the figure
Just write O in the field corresponding to the intersection of adhdm and the output line A IA x A s A &, and write 1 in the other fields, the output line A I A z A s A!
The above signal is decoded by the decoder 20 as a 4-bit binary number representing the priority control circuit number, and is converted into a transmission request signal ro'rts to the priority control circuits 0-15.

If the content of d+dJdkdt is 'o o o o', priority control circuit O should be selected ('1000...
It is decoded into a signal of 0'. This switch is 16X
When used as a crossbar switch smaller than 16, for example a 4x4 crossbar switch, mask register 2 is used.
4 selects only 2 bits and uses them as the input address A s A 2 to the decoder ROM 20. A a A
4 becomes 0. Therefore, in this case, only a portion of the decoder ROM is used. Mask register 24-1~
The contents of 24-3 can be set by instructing the mask register write control circuit 25 from the outside (element processor, host computer, etc.) (using the W and MASK signal lines).

Transmission requests are transmitted from each input channel to the priority control circuit 21-1, and one of them is selected according to predetermined logic, as will be described later. Thereafter, the priority control circuit 21-1 confirms that the buffer 23-1 in the selective transfer control circuit 22-1 is empty, and the signal line 27
-1, the selected input channel number (channel 2) is transmitted to the selection transfer control circuit 22-1. As a result, the transmission information packet on the output port of the processor P (2, jt k) is transferred (via the distributor 8 and the data line 102 (i.e., IDATAz) of the input channel 2) into the selective transfer control circuit 22-1. The data is transferred to the buffer 23-1. During this time, the priority control circuit 21-1 is in a busy state, and when the transfer is completed, it begins the next selection operation.

When data is transferred to the buffer 23-1, the selective transfer control circuit 22-1 outputs an output optical processor (processor P).
Signal line ○RE that requests transmission to (0, j, k))
Qo, that is, output on the control signal line 103. Processor p(o.

Transmission request signals from a plurality of coordinate conversion crossbar switches are input to the selector 7-2 of j+k), and one of them is selected according to predetermined logic and transmitted to the communication control device 3-2. 3-2 is the data line 0DA when the input port register 5-2 is empty.
TAo.

That is, data, 11!The data on 104 is selected by selector 7
-2, write to input port register 5-2,
When writing is completed, a write completion signal is output onto control signal line 0ACKo.

When the selective transfer control circuit 22-1 receives a write completion signal from the line OA CK o, it negates the transmission request signal on the line ORE Qo, and the communication control device 3-2 of the processor P (Ot jt k) detects this. Line OA CK o
Negate the reception completion signal above. Selective transfer control circuit 2
The buffer 23-1 of 2-1 becomes ready for transfer again,
The selector 7-2 of the processor P (0=jtk) also becomes able to select another crossbar switch.

On the other hand, when the priority control circuit 21-1 comes out of the busy state, the decoder 20-3 detects this through the signal line 26-3 and sends an IA signal to the processor P (21, L k).
Sends a transfer completion signal on CKz. The communication control device 3 of the processor p (21, Lk) which has received the transfer completion signal on IACKz negates the transfer request signal on IREQz, and is now able to place the primary transmission data on the output port.

An example of the logic of the priority control circuits 21-1 to 21-3 is shown in FIG. In this example, we focus on the fact that the input from the three decoders is 3-bit information, that is, O to 7.
A system is adopted in which a pattern of permission signals corresponding to each input is stored in a memory (RAM) 15 having eight entries. However, the logic of the priority control circuit is not limited to this.

Second embodiment FIGS. 8 and 9 are explanatory diagrams of the coupling method of the second embodiment.

The difference from the first embodiment is that instead of the communication control device 3 in the element processor performing the relay operation, a relay crossbar switch 14 installed in each element processor performs this operation.

(1) Structure and operation of a relay crossbar switch The structure of a relay crossbar switch is basically the same as that of a coordinate conversion crossbar switch, but the destination processor number input to the decoder is not one coordinate field but three coordinate fields. is the entire coordinate field. A detailed explanatory diagram of the destination decoding section of the relay crossbar switch will be explained using FIG. The destination processor number input from the data line IDATA and the contents of the own processor number register 50, which stores the own processor number prepared in the relay crossbar switch, are input to the comparator 51 and EXORed bitwise. If they match, 1 is returned, and if they do not match, 0 is sent to the signal line 52-
1 to 52-32. This output is input to the mask register 24, and if O is written in the intersection field of the mask register 24, that is, if it is not masked, this input is input to the output line A I A Z A a
It is output as is on the top, and wired AND is performed here. As a result, 1 is output to the output line only when all comparator outputs connected to the output line without being masked are 1. Each output line AI A! If the first to third coordinates of the processor number are assigned to As.

If a certain coordinate field is all equal to the corresponding field of the own processor number, 1 is output to the output line, otherwise (in case of mismatched coordinates) O is output.The signal on the 6 output line is inverted. and is input to the decoder 20.

For example, in FIG. 1, assume that the first coordinate is represented by bits 0°1 and 2 of the destination processor number input from the data line IDATA. It is input to the comparator 51 along with bits 0, 1, and 2 of the corresponding own processor number register 50, and if all the bits match, the signal lines 52-1, 52-2, 52-
1 is output to 3. An intersection field 53-1 between the first coordinate track and the first output line Ar of the mask register;
53-2.53-3 has O, other output line A z A
Since 1 is written in the intersection field with s,
The comparison result is sent only to the first output 1iA A1. Therefore, only when all 1s are output to the signal lines 52-1, 52-2, and 52-3, 1 is output to the first output line A1 of the mask register.

The decoder converts the signal on the output line A s A z A s into 2
The channel number is converted into a channel number, and 1 is sent to the priority control circuit of the channel, and 0 is sent to the others. For example, if the signals on the output line A
For o o', select channel O1, that is, the channel to the own processor.

(2) Communication method In FIG. 8, when a communication packet is input from one coordinate conversion crossbar switch 9 to the relay crossbar switch 14, its destination is decoded, and if it is addressed to this processor, the switch is sent to the element processor. Connect to input port 5 and input packets. If the destination is any other destination, select the coordinate conversion crossbar switch 9 that converts the mismatched coordinates and connect to it. Relay crossbar switch 1
4 external interface is coordinate conversion crossbar switch 9
is the same as

In FIG. 9, from element processor P (i, j, k) to element processor P (01jt k), P (0°0,
An example of transferring the packet to the element processor P (0, O, O) via the relay crossbar switch of k) is shown by a broken line.

In the second embodiment, the communication control device 3 decodes the destination information (communication destination processor number) of the communication packet as described in the first embodiment, and performs a specific coordinate conversion crossbar switch based on the result.

Alternatively, it does not have the functions of selecting the processing device 2 and sending communication packets, but merely has the function of interfacing with the relay crossbar switch 14.

Evaluation In the example shown in Figure 9, there are three coordinate conversion crossbar switches (9-
1, 9, -4, 9-5) and four relay crossbar switches (14-1, 14-2, 14-3゜14-4), so a total of 7 switching operations are required. be. In the first embodiment, the number of crosspoint passages, that is, the unit switching operation of transferring a communication packet from one input/output port/buffer to the next buffer/input/output port, is counted as three times, but the control of the element processor Considering the determination and selection processing in the device 3, the time required for transfer will be the same after all. In the first embodiment (method in which the processor itself relays), a maximum of N transmission operations are required, so the maximum communication path length of this switch is N, and in terms of the number of cross points in terms of hardware, it is ntXnzX・
...XnNX (nt+nz+ -+ n N).

Further, nK'': k=1, the maximum value of -N is the maximum coupling capacity of the crossbar switch.

Furthermore, in the second embodiment (system having a relay crossbar switch corresponding to a processor), if performing a relay operation by the relay crossbar switch 14 itself is regarded as one transmission operation, a maximum of 2N+1 transmission operations are required. That is, the maximum communication path length of this switch is 2N+1. Also, the amount of hardware is n1×n2×-XnN×{(N+1)”+nl
+nz+-+nN).

Next, it will be shown that by using the mutual coupling method of the present invention, it is possible to easily find a configuration that can achieve the highest performance and a configuration that requires the least amount of hardware, given the maximum coupling capacity of one crossbar switch. show.

Performance is determined by the communication path length N or 2N+1, assuming that the number of signal lines for coupling between each processor of the crossbar switch is constant. That is, higher performance can be obtained by reducing the dimension of the space in which processors are logically arranged as small as possible. For example, in the case of the processor relay method shown in the first embodiment, when the number of processors is divided and the maximum number of processors that can be connected to one crossbar switch is n, then q=[
logL/logn] + 1 is the minimum communication path length when using the crossbar switch. Here, [] is a symbol that takes the integer part of the quotient. In this case, the element processors are arranged in a hypercube-like area of a q or q+1-dimensional lattice space, and the number of processors that can be combined with all the element processors constituting a one-dimensional partial area within the hypercube is the maximum value n above. They are connected using a certain crossbar switch.

On the other hand, the amount of hardware is nlXn2X...X-nNX
(n engineering+n2+...+nN), so clearly n
The case of 1=2 is the minimum amount of hardware. However, in the method using the relay crossbar switch shown in the second embodiment, the amount of hardware is minimized when a different configuration is adopted, as shown in FIG. For example, in a 256-device configuration, 8
The amount of hardness is minimized when it is placed in a dimension. Also, from the standpoint that performance is better even if there is a certain amount of hardware, in a configuration with 64 to 1024 element processors, a two-dimensional configuration of 8 x 8 to 32 x 32
For the 768-unit configuration, a three-dimensional configuration of 4x8x8 to 32x32x32 would be appropriate.

[Effects of the Invention] According to the present invention, a switch is configured that connects a large number of element processors that cannot be connected with a single crossbar switch (full crossbar switch) with a coupling capacity close to that of a full crossbar switch, regardless of the number of processors. can do. Second, the coupling ability close to that of a full crossbar switch means that it has high communication performance (fewer cross-point passages) and includes inter-processor coupling topology (lattice, ring, butterfly), which is important for applications. This means that communication can be performed with the minimum number of crosspoints for a certain inter-processor communication pattern. Within the scope of the prior art, a hypercube is known as a network that includes the above-mentioned coupling topology and can couple a large number of processors, but the coupling method of the present invention supports communication in communication patterns other than the above-mentioned specific coupling topology. Performance is much better than Hypercube.

In particular, by using a relay cross-spy switch, deadlock can be completely prevented.

In addition, the present invention also improves the scale of the coordinate conversion crossbar switch (the number of input/output channels of the crossbar switch).
Optimum (maximum communication performance, minimum amount of hardware,
A method of configuring a coupling method (or an intermediate between the two) is provided, making it possible to fill the gap between a full crossbar switch and a hypercube.

Furthermore, it is possible to store coordinate conversion switches of each dimension for each mounting unit such as a chip, module, board, or housing.
It is possible to define the connection relationship of element processors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a hypercuboid arrangement of processors, FIG. 3 is a schematic diagram of an element processor, and FIG. 4 shows a relay operation of a communication control device 3. Figure 5 is an explanatory diagram of the crossbar switch interface.
FIG. 6 is a configuration diagram of a crossbar switch, FIG. 7 is an explanatory diagram showing an example of a priority control circuit, FIG. 8 is a configuration diagram of the second embodiment, and FIG. 9 is an explanatory diagram of the operation of the second embodiment. FIG. 10 is an explanatory diagram showing the amount of hardware when a relay crossbar switch is included, FIG. 11 is an explanatory diagram of a mask register, and FIG. 12 is an explanatory diagram of a decoding section of a relay crossbar switch. 1... Relay device, 2-2-4... Processing device, 3-3
-4...Communication control device, 5-5-4...Input port register, 6-6-4...Output port register, 7-
7-4...Selector, 8-8-4...Distributor, 9-
1 to 9-5...Coordinate conversion crossbar switch, 20.2
0-1 to 20-3... Processor number decoder, 21
-1 to 21-3...Priority control circuit, 22-1 to 2
2-3...Selection transfer control circuit, 24.24-4 to 24
-3...Mask register, 14-1 to 14-4...
Relay crossbar switch, 15...Memory (RAM) 5
0... Own processor number register, 51... Comparator-n-jaw 1 Figure r (v Shin θ) Kz Figure 5 (jIV Kawatan Ja conversion 2 Channel Neru Maefu 9 Nagi P (θ, θ, ρ) ■ /θ Kanfu 11 Figure Z4 Square 7L Nos. 7

Claims (1)

[Claims] 1. In a parallel computer composed of L=n_1×n_2×...×n_N element processors or external devices (hereinafter referred to as element processors), N-dimensional grid coordinates (i_1, i_2 , ..., i_N), 0≦i_1≦
n_1-1, 0≦i_2≦n_2-1, ..., 0≦i
_N≦n_N-1 is given as the processor number of each element processor, and the dimension field in the processor number, which has a unique position and length determined corresponding to the number of grid points of a specific dimension, is decoded to perform switching regarding the dimension. A crossbar switch that performs an operation is prepared, and for any k, a group of element processors having processor numbers that differ only in the coordinates of the k-th dimension, that is, processor numbers (i_1, i_2, ..., ■, ..., i_N)(i
_1, i_2,..., 1,..., i_N)...
... (i_1, i_2, ..., n_K-1, ..., i_
A group of n_K element processors with N) is combined into one n_K
The input n_K outputs are mutually coupled by the above crossbar switch, and the coupling is performed using the coordinates (i_1, i_2, ..., n_K_-1, n_K+1) of the N-1 dimensional subspace excluding the k-th dimension.
, ..., i_N) (L/n_K group), and then for all K (1≦k≦N), total L
+...+1/n_N) crossbar switch interconnection network 2 of element processors according to claim 1, in which a destination processor number of a final destination is attached to transmitted data as an address. It sequentially takes in the information packets given by
, n_N) and the number of the destination element processor (j_1, j
_2, ..., j_N), one of the dimensions that does not match is (i
_K≠j_K), and among the N crossbar switches connected to the element processor, combine the element processor group that has a processor number that differs only in the processor number of the element processor and the coordinates of the k-th dimension, and Select a processor whose k-dimensional coordinate is equal to the k-th dimension coordinate of the destination processor number, that is, a crossbar switch that can send to the destination processor itself or a processor on the path to the destination processor. and inputs the information packet to the crossbar switch, and inputs the information packet to the processing device of its own processor if there are no mismatched coordinates, the information packet relay means provided for each element processor. Interconnected network. 3. In the interconnection network according to claim 1, an input/output port register of the processor and N crossbar switches connected to the processor are connected to the interconnection network, thereby relaying information packets to a destination.
A mutual coupling network characterized by having a relay crossbar switch with N+1 inputs and N+1 outputs provided for each element processor. 4. In claim 3, when the amount of hardware is evaluated by the number of basic changeover switches (cross points) through which information packets pass, the minimum amount of hardware for a given number L of processors. Take, that is, L×{(N+1)^2+n_1+n_2+...+n
The dimension N and the factor n_ of each dimension are set such that _N} is minimized.
1, n_2, . . . n_N is defined as an interconnection network. 5. In a crossbar switch that has the function of inputting an information packet with a destination address expressed in multidimensional coordinates and performing switching and forwarding regarding a specific dimension of the destination address, the unique position and A cross-buy switch characterized by having means for variably selecting and decoding a field in a processor number having a length according to an external instruction.