JP2585318B2 - Interconnecting network and cross bus switch therefor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an interconnecting method of element processors of a parallel computer, and particularly requires a high connecting capability, but has a large number of processors and is fully connected in a full cross bus switch. The present invention relates to a switch structure suitable for a case where the switch cannot be used.

[Conventional technology]

Conventional devices include, in addition to a general method of coupling each element processor to one or several buses, a device adjacent to element processors arranged in a grid as described in JP-A-58-181168. A method of connecting all elements to each other, as described in JP-A-59-109966, a method of connecting all element processors by a (full) cross bus switch, and a method of connecting all element processors to a multi-stage switch as described in JP-A-62-2353. , Method 1
As described above, those taking hypercube bonds are typical.

Literature 1: C. L. Sites, The Kosmitsu Kyubu, Communications of the ACM, Vol. 28, No. 1, pp. 22-23, 1985 (CLSeitz “The C
osmic Cube ", communications of the ACM, vol.28, no.1,
pp.22-33,1985) [Problems to be Solved by the Invention] Among the above-mentioned prior arts, the bus connection method has an advantage that the amount of hardware is small, but if the number of connected element processors is large, However, there is a problem that performance is degraded due to bus contention, and the number is limited to a dozen.

Lattice connection (also called mesh connection) requires a small amount of hardware, and can connect a large number of element processors. However, since it can communicate only with adjacent processors, its communication performance greatly depends on the nature of the problem to be handled. Solving PDEs and image processing for neighborhood calculation are good,
In the finite element method, the fast Fourier transform (FET), the logic / circuit simulation, etc., the communication overhead becomes remarkable.

The full cross bus switch completely connects all the component processors by a matrix switch.
For this reason, the performance is the highest among all combinations. However, since the amount of hardware is proportional to the square of the number of element processors, the coupling limit is generally about several tens.

The multistage switch has a hardware amount reduced to about Llog ₂ L when the number of element processors is L, and can be completely connected. Therefore, the connection method has been adopted for a massively parallel computer including a large number of element processors. However, when the length of the communication path (the number of relay stages) is about log ₂ L and the transfer delay is large, and when many element processors try to access the same shared conversion, multiple access paths rob the middle communication path. The problem is that the entire network of the network called "hot spot contention" (the paralysis affects all accesses) is multiplied, and even if the hotspot contention is not reached, access competition is large and performance does not appear. It is pointed out.

The hypercube connection (hypercube) is known as a connection that enables relatively efficient communication, but requires a communication partner to be specified on a program, which complicates programming. If an automatic relay mechanism is provided for each element processor to avoid this, the amount of hardware increases. In addition, there is a problem that mounting is troublesome because the connections intersect.

In parallel processing of large-scale numerical calculations, it is known that a specific communication pattern between processors often appears. Typical examples include lattice coupling, ring coupling, and butterfly coupling. Therefore, if the communication of these specific patterns can be processed at high speed, the effectiveness of the network can be said to be great. Of the above prior art,
Lattice connection, ring connection, and butterfly connection are included as their own connection topologies, and only full-cross bus switches and hypercube connections can communicate with these patterns without the need for relay operations. All of the bus connection, the lattice connection, and the multistage switch cannot process all of the communication of these specific patterns at high speed. Also, as a special example, reference 2 describes a basic method based on the coupling of two processors.
The Spanning Bus Hypercube, which is an extension of the hypercube coupling of the configuration to a configuration based on the coupling of multiple processors, is introduced, but since multiple processors are bus-coupled, only two processors can communicate at a time. Therefore, it cannot be considered that the above connection topology is included.

Literature 2: Dharma P. Agrawal et al., "Evarieating the Performance of Multicomputer Configuration", IEEComputer, May, 1986, 28-29, 1986 (Dharma
P.Agrawal et.al. "Evaluating the Performance of Mu
lticomputer Configurations ", May 1986, pp.28-29,198
6) Among the above-mentioned problems, the problem of the restriction on the number of connected buses cannot be solved when the number of element processors is large. Further, the point that the performance greatly changes depending on the nature of the problem to be dealt with in the lattice coupling, and the problem of the hot spot contention of the multistage switch are all fundamental and essential problems, and have not been solved at present. Further, along with the Spanning Bus Hypercube, there is a problem of performance degradation in a main application problem due to the fact that these couplings do not include all of lattice coupling, ring coupling, and butterfly coupling.

As described above, there are two remaining networks that have no fundamental difficulty: (full) cross bus switch and hypercube connection. The former has too much hardware and cannot connect a large number of element processors, and the latter has a large number. They can be combined, but programming and implementation are difficult, and the performance decreases as the number of combined units increases. In the hypercube connection, when communication is performed between two element processors that are not directly connected, it is necessary to relay the data to another element processor. As described above, the communication method in which an information packet is once taken into one element processor and then transferred to another element processor is called the store-and-forward method, but the store-and-forward method is not limited to hypercube coupling. When a plurality of element processors P ₁ , P ₂ , P ₃ … form a communication path in a loop and attempt to perform a relay operation thereon, P ₁ receives the signal after the transmission operation is completed by P ₂ can not terminate the transmission operation until it can be, P ₂ is falling into a deadlock state in which the P ₃ can not be the end of the transmission operation until it can be received by the end of the transmission operation, ... get stuck if connexion bite to each other and so on There is a problem that there is.

The performance is the number of basic switching switches (cross points) that a unit of transmission information passes before reaching the final destination, and the hardware amount is evaluated by the total number of cross points constituting the network. The amount of hardware and the performance are in a trade-off relationship. If the total number of cross points is increased, the number of cross points through which one unit of transmission information passes decreases. The present invention is an interconnection network without any fundamental difficulties in the above sense, and when an upper limit (technical / economic) of the hardware amount and the number of element processors are arbitrarily given, To combine processors with high coupling capacity (small number of switching stages) close to a full cross bus switch, and to provide a system configuration that provides optimal coupling in terms of communication performance and hardware amount, and in particular, to minimize the minimum or optimal switch hardware amount. The purpose of the present invention is to provide a technique for variably configuring a network having the same. In other words, in the range of the prior art, a network is formed by a full-cross bus switch while the number of processors is small, and a network is formed by a hypercube connection when the number of processors is more than a certain number. In the case of an automatic relay function having an intermediate performance and no danger of deadlock, it is possible to construct a number of types of connection networks in which the amount of switch hardware is smaller than that of the hypercube connection. In addition, the implementation is as follows:
Since the switches can be collectively mounted in the module, on the board, in the housing, between the housings, and the like, it is suitable for performance balance and maintenance.

[Means for solving the problem]

Basically, in a parallel computer in which L can be factorized into L = n ₁ × n ₂ ×... × n _N , and the number of element processors is L, each of these factors is defined as the number of grid points on one side. The coordinates of the interior points of the hypercube on the N-dimensional interstitial space (i ₁ , i ₂ ,
..., i _N ), 0 ≤ i ₁ ≤ n ₁ -1, 0 ≤ i ₂ ≤ n ₂ -1, ... 0 ≤ i _N ≤ n _N -1
Is given as a processor number of each element processor, and for a given k, a group of element processors having a processor number different only in the k-dimensional coordinate, that is, a processor number N _K number of elements processor groups bonded to each other by cross-bus Lee Tutsi of one n _K input n _K outputs, the coupling coordinates of N-1 dimensional subspace except for the k-th dimension (i _1, i ₂ with, …, N _K−1 , n _{K + 1} ,…, i _N ) (L / n _K pairs), and all K
(1 ≦ k ≦ N), the element processors are connected by a total of L × (1 / n ₁ + 1 / n ₂ +... + 1 / n _N ) cross bus switches. , The relay means associated with the transmitting-side processor includes its own processor number (i ₁ , i ₂ ,..., I _N ) and the destination processor number (j ₁ ,
j ₂ ,..., j _N ), and selects one of the dimensions k (i _K ≠ j _K ) that is inconsistent with N 2 cross bus switches (hereinafter referred to as coordinate transformation) attached to the relay means of the transmitting processor. Cross bus switch), and selects a cross bus switch (k-th coordinate conversion cross bus switch) that connects the element processor groups having different processor numbers only in the k-th coordinate, and sends the destination processor number to this. And a communication information packet configured as a pair, each coordinate conversion cross bus switch decodes the k-th coordinate part of the destination processor number, and the k-th coordinate becomes the k-th coordinate of the destination processor number. A processor having an equal processor number, that is, the destination processor itself or a processor on a route to the destination processor for transmission and relay, and the latter processor This mismatch coordinates can be solved by using a method for transmitting information packet to the destination processor by the repeated until no. Further, by using a cross bus switch as a relay means associated with the element processor, it is possible to completely eliminate the risk of deadlock since there is no competition with other relay paths at the time of relay.

[Action]

It is described that communication can be performed between arbitrary element processors by the mutual connection method of the present invention. Processor number (i ₁ , i ₂ ,
, I _N ) to the processor number (j
₁ , i ₂ ,..., I _N ). If the first coordinate i ₁ of the source processor and the destination processor first coordinate j ₁ are not equal, other coordinates all elements equal processor is connected to one of the crossbar Lee Tutsi (primary coordinate transformation crossbar b Tutsi) Therefore, the information can be transmitted to the element processor having the processor number (j ₁ , i ₂ ,..., I _N ) or the relay cross bus switch associated with the element processor by using the cross bus switch. Next, the element processor that has just received the information,
Alternatively, the relay cross bus switch attached to the element processor is connected to the element processor having the same coordinates other than the secondary coordinates by one coordinate conversion cross bus switch. Therefore, if i ₂ 2j ₂ , the processor number is determined by this switch. Information can be transmitted to an element processor having (j ₁ , j ₂ , i ₃ ,... I _N ) or a relay cross bus switch associated with the element processor. By selecting such a path and sequentially transmitting it to an element processor whose corresponding coordinates are replaced by a cross bus switch or a relay cross bus switch attached to the element processor, finally, the processor numbers (j ₁ , j ₂ , .., J _N ) can be sent to the element processor.

In many cases, the number of connected component processors in each dimension can be limited to a certain range by appropriately performing the factorization of L. As a result, it is possible to store the coordinate transformation cross bus switch of each dimension in a predetermined mounting unit, for example, in a chip, in a module, in a board, in a housing, between housings, and the like. This property is all the factors condition that takes the same value: can not be satisfied sufficiently under the L = m ^N, decomposition of the present invention: a _{L = n 1 × n 2 ×} ... xn N prerequisite .

When not using the relay crossbar Lee Tutsi, the element processor P ₁ is attempting to relay packet to the element processor P _2, deadlock occurs simultaneously element processor P ₂ also tries to relay packet to the element processor P _1. However, the use of relay crossbar Lee Tutsi, it is possible to set the flow of packet from P ₁ to P ₂ independently of the flow of the packet from P ₂ to P _1, Detsutorotsuku does not occur.

〔Example〕

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First Embodiment (1) Configuration of Interconnection Network FIG. 1 is an explanatory view showing a three-dimensional example of a coupling system according to a first embodiment of the present invention. . As shown in FIG. 2, L × M on a three-dimensional lattice space
An arbitrary element processor P (i, j, k) (having a processor number (i, j, k)) logically arranged at each grid point corresponding to the interior point of the × K rectangular parallelepiped is shown in FIG. As shown in (1), they are connected to three cross bus switches 9-1, 9-2, 9-3. Here, the cross bus switch 9-1 is connected to the processor P (i, j,
k) and an element processor P that differs only in the first dimension coordinates
(0, j, k), P (1, j, k),..., P (L−1, j, k) are completely connected. Similarly, the cross-bass switch 9-2 has a second dimension. Element processor P (i, 0, k) which differs only in coordinates,
P (i, 1, k),..., P (i, M−1, k), and the cross bus switch 9-3 is an element processor P (i, j, 0) that differs only in the coordinates of the third dimension. , P (i, j, 1),..., P (i, j, k-1).

Each cross bus switch has a function of communicating with an element processor having a number obtained by replacing one specific dimension coordinate value of three-dimensional coordinates constituting a processor number with another coordinate value. Therefore, this cross bus switch is hereinafter referred to as a coordinate transformation cross bus switch. The switch for performing the coordinate conversion of a specific dimension k is called a K-dimensional coordinate conversion cross bus switch. As will be described later, it is possible to communicate with any number of element processors by relaying the three coordinate transformation cross bus switches.

(2) Structure of Element Processor FIG. 3 shows the structure of the element processor. The element processor P (i, j, k) comprises a relay device 1 and a processing device 2 which is a normal computer having a program counter and sequentially executing instructions. The relay device 1 has a built-in microprogram, decodes a communication packet transmission destination processor number input from the processing device 2 or the input port register 5, and, based on the result, specific coordinate conversion cross-bus switches 9-1 to 9-3; Alternatively, a communication control device 3 having a function of selecting a processing device 2 and sending a communication packet thereto, an input port register 5 and an output port register 6 for temporarily storing a communication packet, and three coordinate conversion crossbars. It comprises a selector 7 for selecting one of the input communication paths from the switch, and a distributor 8 for selecting one of the three coordinate conversion cross-bus switches as a destination of the communication packet in the output port. Here, the communication packet is composed of a destination processor number and transmission data.

(3) Communication method Next, in the three-dimensional example of FIG. 1, the processor P (i, j, k)
The mechanism of transmission from the originating processor to the processor P (0,0,0) will be described with reference to FIGS. First, the departure point processor P (i, j,
The processing device 2 of k) inputs the communication packet to the communication control device 3 and instructs the transmission thereof. The destination information (processor number) of the communication packet is composed of three coordinates (0,0,0), and the coordinate values are sequentially arranged from the first coordinate to the own processor number in the microprogram of the communication control device 3. Is compared with the three coordinate values (i, j, k) to be processed, and an element processor P (0, j, k) having a difference obtained by replacing the coordinate values with 0 with respect to the first coordinate i that first becomes inconsistent. ), The corresponding first coordinate transformation cross-bus switch 9-1 is selected. The communication packet is placed in the output port register 6, and the number “1” of the selected cross bus switch 9-1 is input to the distributor via the signal line 12. The distributor 8 uses the number "1" to connect the data line 13 and the control signal line 12 to one of the input channels 101 and 102 of the first coordinate conversion cross bus switch 9-1.
Connect to The communication control device 3 includes control signal lines 12 and 101
The communication packet in the output port 6 is sent to the first coordinate conversion cross bus switch 9-1 using the data lines 13 and 102. The structure and operation of the coordinate transformation cross bus switch will be described later.

The element processor P (0, j, k) to which the communication packet has been sent via the cross bus switch 9-1 has a plurality of selectors 7-2 whose transmission request signals OREQ (described later) are output. When the cross bus switch 9-1 is selected from the cross bus switches, the output channel lines 103 and 103 of the cross bus switch (the present invention does not claim the logic of selection) are selected.
104 is connected to the control signal line 10-2 and the data line 11-2,
The communication packet is taken into the communication control device 3-2 via the input port register 5-2. At this time, the selector 7-2
Is the reception cross bus switch 9-1 selected by the selection logic.
The number "1" is also transmitted by the control signal line 10-2. In the communication control device 3-2 of the element processor P (0, j, k), the coordinates converted from the switch number “1” —the first coordinates in this example—
And the coordinate values (*, 0, 0) of the destination processor in the order from the coordinates after the first coordinate (*, 0, 0)-* indicate that the coordinates are converted coordinates-and the coordinate values (0, j) of the own processor. , k), and the second-dimensional coordinate j to be transmitted to the element processor P (0,0, k) having the coordinate obtained by replacing the coordinate value with 0 with respect to the first non-coincident second-dimensional coordinate j. Select the conversion cross bus switch 9-4 and input channel lines 201 and 20.
2. Send a communication packet to 2. Output channel wire 203,204
Similarly, the processor P (0,0, k) to which a packet has been input performs a relaying operation, sends a packet to the input channel lines 301 and 302 of the three-dimensional coordinate conversion cross bus switch 9-5, and outputs the packet to the destination processor P (0 , 0,0), a communication packet can be delivered via output channel lines 303,304. In the destination processor P (0,0,0), the destination (processor number) (0,0,0) of the packet stored in the input port 5-4 via the selector 7-4 is transmitted to the communication control device 3- (3). 4 is decrypted and matches the own processor number (0,0,0) in the microprogram, so that the processor 2-4 is notified of the arrival of the packet.

Similarly, in the case of a general N-dimension, the non-coincidence coordinates are successively relayed to the element processors having the coordinates obtained by replacing the non-coincidence coordinates with the coordinates of the destination processor by the coordinate conversion cross bus switch in the same manner. Information can be sent to the processor. Since the conversion of the mismatched coordinates is completed at most N times, the maximum communication path length of this coupling method is N. In the three-dimensional example of FIG. 1, the maximum communication path length is 3. However, with regard to lattice coupling, ring coupling, and butterfly coupling, a communication packet can be transferred to a destination processor in a single transmission without a relay operation, so that the communication performance is equivalent to that of a full cross bus switch. FIG. 4 shows the relay operation logic of the communication control device 3 described above.

(4) Structure and Operation of Coordinate Transform Cross Bus Switch FIG. 5 shows an external interface of one L input L output cross bus switch 9. One set of input channels includes two control signal lines IREQ and IACK and a data line IDATA. IREQ is for storing data to be transmitted by the element processor on the transmission side in the output port register 6 and for carrying a signal for notifying the cross bus switch that the transmission processor is in a transmission waiting state, and IACK is for transmitting the next transmission data to the cross bus switch. Is written to the output port register 6 to inform the element processor that the data may be written. The transmission data is placed on IDATA. Similarly,
One set of output channels is composed of two control signal lines OREQ and OACK, and an output data line ODATA. OREQ is for the cross bus switch to carry a signal requesting transfer of transmission data to the input port register 5 of the receiving element processor, and OACK is for carrying the signal that the receiving element processor has completed the transfer. . The transmission data is placed on ODATA. In the above interface, the control signal lines IREQ and IACK are connected to the communication control device 3 of the element processor via the distributor 8 as shown in FIG. 3, and the control signal lines OREQ and OACK are connected to the element It is connected to the communication control device 3 of the processor. Also, the data line IDATA
Is connected to the output port register 6 of the element processor via a distributor 8, and the data line ODATA is connected to the input port register 5 of the element processor via a selector 7. The cross bus switch further includes a mask register write control signal line W and a mask pattern signal line MASK for setting the contents (mask pattern) of a mask register for masking a processor number described later.

FIG. 6 shows an example of the structure of the cross bus switch. In this example, a three-input, six-output cross bus switch is described, but the same applies to a general L-input, L-output case. The element processor that is trying to send, for example the third
In the case where i = 2 in the figure, the communication control device 3 of the processor P (2, j, k) stores the transmission data in the output port register 6 and then sends the number 8 of the cross bus switch to the distributor 8 to specify the same. Select and connect the cross bus switch 9-1 of
Via the control signal line 101 of the input channel 2
It outputs a transmission request signal to REQ2. The cross bus switch connects processors P (0, j, k), P (1, j, k) and P (2, j, k) by input / output channels 0,1,2, respectively. Line IRE
Decoder request signal on Q ₂ is of the crossbar Lee Tutsi 20-
When input to port 3, output port 6 is used to determine the destination.
The part corresponding to the first-dimension coordinates of the destination processor number in the transmission information packet above is decoded, and is transmitted to the destination channel, for example, the channel (output channel 0) corresponding to the destination processor P (0,0,0). 1 is output to the priority control circuits 21-1 to 21-3, and 0 is output to the others on the signal line 26-3. Only a part of the bit string of the processor number to be decoded is
-3 may be input. Therefore, the processor number is
It consists of three fields representing the coordinates of the three-dimensional lattice space. The coordinate transformation cross bus switch of each dimension needs a mechanism for extracting one field corresponding to the dimension of these fields. In general, the range of coordinate values in each dimension is not equal, and accordingly, the position and length of the coordinate field in each dimension vary. In this embodiment, mask registers 24-1 to 24-3 are prepared in each decoder so that this field can be variably selected, and a part of the processor number is masked to decode only the remaining bit strings. ing.

FIG. 11 illustrates the function and configuration of the mask register. In the figure, a 16 × 16 cross bass switch is assumed, but the same applies to cross bass switches of other sizes. Mask register
24 functions as a kind of matrix switch, and selects a partial bit sequence d _i d _j d _k d _l indicating a coordinate of a specific dimension among bit sequences d ₀ , d ₁ ,... D ₃₁ indicating a destination processor number in IDATA And outputs it as an input (address) A ₁ A ₂ A ₃ A ₄ to the decoder (ROM) 20. To do so, use the data line as shown
It suffices to write 0 in the field corresponding to the intersection of d _i d _j d _k d _l and the output line A ₁ A ₂ A ₃ A ₄ , and write 1 in the other fields. Output line
Signal on A ₁ A ₂ A ₃ A ₄ is decoded as a binary number of 4 bits representing the priority control circuit number by the decoder 20, converted into a transmission request signal r ₀ ~r ₁₅ to the priority control circuit 0-15 Is done. In other words, if the contents of d _i d _j d _k d _l are “0000”, they are decoded into signals of “1000... 0” to select the priority control circuit 0. When this switch is used as a cross bus switch smaller than 16 × 16, for example, a 4 × 4 cross bus switch, the mask register 24 selects only 2 bits and uses it as an input address A ₁ A ₂ to the decoder ROM 20. A ₃ A ₄ becomes 0. Therefore, in this case, the decoder RO
M is only partially used. Mask register 24-1
The contents of .about.24-3 can be set by instructing the mask register write control circuit 25 from outside (such as an element processor or a host computer) (using the W and MASK signal lines).

A transmission request is transmitted from each input channel to the priority control circuit 21-1, and one of them is selected according to a predetermined logic, as described later. Thereafter, the priority control circuit 21-1 confirms that the buffer 23-1 in the selective transfer control circuit 22-1 is empty, and the input selected by the selective transfer control circuit 22-1 by the signal line 27-1. Give the channel number (Channel 2). As a result, processor P
(2, j, k) of the output port is sent information packet in on 6 (through the distributor 8 and the input channel 2 of the data lines 102 (i.e. IDATA ₂₎₎ buffer of the selected transfer control circuit 22-1 23-1. During this time, the priority control circuit
21-1 is in a busy state, and when the transfer is completed, the next selection operation is started.

When the data is transferred to the buffer 23-1, the selective transfer control circuit 22-1 outputs the data to the output destination processor (processor P (0,
j, k)) on the signal line OREQ ₀ requesting transmission, that is, on the control signal 103. A transmission request signal from a plurality of coordinate transformation cross bus switches is input to the selector 7-2 of the processor P (0, j, k), and one of the transmission request signals is selected according to a predetermined logic, and the communication control device 3 is selected. -2. When the input port register 5-2 is empty, the communication control device 3-2 writes the data on the data line ODATA ₀ , that is, the data on the data line 104, to the input port register 5-2 via the selector 7-2. When writing is completed, it outputs a write completion signal on the control signal line OACK _0. Negates the transmission request signal of selecting the transfer control circuit 22-1 on line OREQ ₀ by entering a write completion signal from line OACK _0, processor P (0, j, k) the communication control unit 3-2 detects this in Then, the reception completion signal on the line OACK ₀ is negated. The buffer 23-1 of the selective transfer control circuit 22-1 is again in a transfer enable state, and the selector 7-2 of the processor P (0, j, k) can also select another cross bus switch.

On the other hand, when the priority control circuit 21-1 comes out of the busy state, the decoder 20 which has detected this by the signal line 26-3.
-3 sends a transfer completion signal on IACK ₂ to processor P (2, j, k). The communication control device 3 of the processor P (2, j, k) that has received the transfer completion signal on IACK ₂ can negate the transfer request signal on IREQ ₂ and put the next transmission data on the output port 6 Becomes

An example of the logic of the priority control circuits 21-1 to 21-3 is shown in FIG.
Shown in the figure. In this example, the inputs from the three decoders are 3
Paying attention to the bit information, that is, 0 to 7,
A method is employed in which a pattern of a permission signal corresponding to each input is stored in a memory (RAM) 15 of the entry. However, the logic of the priority control circuit is not limited to this.

Second Embodiment FIGS. 8 and 9 are explanatory views of the connection method of the second embodiment.
The difference from the first embodiment is that, instead of performing the relay operation by the communication control device 3 in the element processor, the relay cross bus switch 14 installed for each element processor performs this operation.

(1) Structure and operation of the relay cross bus switch The structure of the relay cross bus switch is basically the same as that of the coordinate conversion cross bus switch, but the destination processor number input to the decoder is not one coordinate field but three. Are all coordinate fields. A detailed explanatory diagram of the destination decoding section of the relay cross bus switch will be described with reference to FIG. The destination processor number input from the data line IDATA and the contents of the own processor number register 50 that stores the own processor number prepared in the relay cross bus switch are input to the comparator 51, and are bitwise EXORed and matched. In this case, 1 is output, and if they do not match, 0 is output from the signal lines 52-1 to 52-1.
Output on 52-32. This output is input to the mask register 24, and when 0 is written in the intersection field of the mask register 24, that is, when the mask is not masked,
This input is output as it is on output lines A ₁ A ₂ A ₃ , where a wired AND is taken. As a result, only when all the comparator outputs connected to the output lines without being masked are 1,
1 is output to the output line. If the first to third coordinates of the processor number are assigned to each output line A ₁ A ₂ A ₃ , 1 is output to the output line if all coordinate fields are equal to the corresponding field of the own processor number, and so on. Otherwise (in the case of mismatched coordinates) 0 will be output. The signal on the output line is inverted and input to the decoder 20. For example, assume that the first coordinate is represented by bits 0, 1, and 2 of the destination processor number input from the data line IDATA in the figure. The bits are input to the comparator 51 together with the corresponding bits 0, 1, and 2 of the own processor number register 50. If all the bits match, 1 is output to the signal lines 52-1, 52-2, and 52-3. The first coordinate field and the intersection field 53-1,53-2,53-3 first output line A ₁ of the mask register 0, 1 written to the intersection field with other output line A ₂ A ₃ The first
Only a comparison result to the output line A ₁ is sent. Accordance connexion, only when all the signal lines 52-1,52-2,52-3 1 is output, 1 is output to the first output line A ₁ of the mask register.

The decoder converts the signal on output line A ₁ A ₂ A ₃ as a binary address to a channel number and sends a 1 to the channel priority control circuit and a 0 to the others. For example, when the signals on the output lines A ₁ A ₂ A ₃ are all 1, that is, for the inverted decoder input address '000', the channel 0, that is, the channel to the own processor is selected.

(2) Communication method In FIG. 8, one coordinate transformation cross bus switch 9 is used.
When a communication packet is input to the relay cross bus switch 14, the destination of the packet is decoded. If the packet is addressed to this processor, the switch is connected to the input port 5 of the element processor to input the packet. If the destination is any other address, the coordinate conversion cross bus switch 9 for converting the mismatched coordinates is selected and connected thereto. Relay cross bus switch 14
Is the same as that of the coordinate transformation cross bus switch 9.

FIG. 9 shows the element processor P (0,0) from the element processor P (i, j, k) via the relay cross bus switch of the element processor P (0, j, k), P (0,0, k). , 0) is shown by a broken line in the example of transferring a packet.

In the second embodiment, the communication control device 3 decodes the destination information (communication destination processor number) of the communication packet as described in the first embodiment, and performs a specific coordinate conversion cross-bus switch or processing based on the result. It does not have the function of selecting the device 2 and the function of transmitting a communication packet, but merely the function of interfacing with the relay cross bus switch 14.

Evaluation In the example of FIG. 9, three coordinate transformation cross bus switches (9
-1,9-4,9-5) and four relay cross bus switches (14
-1, 14-2, 14-3, 14-4), a total of seven switching operations are required. In the first embodiment, the number of crossing points, that is, the unit switching operation for transferring a communication packet from one input / output port / buffer to the next buffer / input / output port is counted as three times.
Considering the determination / selection process in the control unit 3 of the element processor, the time required for the transfer is the same after all. In the first embodiment (a method in which the processor itself relays), since a maximum of N transmission operations are required, the maximum communication path length of this switch is N, and the number of cross points in hardware is n. ₁ × n ₂ ×… × n _N × (n ₁ + n ₂ +… + n _N )
Becomes The maximum value of n _K ² : k = 1,... N is the maximum coupling capacity of the cross bass switch. Further, in the second embodiment (a system having a relay cross bus switch corresponding to a processor), when performing the relay operation by the relay cross bus switch 14 itself is regarded as one transmission operation, a maximum of 2N + 1 transmission operations are required. That is, the maximum communication path length of this switch is 2N + 1. The amount of hardware is represented by n ₁ × n ₂ × ... × n _N × {(N + 1) ² + n ₁ + n ₂ +... + _{N N} }.

Next, by the mutual coupling method of the present invention, when the maximum coupling capacity of one cross bus switch is given, it is possible to easily find a configuration that can provide the highest performance and a configuration that requires a minimum amount of hardware. Show.

The performance is determined by the communication path length N or 2N + 1, assuming that the number of signal lines for coupling between processors of the cross bus switch is fixed. That is, higher performance can be obtained by reducing the dimension of the space where processors are logically arranged as much as possible. For example, in the case of the processor relay system shown in the first embodiment, when the number of processors is L and the maximum number of processors that can be combined in one cross bus switch is n, q = [logL / logn] +1 uses the cross bus switch. This is the minimum communication path length when there is. Here, [] is a symbol that takes an integer part of a quotient. The configuration at this time is such that the element processors are arranged in a hypercube-shaped region of a q or q + 1-dimensional lattice space, and the number of processors capable of coupling all the element processors constituting the one-dimensional partial region therein is the maximum value n. These are combined using a certain cross bass switch.

On the other hand, the hardware amount is n ₁ × n ₂ × ... × n _N × (n ₁ + n ₂ +
.. + _{N N} ), and the case of n _i = 2 is obviously the minimum amount of hardware. However, in the system using the relay cross bus switch shown in the second embodiment, as shown in FIG.
The amount of hardware is minimized when taking another configuration. For example, 25
In the case of a 6-unit configuration, the amount of hardware is the smallest when arranged in 8 × 8 × 4 3 dimensions, and in the case of a 4096-unit configuration, 8 × 8 × 8 × 8 units are arranged in 4 dimensions. In addition, from the standpoint that it is better to have high performance even with a certain amount of hardware, a two-dimensional configuration of 8 × 8 to 32 × 32 is required for a configuration of 64 to 1024 element processors.
For a configuration of ~ 32768 units, a three-dimensional configuration of 4x8x8 to 32x32x32 would be appropriate.

〔The invention's effect〕

According to the present invention, it is possible to configure a switch that connects a large number of element processors that cannot be connected by one cross bus switch (full cross bus switch) with a coupling capacity close to that of a full cross bus switch regardless of the number of processors. Here, the coupling capability close to a full cross bus switch means that the communication performance is high (the number of cross points passing is small) and the coupling topology between processors (lattice, ring, butterfly) that is important in application is included. This means that communication can be performed with a minimum number of crosspoints for the inter-processor communication pattern. In the range of the prior art, a hypercube is known as a network including the above connection topology and capable of connecting a large number of processors, but the connection method of the present invention employs a communication pattern other than the specific connection topology. Is much better than Hypercube. In particular, by using a relay cross-by switch, it is possible to completely prevent destruction. According to the present invention, when the (technically and economically) upper limit value and the number of element processors of the scale of the cross bus switch for coordinate conversion (the number of input / output channels of the cross bus switch) and the number of element processors are arbitrarily given, the optimum (the maximum communication performance, A method of constructing a coupling system with a minimum amount of hardware or an intermediate between the two is provided, and it is possible to bridge the gap between the full cross bus switch and the hypercube.

Furthermore, it is possible to determine the connection relationship of the element processors so that the coordinate transformation switches of each dimension can be stored for each mounting unit such as a chip, a module, a board, a housing, and the like.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a diagram of a supercuboid arrangement of processors, FIG. 3 is a block diagram of an element processor, and FIG. 4 shows a relay operation of the communication control device 3. FIG. 5 is an explanatory diagram of the interface of the cross bus switch, FIG. 6 is a configuration diagram of the cross bus switch, FIG. 7 is an explanatory diagram showing an example of the priority control circuit, and FIG. 8 is a configuration of the second embodiment. FIG. 9, FIG. 9 is an explanatory diagram of the operation of the second embodiment, FIG. 10 is an explanatory diagram showing the amount of hardware when a relay cross bus switch is included, FIG. 11 is an explanatory diagram of a mask register, and FIG. FIG. 4 is an explanatory diagram of a decoding unit of a cross bus switch. 1 ... relay device, 2-2-4 ... processing device, 3-3-4
... Communication control device, 5-5-4 ... Input port register, 6-6-4 ... Output port register, 7-7-4 ...
... selector, 8-8-4 ... distributor, 9-1-9-5 ...
… Coordinate conversion cross bus switch, 20,20-1 to 20-3 ……
Processor number decoders, 21-1 to 21-3 ... priority control circuits, 22-1 to 22-3 ... selective transfer control circuits, 24, 2
4-1 to 24-3 ... Mask register, 14-1 to 14-4 ...
… Relay cross bus switch, 15 …… Memory (RAM), 50…
... own processor number register, 51 ... ... comparator

Continued on the front page (72) Inventor Kazuo Nakao 1099 Ozenji Temple, Aso-ku, Kawasaki City, Kanagawa Prefecture Inside Hitachi, Ltd. System Development Laboratory Co., Ltd. (72) Inventor Takehisa Hayashi 1-280, Higashi-Koikekubo, Kokubunji-shi, Tokyo Hitachi, Ltd. In the laboratory (72) Inventor Teruo Tanaka 1-280 Higashi Koikekubo, Kokubunji, Tokyo, Japan Inside the Central Research Laboratory of Hitachi, Ltd. (72) Inventor Shigeo Nagashima 1-280 Higashi Koikekubo, Kokubunji, Tokyo, Japan, Central Research Laboratory of Hitachi, Ltd. (56 References JP-A-64-4856 (JP, A) IPSJ 35th (late 1987) National Convention (September 28-30, 1987) 135-136 (3C-5) Setsu Suzuoka Sadao Nakamura Junichi Fujita Shigeru Koyanagi "The concept of massively parallel AI machine"

Claims (4)

(57) [Claims] 1. A _{L = n 1 × n 2 ×} ... × n N pieces of N-dimensional lattice processors and bonded to each other said element processors L × the element including a processor _{(1 / n 1 + 1 /} n 2 + ... + 1 / n _N ) In a parallel computer constituted by an interconnection network including crossbar switches, a) N-dimensional grid coordinates (i ₁ , i ₂ ,..., I _N ), 0 ≦ i _k ≦ n _k -1
Means for identifying each element processor by element processor numbers represented by (k = 1, 2,..., N); b) the element processor number and the number _{k of the} k-th element processors (k = 1, 2) ,..., N), based on the positional relationship between the two element processors specified by the above-described identifying means, the information transmission destination of the element processor which is the information transmission source among the two element processors. And c) means for operating the crossbar switch so that information is transmitted to the selected element processor. 2. A parallel computer as claimed in claim 1, wherein said interconnection network relays information packets to each element processor for relaying information packets from a source element processor to a final destination element processor. A parallel computer comprising: 3. The parallel computer according to claim 2, wherein: said information packet relay means: d) an information packet of a departure source element processor comprising transmission data and an element processor number of a final destination element processor; And (e) the first element processor number of the own element processor.
Element processor number _{(i 1, i 2, ...} , i N) of the captured second element processor number is an element processor number of the final destination element processors in the information packet _{(j 1, j 2, ...} , j
_N ) is compared with each coordinate, and coordinates i _k and j _k (k = 1, 2,...,
N) means for detecting one of the dimensions k in which the mismatch (i _k ≠ j _k ) is detected; and f) coordinates of the detected one dimension from among the N crossbar switches connected to the self-element processor. Means for selecting a crossbar switch to which a plurality of element processors having different element processor numbers having the same coordinate in other dimensions are connected; g) means for inputting the information packet to the selected crossbar switch; ) said first element processor number _{(i 1, i 2, ...} , i N) and the second element processor number _{(j 1, j 2, ...} , j N) If the match, the own element processor the Means for determining the final destination element processor and inputting the information packet to the processing device of the own element processor. 4. The parallel computer according to claim 1, wherein the parallel computer comprises: a) a plurality of relay crossbar switches having N + 1 inputs and N + 1 outputs provided to each of the element processors; Nu) relaying the information packet to the final destination element processor by connecting the input port register and the output port register of the source element processor; and l) the source element processor via the relay crossbar switch. A parallel computer comprising: N crossbar switches connected to a processor.