JPH0113130B2 - - Google Patents
Info
- Publication number
- JPH0113130B2 JPH0113130B2 JP56208241A JP20824181A JPH0113130B2 JP H0113130 B2 JPH0113130 B2 JP H0113130B2 JP 56208241 A JP56208241 A JP 56208241A JP 20824181 A JP20824181 A JP 20824181A JP H0113130 B2 JPH0113130 B2 JP H0113130B2
- Authority
- JP
- Japan
- Prior art keywords
- decimal
- digit
- carry
- during
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000012546 transfer Methods 0.000 claims description 14
- 230000004044 response Effects 0.000 claims description 4
- 230000015654 memory Effects 0.000 description 44
- 238000012545 processing Methods 0.000 description 17
- 230000006870 function Effects 0.000 description 16
- 238000000034 method Methods 0.000 description 10
- 238000003860 storage Methods 0.000 description 9
- 101000580780 Arabidopsis thaliana Cysteine protease RD19A Proteins 0.000 description 8
- 230000007423 decrease Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000006243 chemical reaction Methods 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 238000012937 correction Methods 0.000 description 4
- 238000006073 displacement reaction Methods 0.000 description 4
- 230000010365 information processing Effects 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 238000013461 design Methods 0.000 description 3
- 102100031577 High affinity copper uptake protein 1 Human genes 0.000 description 2
- 101710196315 High affinity copper uptake protein 1 Proteins 0.000 description 2
- 102100031145 Probable low affinity copper uptake protein 2 Human genes 0.000 description 2
- 101710095010 Probable low affinity copper uptake protein 2 Proteins 0.000 description 2
- 101150026303 HEX1 gene Proteins 0.000 description 1
- 102000016870 Hexosaminidase B Human genes 0.000 description 1
- 108010053345 Hexosaminidase B Proteins 0.000 description 1
- 101100329714 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) CTR3 gene Proteins 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000001143 conditioned effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000004313 iron ammonium citrate Substances 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000011084 recovery Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/491—Computations with decimal numbers radix 12 or 20.
- G06F7/4915—Multiplying; Dividing
Landscapes
- Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Complex Calculations (AREA)
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US06/219,810 US4484300A (en) | 1980-12-24 | 1980-12-24 | Data processor having units carry and tens carry apparatus supporting a decimal multiply operation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57172446A JPS57172446A (en) | 1982-10-23 |
| JPH0113130B2 true JPH0113130B2 (US06312121-20011106-C00033.png) | 1989-03-03 |
Family
ID=22820876
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56208241A Granted JPS57172446A (en) | 1980-12-24 | 1981-12-24 | Information processor using unit digit carrying device and ten digit carrying device supporting decimal multiplication |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US4484300A (US06312121-20011106-C00033.png) |
| JP (1) | JPS57172446A (US06312121-20011106-C00033.png) |
| AU (1) | AU554953B2 (US06312121-20011106-C00033.png) |
| CA (1) | CA1170371A (US06312121-20011106-C00033.png) |
Families Citing this family (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4589087A (en) * | 1983-06-30 | 1986-05-13 | International Business Machines Corporation | Condition register architecture for a primitive instruction set machine |
| JPS6011927A (ja) * | 1983-07-01 | 1985-01-22 | Hitachi Ltd | １０進乗算装置 |
| US4608659A (en) * | 1983-09-30 | 1986-08-26 | Honeywell Information Systems Inc. | Arithmetic logic unit with outputs indicating invalid computation results caused by invalid operands |
| US4604695A (en) * | 1983-09-30 | 1986-08-05 | Honeywell Information Systems Inc. | Nibble and word addressable memory arrangement |
| US4615016A (en) * | 1983-09-30 | 1986-09-30 | Honeywell Information Systems Inc. | Apparatus for performing simplified decimal multiplication by stripping leading zeroes |
| US4672360A (en) * | 1983-09-30 | 1987-06-09 | Honeywell Information Systems Inc. | Apparatus and method for converting a number in binary format to a decimal format |
| US4604722A (en) * | 1983-09-30 | 1986-08-05 | Honeywell Information Systems Inc. | Decimal arithmetic logic unit for doubling or complementing decimal operand |
| US4638450A (en) * | 1983-09-30 | 1987-01-20 | Honeywell Information Systems Inc. | Equal nine apparatus for supporting absolute value subtracts on decimal operands of unequal length |
| US4942547A (en) * | 1985-04-11 | 1990-07-17 | Honeywell Bull, Inc. | Multiprocessors on a single semiconductor chip |
| US4999802A (en) * | 1989-01-13 | 1991-03-12 | International Business Machines Corporation | Floating point arithmetic two cycle data flow |
| US5212662A (en) * | 1989-01-13 | 1993-05-18 | International Business Machines Corporation | Floating point arithmetic two cycle data flow |
| US5440749A (en) * | 1989-08-03 | 1995-08-08 | Nanotronics Corporation | High performance, low cost microprocessor architecture |
| US20050022322A1 (en) * | 2003-05-12 | 2005-02-03 | Eduardo Jimenez | Powered toothbrush with curved neck and flexible shaft and single battery |
| US7167889B2 (en) | 2003-05-12 | 2007-01-23 | International Business Machines Corporation | Decimal multiplication for superscaler processors |
| US7266580B2 (en) * | 2003-05-12 | 2007-09-04 | International Business Machines Corporation | Modular binary multiplier for signed and unsigned operands of variable widths |
| US7136893B2 (en) * | 2003-07-10 | 2006-11-14 | International Business Machines Corporation | Decimal multiplication using digit recoding |
| US10127015B2 (en) * | 2016-09-30 | 2018-11-13 | International Business Machines Corporation | Decimal multiply and shift instruction |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4897460A (US06312121-20011106-C00033.png) * | 1972-03-25 | 1973-12-12 | ||
| JPS5345948A (en) * | 1976-10-07 | 1978-04-25 | Nippon Telegr & Teleph Corp <Ntt> | Multiplier circuit |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3319056A (en) * | 1965-11-19 | 1967-05-09 | Burroughs Corp | Multiplication unit operating serially by digit and parallel by bit |
| FR2301870A1 (fr) * | 1975-02-19 | 1976-09-17 | Majos Jacques | Circuit multiplicateur a fort debit numerique notamment pour filtre numerique |
| US4075704A (en) * | 1976-07-02 | 1978-02-21 | Floating Point Systems, Inc. | Floating point data processor for high speech operation |
-
1980
- 1980-12-24 US US06/219,810 patent/US4484300A/en not_active Expired - Fee Related
-
1981
- 1981-12-11 CA CA000392077A patent/CA1170371A/en not_active Expired
- 1981-12-24 AU AU78870/81A patent/AU554953B2/en not_active Ceased
- 1981-12-24 JP JP56208241A patent/JPS57172446A/ja active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4897460A (US06312121-20011106-C00033.png) * | 1972-03-25 | 1973-12-12 | ||
| JPS5345948A (en) * | 1976-10-07 | 1978-04-25 | Nippon Telegr & Teleph Corp <Ntt> | Multiplier circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CA1170371A (en) | 1984-07-03 |
| AU7887081A (en) | 1982-07-01 |
| JPS57172446A (en) | 1982-10-23 |
| AU554953B2 (en) | 1986-09-11 |
| US4484300A (en) | 1984-11-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0113130B2 (US06312121-20011106-C00033.png) | ||
| US4604695A (en) | Nibble and word addressable memory arrangement | |
| US4484259A (en) | Fraction bus for use in a numeric data processor | |
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| JPH022171B2 (US06312121-20011106-C00033.png) | ||
| US4638450A (en) | Equal nine apparatus for supporting absolute value subtracts on decimal operands of unequal length | |
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| JPH0139131B2 (US06312121-20011106-C00033.png) | ||
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| US4240144A (en) | Long operand alignment and merge operation | |
| US4672360A (en) | Apparatus and method for converting a number in binary format to a decimal format | |
| US4615016A (en) | Apparatus for performing simplified decimal multiplication by stripping leading zeroes | |
| US4224677A (en) | Effective digit count on a resultant operand | |
| JPS5917457B2 (ja) | ２進化１０進訂正装置 | |
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| US4608659A (en) | Arithmetic logic unit with outputs indicating invalid computation results caused by invalid operands | |
| US4604722A (en) | Decimal arithmetic logic unit for doubling or complementing decimal operand | |
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