JPH01130245A - Trace control system for peripheral controller - Google Patents

Abstract

PURPOSE:To utilize a counter value as the timer stamp of a trace by outputting a system timer value held by a system timer mechanism to the counter of a peripheral equipment by an information processing subsystem. CONSTITUTION:A peripheral controller 4 executes the transfer of a data to an information processing subsystem 6, and also, controls a peripheral equipment 5. When the information processing subsystem 6 executes an output command of a system timer value, the system timer value is outputted to a signal line 402. A system synchronizing timer counter 46 inputs the timer value of the signal 402 as the initial value of time. A trace controller 44 monitors the operation of a microprocessor 40, applies an interruption to the microprocessor 40 when an event to be traced is detected, writes a system synchronizing timer value and the contents of a trace object register in a trace memory area 45, and restarts the operation of the microprocessor.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to trace control of processing events of a peripheral controller sp lj, and in particular to control of time stamps in the trace.

Conventional Technology Conventional 1 In order to clarify the order of occurrence of trace events in a trace method that traces and stores processing events of a peripheral control device, a system timer built into the peripheral control device that operates asynchronously and independently of the system timer of the information processing subsystem is used. The value of the clock counter was used as the timestamp of the trace information. On the other hand, a system timer is generally used to time stamp various traces in an information processing subsystem.

Problems to be Solved by the Invention In the conventional time stamp method for tracing peripheral control devices, the clock counter used for time stamps operates independently and asynchronously with the system timer of the information processing subsystem.

When checking the peripheral control device control trace of the information processing subsystem that uses the system timer as a trace timestamp, it is difficult to correspond between the processing events of the peripheral control device and the peripheral control device control events of the information processing subsystem. However, it has the disadvantage that failure analysis takes a long time.

The present invention has been made in order to eliminate the above-mentioned drawbacks inherent in the prior art, and therefore, an object of the present invention is to facilitate the verification of the above-mentioned phenomena.

An object of the present invention is to provide a new trace control method for a peripheral control device that makes it possible to greatly reduce the time required for failure analysis.

Means for Solving the Problems In order to achieve the above object, a trace control method for a peripheral control device according to the present invention outputs a system timer value held by a system timer mechanism in an information processing subsystem to a peripheral control device. a counter for setting the system timer value outputted from the information processing subsystem as an initial value in one peripheral control device; and a timer for updating the counter at regular intervals upon receipt of the system timer value. and means for generating a time signal, and each time a processing event of one peripheral control device is stored in a trace memory, the value of the counter is used as a trace time stamp.

Embodiment Next, a preferred embodiment of the present invention will be specifically explained with reference to the drawings.

FIG. 7 is a block diagram showing an embodiment of a microprogram-controlled peripheral control device to which the present invention is applied.
The figure is a block diagram showing an example of an information processing system to which this peripheral control device is connected.

In FIG. 1, a peripheral control device 1I (2) transfers commands and data to the information processing subsystem 6 via an input/output interface, and controls the operation of the peripheral device 3 via a device interface.

The microprocessor q executes a control microprogram stored in the processor memory 4 (/) and decodes commands from the information processing subsystem 6.

It is configured to control the operation of the peripheral device S as well as the processor. When the information processing subsystem 6 executes the system timer value output command.

The input/output interface Q activates the signal line IIoi indicating execution of the system timer value output command, and outputs the system timer value output from the information processing subsystem 6 to the signal line Dako. System synchronous timer counter Hiro6 is signal m
When 440/ is activated, the system timer value output to the signal line RI is taken in and set as the initial time value. Clock signal generation circuit 4 (7).

The operation starts with the activation of the signal line uO/.

It outputs a signal pulse IIo3 that counts up and updates the system synchronous timer counter 4!6 at a set fixed period. The trace controller monitors the operation of the microprocessor, and when it detects an event to be traced, it generates an interrupt to the microprocessor ψ and interrupts the execution of the microprocessor.

Signal line u connected to system synchronous timer counter O
The system synchronization timer value output to Qu.

The contents of the register to be traced in the microprocessor Q are written to the area of the trace memory indicated by the trace memory address (not shown), the trace memory address is incremented, and then execution of the microprocessor is resumed.

Trace control method! is a memory that stores trace information cyclically based on the trace memory address, and when the trace memory address reaches the highest address of trace control method 3, the primary trace memory address becomes the lowest address of trace memory IIS, and the trace information is stored. The storage of will be overlaid. When a command to read trace information is executed from the information processing subsystem 6, the trace controller starts from the address indicated by the ll'lu trace memory address.

Read all contents of trace memo IJ q3 and transfer to information processing subsystem B. Clock signal generation circuit 417
The period of the signal pulse 440.7 generated by is set to the same period as the update period of the system timer mechanism 3 or a period shorter than that. Every time the information processing subsystem 6 executes a system timer value output command.

In order to set the initial value of the system synchronization timer counter tIA, the information processing subsystem 6 is
If the system timer value output command is executed at an interval (which is very long compared to the update cycle of the system timer mechanism 3), the synchronization between the value of the system synchronization timer counter II6 and the system timer can be appropriately maintained.

As described in detail, according to the present invention, the time stamp of trace information collected within one peripheral control device and the time stamp of trace information collected within the information processing subsystem are displayed in the same manner.

This has the effect that events obtained from this trace information can be easily collated.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a microprogram-controlled peripheral control device to which the present invention is applied. FIG. 1g is a block diagram showing an example of an information processing system. l... central processing unit, co... main memory, J...
System timer mechanism, peripheral control device, j...
Peripheral equipment, microprocessor, II/processor memory, tacho...input/output interface, t
Ij...Device interface, Ij...Trace controller, S...Trace memory, R6...
System synchronous timer counter, Hiro7... Clock signal generation circuit, lIO/... System timer value output command execution display signal, 1I02... System timer value output signal,
1I03...System synchronous timer counter count up pulse signal, a□a...System synchronous timer value output signal Patent applicant NEC Corporation Representative Patent attorney Yutabe Kumagai

Claims (1)

[Claims] A peripheral control device that is connected to an information processing subsystem that includes a central processing unit, a main storage device, and a system timer mechanism that keeps time in the system, and that controls the operation of peripheral devices under the control of the central processing unit. , in a peripheral control device configured to store processing events processed by the peripheral control device in a built-in trace memory in chronological order, and to transfer the contents of the trace memory to an information processing subsystem according to a command from a central processing unit. , a system synchronization timer in which the information processing subsystem is equipped with means for outputting a system timer value held by a system timer mechanism to a peripheral control device at fixed intervals, and the system timer value output to the peripheral control device is held as an initial value. a counter; and a clock signal generating means for generating a clock signal for updating the system synchronous timer counter at regular intervals using the output of the system timer value as a trigger, and a trace memory for processing events of the peripheral control device. A trace control method for a peripheral control device, characterized in that a system synchronization timer value held by the system synchronization timer counter is stored as a trace timestamp each time the system synchronization timer counter is stored.