JPH01129688A - Picture signal receiver - Google Patents

Picture signal receiver

Info

Publication number
JPH01129688A
JPH01129688A JP28885487A JP28885487A JPH01129688A JP H01129688 A JPH01129688 A JP H01129688A JP 28885487 A JP28885487 A JP 28885487A JP 28885487 A JP28885487 A JP 28885487A JP H01129688 A JPH01129688 A JP H01129688A
Authority
JP
Japan
Prior art keywords
signal
data
circuit
output
squelch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28885487A
Other languages
Japanese (ja)
Inventor
Mitsumasa Saito
光正 斉藤
Shinji Shibao
新路 柴尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP28885487A priority Critical patent/JPH01129688A/en
Publication of JPH01129688A publication Critical patent/JPH01129688A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent flickering of a video image and disturbance of it by reading a data just before the stop repetitively so as to stop the video image at the video image just before the reception of a mixed signal. CONSTITUTION:A reception level detection circuit 10 is provided to a signal reception section and when transmission signals of two stations are received in mixture, that is, a received power is lower than a received power threshold value, a squelch circuit 14 squelches a reproduced data and an extracted clock to be OFF to stop data write in a memory circuit 17 having a capacity by one frame of picture data installed at the post-stage of the squelch circuit 14. Then the data given to the memory circuit 17 is read repetitively just before the squelch circuit 14 is operated and when the received power is over the threshold value, the data inputted to the memory 17 is read at any time.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、空間的に離れた2局以上の送信局の同一画
像信号を移動体に搭載された1局の受信局が受信する光
空間伝送通信系における画像信号受信装置に関するもの
である。
[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to an optical space system in which a single receiving station mounted on a mobile body receives the same image signal from two or more spatially separated transmitting stations. The present invention relates to an image signal receiving device in a transmission communication system.

〔従来の技術〕[Conventional technology]

第3図は、従来の画像信号受信装置を示す図であl)、
 fn、 +21は空間的に離れた2局の送信局A。
FIG. 3 is a diagram showing a conventional image signal receiving device l),
fn, +21 are two transmitting stations A that are spatially separated.

及び送信局B、+31は前記送信器A(1)の送信画像
信号A、+41は前記送信器B(2)の送信画像信号B
、+51は前記送信画像信号A(3)及び前記送信画像
信号B(4Iから、再生データと抽出クロックを生成す
る受信信号再生回路9(61は前記受信信号再生回路(
5Iの出力信号である再生データ、(7)は前記受信信
号再生回路+51の出力信号である抽出クロック、f8
)は前記再生データ+61及び前記抽出クロック(7)
から画像信号に信号処理を行なう画像処理系、(9)は
画像信号受信装置を搭載した移動体、イは移動体+91
の移動方向である。第4図は、前記再生データ(6)及
び抽出クロック(71のタイミングチャートである。
and transmitting station B, +31 is the transmitted image signal A of the transmitter A (1), and +41 is the transmitted image signal B of the transmitter B (2).
, +51 is the received signal regeneration circuit 9 (61 is the received signal regeneration circuit (61 is the received signal regeneration circuit (
(7) is the extracted clock which is the output signal of the received signal regeneration circuit +51, f8 is the reproduced data which is the output signal of 5I,
) is the reproduced data +61 and the extracted clock (7)
(9) is a mobile body equipped with an image signal receiving device; A is a mobile body +91
is the direction of movement. FIG. 4 is a timing chart of the reproduction data (6) and the extraction clock (71).

次に動作について説明する。受信信号再生回路(5弓ま
、移動体(91が移動する間第4図のToからT2の区
間は送信器A(11の送信信号A(31のみを受信し。
Next, the operation will be explained. While the received signal reproducing circuit (5 bows) and the moving body (91) are moving, the section from To to T2 in FIG. 4 receives only the transmitted signal A (31) of the transmitter A (11).

T2からT3の区間は送信器A(1)の送信信号A f
31と送信器B(21の送信信号13 F41の混合信
号を受信し。
The interval from T2 to T3 is the transmission signal A f of the transmitter A(1)
31 and transmitter B (receives the mixed signal of the transmitted signal 13 of 21 and F41.

T3からT5の区間は送信器B(2)の送信信号B i
41のみを受信し、全区間において第4図1alの再生
データ+61と第4図1alの抽出クロック(7)ヲ画
像処理系181へ送出する。
The period from T3 to T5 is the transmission signal B i of transmitter B (2)
41, and sends out the reproduced data +61 of FIG. 4 1al and the extracted clock (7) of FIG. 4 1al to the image processing system 181 in the entire interval.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

従来の画像信号受信装置は以上のように構成されている
ので、第4図のT2からT3の区間にて。
Since the conventional image signal receiving apparatus is configured as described above, in the section from T2 to T3 in FIG.

受信器が混合信号を受信する為9画像処理系に送出する
再生データ(6)及び抽出クロック(71が第4図のよ
うに乱れ、処理後の映像がちらついたシ、乱れたりする
問題があった。
In order for the receiver to receive the mixed signal, the reproduced data (6) and the extraction clock (71) sent to the image processing system 9 are disturbed as shown in Figure 4, and there is a problem that the processed image may flicker or be distorted. Ta.

この発明は上記のような問題点を解消するためになされ
たもので、受信期間第4図のToからT5゜において処
理後の映像にちらつきや乱れが発生しない装置を得るこ
とを目的とする。
This invention has been made to solve the above-mentioned problems, and aims to provide an apparatus in which flickering or disturbance does not occur in the processed video during the reception period from To to T5° in FIG. 4.

〔問題点を解決するための手段〕[Means for solving problems]

この発明に係る画像信号受信装置は、信号受信部に受信
レベル検出回路を付加し、2局の送信信号が混合して受
信される時には全受信電力が低下することを利用し、受
信電力がある受信電力閾値を下まわった場合には、スケ
ルチ回路により再生データと抽出クロック’i OFF
にスケルチし、スケルチ回路の後段に設置した画像デー
タ1フレーム分の容量を持つメモリ回路へのデータ書き
込みを停止し、スケルチ回路が動作する直前にメモリへ
入力されたブータラ、くり返し読みだすとともに。
The image signal receiving device according to the present invention adds a reception level detection circuit to the signal receiving section, and takes advantage of the fact that the total reception power decreases when the transmission signals of two stations are mixed and received, and the reception power is When the received power falls below the threshold, the squelch circuit turns off the reproduced data and the extracted clock.
It squelches, stops writing data to a memory circuit with a capacity for one frame of image data installed after the squelch circuit, and repeatedly reads out the booter input to the memory just before the squelch circuit operates.

(す 受信電力が閾値を上まわった場合は、メモリに入力され
るデータを随時読みだすようにしたものである。
(If the received power exceeds a threshold value, the data input to the memory is read out at any time.

〔作用〕[Effect]

この発明においては、第4図のT2からT3の区間にて
受信器が混合信号を受信しても映像がその間混合信号受
信開始直前の映像にて停止し、ちらつきや乱れが無くな
る。
In this invention, even if the receiver receives the mixed signal in the interval from T2 to T3 in FIG. 4, the image stops at the image immediately before the start of receiving the mixed signal during that time, eliminating flickering and disturbance.

〔実施例〕〔Example〕

以下この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.

第1図において(1)から(9)までは第1図と同一で
ある。aOは、受信信号の受信レベルが一定の閾値PO
よりも低くなった場合に検出信号を送出する受信レベル
検出回路、 flllは前記受信レベル検出回路(11
mから出力される受信レベル低下検出信号、σ2は前記
再生データ(61より画像データ1フレームに同期した
パルスを出力するデータフレーム検出回路。
In FIG. 1, (1) to (9) are the same as in FIG. aO is the threshold PO at which the reception level of the reception signal is constant.
A reception level detection circuit (11) is a reception level detection circuit that sends out a detection signal when the signal becomes lower than .
σ2 is a data frame detection circuit that outputs a pulse synchronized with one frame of image data from the reproduction data (61).

03は前記データフレーム検出回路11zから出力され
るデータフレーム同期信号、 Oaは前記再生データ(
61,前記抽出クロックf” k e前記受信レベル低
下検出信号flllと前記データフレーム同期信号0多
とからデータフレームに同期してOFFにスケルチする
スケルチ回路であシ、フリップフロップ(14a)*論
理積回路(t4b)とから構成されている。0りは前記
スケルチ回路a4から出力される再生データスケル壬出
力信号、 aeは前記スケルチ回路+14から出力され
る抽出クロックスケルチ出力信号、aDは前記再生デー
タスケルチ出力信号aつヲ前記抽出りロツクスケル千出
力信号任eにて読み込む1フレームメモリ、 aSは前
記1フレームメモリ(171より読み出された再生デー
タメモリ出力、r19は前記再生データメモリ出力音読
み出す為の内蔵クロック、■は内蔵クロックを発するク
ロック発振器である。
03 is a data frame synchronization signal output from the data frame detection circuit 11z, and Oa is the reproduction data (
61, The extracted clock f''ke is a squelch circuit that squelches OFF in synchronization with the data frame from the reception level drop detection signal flll and the data frame synchronization signal 0, flip-flop (14a) * logical product 0 is a reproduced data squelch output signal outputted from the squelch circuit a4, ae is an extracted clock squelch output signal outputted from the squelch circuit +14, and aD is the reproduced data output signal. The squelch output signal a is read from the above-mentioned extracted lock squelch output signal, aS is the playback data memory output read from the above-mentioned one frame memory (171), and r19 is for reading the sound output from the playback data memory. The built-in clock is a clock oscillator that generates the built-in clock.

第1図における各部の動作波形を第2図に示す。FIG. 2 shows operating waveforms of each part in FIG. 1.

以下動作を説明する。移動体(81が移動中、送信信号
A(3)と送信信号B f41との混合信号を受信する
期間T2からT3における受信信号電力A、  Bの最
大値f pmaxとすれば、移動体が受信する受信信号
電力は第2図に示すような曲線を描くので、閾値”eP
o(≧Pmax)と設定した受信レベル検出回路CIo
の受信レベル低下検出信号は(110)のようになる。
The operation will be explained below. When the mobile body (81) is moving, if the maximum value f pmax of the received signal powers A and B during the period T2 to T3 during which the mobile body (81) receives a mixed signal of the transmitted signal A(3) and the transmitted signal B f41, the mobile body receives Since the received signal power draws a curve as shown in Figure 2, the threshold value "eP"
Reception level detection circuit CIo set as o (≧Pmax)
The received level drop detection signal is as shown in (110).

また、再生データf61は送信信号A +31が(1o
6)。
In addition, the reproduced data f61 has a transmission signal A +31 of (1o
6).

送信信号B T41が(104)のようなタイミングで
ある場合には(106)のようにT2からT3にてデー
タは乱れ、  (107)のようにT2からT3にてク
ロックは乱れる。スケルチ回路+141ではデータフレ
ーム検出回路riZにて、出力されたデータフレーム同
期信号(115)により受信レベル低下検出信号(11
1)klJタイミングした信号を用い、再生データ(6
1及び抽出クロック(71ヲスケルチすることで、フレ
ームに同期した再生データスケルチ出力信号051が(
N5)のように出力されフレームに同期した抽出クロッ
クスケルチ出力信号aeが(N6)のように出力される
。1フレームメモリ(L71へのデータ入力はTo か
らT1まで行なわれ、その後T4からT5で再開される
。T1からT4までの期間は時間T1 に1フレームメ
モリαηへ最後に入力されたある1フレームが1フレー
ムメモリより内蔵発振器出力(119)によりくり返し
読み出される。この様子i([8)に示す。この時画像
処理系の出力は、TOからT1まで送信信号A T31
の信号を出力し、T1からT4まではT1の最終フレー
ム映像が固定され、  T4からT5では送信信号B(
41の信号を出力することになる。
When the transmission signal B T41 has a timing as shown in (104), the data is disturbed from T2 to T3 as shown in (106), and the clock is disturbed from T2 to T3 as shown in (107). In the squelch circuit +141, the data frame detection circuit riZ detects a reception level drop detection signal (11
1) Using the klJ timing signal, reproduce the playback data (6
By squelching 1 and extraction clock (71), the reproduced data squelch output signal 051 synchronized with the frame becomes (
The extracted clock squelch output signal ae synchronized with the frame is output as shown in (N6). Data input to the 1-frame memory (L71) is performed from To to T1, and then restarts from T4 to T5. During the period from T1 to T4, a certain frame that was last input to the 1-frame memory αη at time T1 is One frame memory is read out repeatedly by the built-in oscillator output (119). This situation is shown in i ([8). At this time, the output of the image processing system is the transmission signal A T31 from TO to T1.
From T1 to T4, the final frame image of T1 is fixed, and from T4 to T5, the transmitted signal B (
41 signals will be output.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば2局以上からの混合信
号を受信してもその期間の信号受信を中止し、中止直前
のデータをくり返し読み出すようにし、映像が混合信号
受信直前の映像にて停止するように構成したので、映像
のちらつきや乱れが無くなるという効果がある。
As described above, according to the present invention, even if a mixed signal is received from two or more stations, signal reception for that period is stopped, and the data immediately before the stop is repeatedly read out, so that the image changes to the image immediately before the mixed signal is received. Since the screen is configured to stop at a certain point, it has the effect of eliminating flickering and disturbances in the image.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの発明の一実施例による画像信号受信装置の
ブロック図、第2図は第1図の各部の動作波形図、第3
図は従来の画像信号受信装置のブロック図、第4図は第
3図の各部の動作波形図である0 図中、a[1は受信レベル検出回路、 a21はデータ
フレーム検出回路9口をはスケルチ回路、tiηは1フ
レームメモリ、■はクロック発振器である。 なお9図中同一あるいは相当部分には同一符号して示し
である。
FIG. 1 is a block diagram of an image signal receiving device according to an embodiment of the present invention, FIG. 2 is an operation waveform diagram of each part of FIG. 1, and FIG.
The figure is a block diagram of a conventional image signal receiving device, and FIG. 4 is an operation waveform diagram of each part of FIG. The squelch circuit, tiη is a one-frame memory, and ■ is a clock oscillator. In FIG. 9, the same or corresponding parts are indicated by the same reference numerals.

Claims (1)

【特許請求の範囲】[Claims] 空間的に離れた2局以上の送信局の同一画像信号を移動
体に搭載された1局の受信局が受信する光空間伝送通信
系において、再生データと抽出クロックを出力する光受
信信号再生回路と、光受信レベルがある閾値P_oより
低下した際にスケルチ信号を送出する光受信レベル検出
回路と、前記光受信信号再生回路から出力される再生デ
ータよりデータのフレーム同期信号を検出するデータフ
レーム検出回路と、前記光受信信号再生回路から出力さ
れる抽出クロック、再生データ、前記データフレーム検
出回路から出力されるフレーム同期信号及び前記光受信
レベル検出回路から出力される受信信号スケルチ信号と
から、データフレームに同期した受信レベルが閾値P_
oより低下した場合は再生データ及び抽出クロックの送
出を禁止するスケルチ回路と、画像1フレーム分の容量
を有し、前記、再生データを上記スケルチ回路の出力に
応じて入力するメモリと、光受信信号断時には上記メモ
リに再生データを書込み、光受信信号が断してから光受
信信号が再度入力されるまで上記メモリから記憶データ
を繰返し読み出す読出しクロックを発生する発振器と、
上記メモリ回路の出力データから画像処理を行なう画像
処理系とを備えた画像信号受信装置。
An optical reception signal regeneration circuit that outputs reproduced data and an extracted clock in an optical space transmission communication system in which a single reception station mounted on a mobile body receives the same image signal from two or more spatially separated transmission stations. an optical reception level detection circuit that sends out a squelch signal when the optical reception level drops below a certain threshold P_o; and a data frame detection circuit that detects a data frame synchronization signal from the reproduced data output from the optical reception signal regeneration circuit. data from the extracted clock output from the optical reception signal regeneration circuit, the reproduced data, the frame synchronization signal output from the data frame detection circuit, and the reception signal squelch signal output from the optical reception level detection circuit. The reception level synchronized with the frame is the threshold P_
a squelch circuit that prohibits the transmission of reproduced data and extracted clocks when the output voltage drops below o; a memory having a capacity for one image frame and into which the reproduced data is input in accordance with the output of the squelch circuit; and an optical receiver. an oscillator that generates a read clock that writes reproduced data to the memory when the signal is cut off and repeatedly reads the stored data from the memory after the optical reception signal is cut off until the optical reception signal is input again;
An image signal receiving device comprising an image processing system that performs image processing from output data of the memory circuit.
JP28885487A 1987-11-16 1987-11-16 Picture signal receiver Pending JPH01129688A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28885487A JPH01129688A (en) 1987-11-16 1987-11-16 Picture signal receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28885487A JPH01129688A (en) 1987-11-16 1987-11-16 Picture signal receiver

Publications (1)

Publication Number Publication Date
JPH01129688A true JPH01129688A (en) 1989-05-22

Family

ID=17735607

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28885487A Pending JPH01129688A (en) 1987-11-16 1987-11-16 Picture signal receiver

Country Status (1)

Country Link
JP (1) JPH01129688A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58224142A (en) * 1982-06-22 1983-12-26 Sumitomo Light Metal Ind Ltd Aluminum alloy plate with superior formability and its manufacture
JPS6140299A (en) * 1984-06-11 1986-02-26 シコ−ル ソシエテ イタリア−ナ コルテイコステロイデイ エス・ピ−・エ− Manufacture of 16,17_acetals of pregnane derivative and compounds thereby
JPS62182257A (en) * 1986-02-07 1987-08-10 Sky Alum Co Ltd Manufacture of hard aluminum alloy rolled sheet for forming

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58224142A (en) * 1982-06-22 1983-12-26 Sumitomo Light Metal Ind Ltd Aluminum alloy plate with superior formability and its manufacture
JPS6140299A (en) * 1984-06-11 1986-02-26 シコ−ル ソシエテ イタリア−ナ コルテイコステロイデイ エス・ピ−・エ− Manufacture of 16,17_acetals of pregnane derivative and compounds thereby
JPS62182257A (en) * 1986-02-07 1987-08-10 Sky Alum Co Ltd Manufacture of hard aluminum alloy rolled sheet for forming

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