JPH01128297A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce a defective generating rate by constituting the selected circuit with the switching of a defective selected circuit to a normal selected circuit when the defective selected circuit exists in the plural selected circuits. CONSTITUTION:When a defective memory MI exists at a position shown in a figure, the fuse link of a selector S3 corresponding to a memory cell array MCI to which the defective memory cell belongs is disconnected. Further, the fuse link of a spare selector SR is disconnected. Thus, the selective signal is outputted as S1 S2 S4 SR, the memory cell array MCI to which the defective memory cell MI belongs is jumped off, and a spare memory cell array MCR is selected instead of it. Thus, the defective generating rate can be reduced.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to a serial system consisting of a plurality of selected circuits and a plurality of cascade-connected selectors that sequentially output selection signals to the plurality of selected circuits. - The selector circuit is configured such that each stage selector receives an activation signal from a previous stage selector, is activated by the activation signal, outputs the selection signal, and outputs an activation signal to a subsequent stage selector. The present invention relates to a semiconductor integrated circuit device having a serial selector circuit, and particularly to a semiconductor integrated circuit device provided with means for replacing a defective selected circuit with a normal selected circuit.

<Prior Art> First, the configuration of a conventional semiconductor integrated circuit device will be described in detail using a DRAM as an example.

FIG. 8 is a block diagram of a conventional DRAM.

In the figure, MA' is a memory cell array, RD' is a row decoder, SA' is a sense amplifier, DI is a data holding circuit, and T'1. ..., T'. is an N-channel MOS transistor, IO' is the I10 port, and ss is the MO3) transistor T1 based on the SO signal input.

..., selection signal S'l + that turns on T'o sequentially
..., S'.

n cascade-connected selectors S′1°・
, S′o (column C selector). FIG. 9 shows the configuration of each of the above selectors. In the figure, CK' is a clock signal and R3T is a reset signal.

The data read from the memory cell array MA' to the data holding circuit DH' is transferred to the serial selector circuit ss'.
The selection signals 81, . Also, I1
The data that is input sequentially from port 0 is serial.
Selection signal s'1. output from selector circuit SS'.・
..., s'o, the data is sequentially input and held in the data holding circuit DH', and then written to the memory cell array MA.

<Problems to be Solved by the Invention> The conventional semiconductor integrated circuit device has been described using a DRAM as an example. There is a problem that if a selected circuit exists, the device becomes a defective product. In the case of the conventional DRAM mentioned above, even one bit of defective memory cell M' exists in the memory cell array MA.
If I exists, the DRAM is defective.

The present invention has been made in view of the above conventional problems, and even if a defective selected circuit exists among a plurality of selected circuits,
The purpose of this is to bring the defective selected circuit down to a normal selected one.

<Means for solving the problem> A serial selector circuit consisting of a plurality of selected circuits and a plurality of cascade-connected selectors that sequentially output selection signals to the plurality of selected circuits, in which each stage The selector is a semiconductor integrated circuit having a serial selector circuit configured to receive an activation signal from a previous-stage selector, to be activated by the activation signal, and output the selection signal, as well as to output an activation signal to a subsequent-stage selector. The circuit device is provided with a preliminary selected circuit and a preliminary selector that outputs a selection signal to the preliminary selected circuit when activated by an activation signal, and a fuse link, and by disconnecting the fuse link, a preliminary selector is provided. Providing each selector constituting the serial selector circuit with a switching control circuit that prohibits activation of the selector by an activation signal from the selector and short-circuits the activation signal from the preceding selector to the subsequent selector; The preliminary selector is provided with a fuse link and a switching control circuit that enables activation by an activation signal input from a predetermined selector by disconnecting the fuse link.

Effect> By cutting the fuse link of the selector corresponding to the defective selected circuit, the selector is skipped.

As a result, output of the selection signal to the defective selected circuit is prohibited, and the circuit becomes non-selected. On the other hand, by disconnecting the fuse link of the spare selector, the inactive spare selector is activated. by this,
The preliminary selected circuit whose selection was prohibited is now selected, thereby compensating for the non-selection of the specified defective selected circuit.

<Example> Hereinafter, the present invention will be described in detail based on Examples.

FIG. 2 is a block diagram of a DRAM which is an embodiment of the present invention. FIG. 1 is a block diagram of the serial selector circuit SS in the same DRAM. In FIG. 1, CK is a clock signal and R3T is a reset signal.

In the figure, MA is a memory cell array, MCR is a spare memory cell column included in the memory cell array MA, and R
D is a row decoder, SA is a sense amplifier, DH is a data holding circuit, TI+'...+Tn+TR is an N-channel MOS transistor, and IO is an I10 port. S.S.
is n selectors Sl,...,Sn connected in cascade
and a spare selector SR.

When the fuse links Fl,..., Fo, and FR in each of the selectors Sl,..., So, and sR are all not disconnected, the serial selector circuit SS is
Based on the so signal input, the transistor Tl
,..., a selection signal Sl that sequentially turns on Tn.
+..., sn is output. In this case, the spare selector sR
There is no selection signal output. Each of the above selectors SI+...
, one of the fuse links Fl in Sn, . . . , Fk of Fn and the fuse link F in the preliminary selector S2
When R is disconnected and all other fuse links are disconnected, the serial selector circuit SS
Based on the signal input, the MOS transistor Tl, ”
'+Tk-1+Tk+1,''・,Tn.

Selection signal SI+...+81(
-ItSk+I+...+Sl'l+SR is output. In this case, there is no selection signal output from selector Sk.

When the defective memory cell MI exists at the position shown in FIG. 2, the fuse link F3 of the selector S3 corresponding to the memory cell column MCI to which the defective memory cell belongs is cut. Also, the fuse link FR of the spare selector SR is disconnected. As a result, the selection signal output becomes Sl−+S2→
S4→...→Sn-+SR, defective memory cell M
The memory cell column MCI to which I belongs is skipped, and the spare methyl cell column MCR is selected instead.

In the case of a DRAM that is serially accessed also in the row direction, a spare memory cell row may be provided, and a circuit having the same configuration as the serial selector circuit SS described above may be provided as a row decoder.

Next, a second embodiment will be described.

5 and 5 respectively show the serial selector circuit SS
FIG. 2 is a configuration diagram of a selector si (i=' +.-+ n) and a spare selector 5Rj (j=1.2) that constitute the.

In the figure, CL and CL are clock signals. Also,
MOS) run transistors in Figures 4 and 5 are all N.
channel MOS) transistor.

Fuse links FI+"'+Fn in each of the above selectors SL, . . . , So and spare selectors SR1 and SR2
When FRI and FR2 are all uncleaved,
The serial selector circuit SS sequentially outputs phase-shifted selection signals S11+...+312 based on the SQ signal input.
Output. In this case, there is no selection signal output from the preliminary selectors SRI and SR2.

A time chart at this time is shown in FIG.

One Fk of the fuse links Fl,..., Fn in each of the selectors Sl,..., Sn and the fuse link FRI or FR in the spare selector Sl or SR2.
2 is disconnected and all other fuse links are disconnected, the serial selector circuit SS
Based on the signal input, the selection signal S Il is sequentially phase-shifted.
+ 312+”'+ 5(k-1)I+S(k I)
2+”(k+I)I,”(k+1)21”’+SHI
+Sn2. sR+1 (or S R2+) l S R
+2 (or S R22) is output. In this case, there is no selection signal output from selector Sk and reserve selector 5R2 (or 5RI).

FIG. 7 shows a time chart when the fuse link F2 in the selector S2 and the fuse link FRI in the preliminary selector S2 are disconnected.

<Effects of the Invention> As explained in detail below, according to the present invention, even if a defective selected circuit exists among a plurality of selected circuits, the defective selected circuit can be replaced with a normal selected circuit. This makes it possible to reduce defective rates, improve yields, and reduce costs.

[Brief explanation of the drawing]

Figure 1 is a circuit configuration diagram, Figure 2 is a block diagram, Figure 3 is a block diagram, Figure 4 is a circuit configuration diagram, Figure 5 is a circuit configuration diagram,
FIG. 6 is a time chart, FIG. 7 is a time chart, FIG. 8 is a block diagram, and FIG. 9 is a circuit configuration diagram. Description of symbols MA: memory cell array, MCR: spare memory cell column, MI: defective memory cell, RD: row decoder, SA:
Sense amplifier, DH: data holding circuit, "I +
"' + TQ + TR" channel MO3) transistor, IO: I10 port, SS serial selector circuit, Sl,..., Sn: selector, 5R9SR
I + SR2' spare selector, F] + "'+F
n + FR+FR1+ FR2' fuse link, s
l +”'+ sl +SR: selection signal, 811
+ ”' T Sn2+ SRI++ ”' +5R2
2: Selection signal. Agent: Patent attorney Takeshi Sugiyama (and 1 other person), 9R, Figure 9

Claims (1)

[Claims] 1. A serial selector circuit consisting of a plurality of selected circuits and a plurality of cascade-connected selectors that sequentially output selection signals to the plurality of selected circuits, wherein each stage selector , a serial selector circuit configured to receive an activation signal from a pre-stage selector, be activated by the activation signal, output the selection signal, and output an activation signal to a subsequent-stage selector. A preliminary selected circuit and a preliminary selector that outputs a selection signal to the preliminary selected circuit by being activated by an activation signal are provided, and a fuse link, and when the fuse link is disconnected, a preliminary selector is provided that outputs a selection signal to the preliminary selected circuit. Each selector constituting the serial selector circuit is provided with a switching control circuit that prohibits activation of the selector by the activation signal of the serial selector and short-circuits the activation signal from the preceding selector to the subsequent selector, and a fuse link. and a semiconductor integrated circuit device characterized in that the preliminary selector is provided with a switching control circuit that enables activation by an activation signal input from a predetermined selector by disconnecting the fuse link.