JPH01127034U - - Google Patents

Info

Publication number
JPH01127034U
JPH01127034U JP1988020794U JP2079488U JPH01127034U JP H01127034 U JPH01127034 U JP H01127034U JP 1988020794 U JP1988020794 U JP 1988020794U JP 2079488 U JP2079488 U JP 2079488U JP H01127034 U JPH01127034 U JP H01127034U
Authority
JP
Japan
Prior art keywords
cpu
runaway
storage section
detects
watchdog timer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988020794U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988020794U priority Critical patent/JPH01127034U/ja
Publication of JPH01127034U publication Critical patent/JPH01127034U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Storage Device Security (AREA)
  • Debugging And Monitoring (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の第1の実施例を示した電気回
路図、第2図は本考案の第2の実施例を示した電
気回路図、第3図は第2図の動作を示したタイム
チヤートである。 1…CPU、2…第1の記憶部、3…ウオツチ
ドツグタイマ、4…第2の記憶部、5…リセツト
回路。
Fig. 1 is an electrical circuit diagram showing the first embodiment of the present invention, Fig. 2 is an electrical circuit diagram showing the second embodiment of the invention, and Fig. 3 shows the operation of Fig. 2. It is a time chart. DESCRIPTION OF SYMBOLS 1... CPU, 2... First storage section, 3... Watchdog timer, 4... Second storage section, 5... Reset circuit.

Claims (1)

【実用新案登録請求の範囲】 CPU(中央処理回路)と、 このCPUの処理によつてデータを記憶する第
1の記憶部と、 上記CPUの暴走を検出するウオツチドツグタ
イマと、 このウオツチドツグタイマにより上記CPUの
暴走が検出されたときに第1の記憶部に記憶され
ているデータを記憶する第2の記憶部と、 この第2の記憶部にデータが書き込まれた後に
上記CPUをリセツトするリセツト回路とを具備
することを特徴とする暴走対策回路。
[Scope of Claim for Utility Model Registration] A CPU (central processing circuit), a first storage unit that stores data through processing by the CPU, a watchdog timer that detects runaway of the CPU, and a watchdog timer that detects runaway of the CPU; a second storage section that stores the data stored in the first storage section when the runaway of the CPU is detected by the runaway timer; A runaway prevention circuit comprising a reset circuit for resetting a CPU.
JP1988020794U 1988-02-19 1988-02-19 Pending JPH01127034U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988020794U JPH01127034U (en) 1988-02-19 1988-02-19

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988020794U JPH01127034U (en) 1988-02-19 1988-02-19

Publications (1)

Publication Number Publication Date
JPH01127034U true JPH01127034U (en) 1989-08-30

Family

ID=31237459

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988020794U Pending JPH01127034U (en) 1988-02-19 1988-02-19

Country Status (1)

Country Link
JP (1) JPH01127034U (en)

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