JPH01124044A - Data transmission equipment - Google Patents

Abstract

PURPOSE:To continuously write or read out 1-word or 2-word data without deteriorating responseness by providing the title equipment with a bus request/ gate control means for writing or reading out data consisting of one word or plural words and a bus determining mean for sending bus authorized signals. CONSTITUTION:When a corresponding bus request/gate control means 10 is accessed from each of bus masters 21, 22...,5 a bus request signal is sent to the bus determining means 30. At the time of receiving the bus request signal, the means 30 sends bus authorized signals at a fixed rate in the order of priority. The means 10 controls plural write data gates 11, 12 and plural read data gates 13, 14 for data divided in each word to selectively open the gate and writes or reads out one-word or plural-word data. Consequently, data of one word or more can be continuously written or read out without deteriorating responseness.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention relates to a data transmission device used in, for example, a process control system where a plurality of devices read and write data using a shared memory. In particular, the present invention relates to an improvement of a data transmission device that can read or write 2-word data by asynchronous access without having a protocol.

(Conventional technology) Generally, in various process control systems such as chemical plants, steel plants, etc., it is necessary to perform necessary processing while quickly responding between the main equipment side and each external device. High speed and easy connectivity with external devices are required for titrating time control. The reason for this is that even if the data transmission speed is increased, if the protocol for exchanging data with each external device is complicated, the data transmission speed will eventually decrease.

Therefore, conventionally, the seventh
A common memory (shared memory) system as shown in the figure is being considered. This method uses, for example, a 16-bit common bus 1
A plurality of external devices 21, 22, . . . and the main device 3 are respectively connected to the main device 3.
A common memory 4 and a device basic unit 5 are provided which are divided and allocated to transmission areas of + 22 + .
When each external device 21 + 22, ... obtains the transmission right, it broadcasts data in its own transmission area to other stations, and the other stations transmit the data to areas similar to the transmission area of their own station. This method stores the data in As a result, the connected external devices 2++22. ... will all have the same memory, and as long as it recognizes the divided data map, it will be possible to easily communicate data with other external devices without having to have a complicated protocol. can.

However, in the above-described common memory system, the data handled by the common memory 4 is guaranteed only in units of words (data bus length).

It consists of the inside of the main device 3 and the external devices 21, 2□11. This is because access to the common memory 4 is asynchronous because there is no protocol between the two devices, and in many cases, an action has already been taken by another device when the transmission of one word of data is completed. In addition, external equipment 21+ 22 +...
- If the shared bus 1 is freely monopolized by outputting a lock command etc. from the main unit basic unit 5, there is a risk that the main device basic unit 5 will not be able to read or write data from the common memory 4 in time. be. Therefore, the main device basic section 5 or each external device 21, 22. ...etc.2
Word data can be written to or read from the common memory 4, but in order to avoid reading out word data that has changed over time, each word data is read twice with an interval between the previous and current data. By using the data while checking the consistency, or by setting flag 1'' when writing each word data to the common memory 4 and setting flag 0'' when reading that word data, that data can be saved. The data is used by each external device 21, 22+, etc. while ensuring the validity of the data.

(Problem to be Solved by the Invention) Therefore, in the data transmission device as described above, when accessing the common memory 4 asynchronously without a protocol, the two words written to the common memory 4 inside the main transmission device 3 External device 21 while checking the validity of the data.
+ 22 , . . . , etc., and as a result, the responsiveness of the data becomes extremely poor, making it difficult to apply it to, for example, a process control system that performs real-time control.

The present invention has been made in view of the above-mentioned circumstances, and is capable of reliably accessing a common memory asynchronously without a protocol, and continuously writing or reading 1-word or 2-word data without deteriorating responsiveness. The purpose is to provide a data transmission device that can.

[Structure of the Invention] (Means for Solving the Problems) A data transmission device according to the present invention provides data transmission in which a plurality of bus masters write data to or read data from a common memory using a common bus using an asynchronous access method. The device is provided for each bus master and outputs a bus request signal based on an access from the bus master, and selectively operates a plurality of write data gates and read data gates in units of words in response to a bus permission signal and a word number designation signal. bus request/gate control means for writing one word or multiple words of data into the common memory or reading one word or multiple words of data from the common memory through gate control;
One or a plurality of bus request signals are commonly provided in the gate control means and are configured to permit access at a fixed rate in priority order when a bus request signal is received from the bus request/gate control means based on the number of words designation signal. and bus determining means for sending out the bus permission signal.

(Function) Accordingly, in the present invention, by using the above means, when access is received from each bus master, a bus request signal is sent from the bus request/gate control means corresponding to the bus master to the bus determining means. At this time, the bus determining means determines the access cycle time in advance from the throughput considering the transmission speed and the number of bus masters, etc., and when it receives the bus request signal from the bus request/gate control means, it latches it and assigns a certain number of signals in order of priority. It is determined whether there is a bus request from the bus master based on the ratio, and if there is a bus request, a bus permission signal is sent out. Here, when the bus request/gate control means receives the bus permission signal, it selectively controls the gate opening of a plurality of write data gates and a plurality of read data gates in word units to write or write data of one word or a plurality of words. It is something to read out.

(Example) Hereinafter, an example of the apparatus of the present invention will be described with reference to the drawings. FIG. 1 is a diagram schematically showing the configuration of the device of the present invention, which has a configuration in which an additional circuit 6 is newly added to the conventional common memory system (FIG. 7). This additional circuit 6 includes external devices 21+22. . . . and the main unit basic unit 5, that is, a bus request/gate control means having an interface function for each bus master, and further a bus determination means for determining a bus based on a bus request from the bus request/gate control means. is provided. 7 is a local bus.

This bus request/gate control means 10 is a part that performs signal conversion between the local bus 7 and the common bus 1 as shown in FIG. 2, and makes a bus request to the bus determination means (FIG. 3). Specifically, each bus master 21, 2°,
..., a write data gate 11 that holds local write data for 2 words between the data line 7-1 of the local bus 7 every 5 and the data line 1-1 of the common bus 1.
12 and read data gates 13 and 14 which hold data for two words during reading are provided, and an address gate 15 is similarly provided between address lines 7-2 and 1-2. The input/output bus of each gate 11-14 has a 16-bit configuration corresponding to one word unit.

16 and 17 are a bus request circuit and a common memory control circuit provided between the control line of the local bus 7 and the control lines 1 to 3 of the common bus 1; of these, the bus request circuit 16 receives control signals from the local bus 7;

In other words, the common memory select signal 7-3. Read signal 7
-4. If it is determined that it is a common memory access from the write signal 7-5 and word switching signal 7-6, etc., the bus request signal 1
8-1 to the bus determining means shown in FIG. It has a function of creating normal memory control signals such as write/read and output enable and sending them to control lines 1-3.

19 is a gate control circuit which operates when receiving the bus permission signal 18-2 from the bus determining means 30 and outputs a control signal 20 in order to control the necessary gates 11 to 15; 21 is a gate control circuit that accesses the common memory 4; This is a response circuit that returns a response signal, that is, an acknowledge signal 7-7, to the bus master when the operation is completed.

Next, the bus determining means 30 determines whether each bus master 21.2
□, ..., common to 5, and as shown in Figure 3, common memory access is performed at a certain rate for priority classes in response to bus requests sent from bus request/gate control means-1. Specifically, it has a request latch circuit 31 that latches the bus request signal 18-1 at regular intervals, and prioritizes the bus request data latched by this request latch circuit 31. Based on the priority encoder 32 for taking out the bus request data taken out from the encoder 32 and the word switching signal 7-6 indicating switching between 1 word and 2 words, the bus request/gate control means of each bus master is sent to the bus request/gate control means of each bus master. A selector circuit 33 and the like for returning the bus permission signal 18-2 is provided.

Note that the bus permission signal 18-2 is sent once when it is one word;
If it is 2 words, it will be returned twice. 34 is a word counter that counts the basic clock and outputs a signal indicating the number of words;
Reference numeral 35 designates a request set/reset circuit which outputs the bus request data latched by the request latch circuit 31 according to the number of words in the word counter 34 and resets the lie/reset state of the bus request data after the bus permission signal is returned. be.

Next, the apparatus configured as described above will be explained in the order of throughput allocation, write operation, and read operation.

(1) Throughput allocation In this type of device, each bus master 21, 22, .
..., 5 uses common bus 1, this common bus 1
It is necessary to consider the throughput, or data processing capacity. Therefore, when allocating the throughput of the common bus 1 to each bus master, the transmission speed becomes an important requirement. Now, for a transmission device, if the transmission speed is M and the bit length of common bus 1 is L bits, a bus throughput of more than M/L (M words/sec) is required. When the throughput of bus 1 is A (M words/sec) and the number of bus masters is N, the following relationship must hold: (M/L) < (A/N). This means that in the bus determining means 30, N< I (
A-L)/M It is necessary to equally allocate the common bus 1 to one bus master. To this end, the bus determining means 30 can time-share the common bus 1 in (N/A) time slots and give each bus master the right to access the common memory 4 once in turn. In particular, when two words are accessed, the access time for one bus master increases, and in the worst case, if all bus masters access two words, the access right circulation time doubles; If it is set to 2 words, the average throughput will not change. Moreover, access rights can be circulated at a sufficiently high speed while skipping the time slots of bus masters that do not access.

(2) Write operation When the common memory select signal, write signal, 2-word switching signal, and address data as shown in FIG. 4 are input from the bus master, the bus request circuit 16 of the bus request/gate control means It is determined that the bus has been selected by the relevant bus master, and this determination result is sent to the gate control circuit 19.
to communicate.

Here, the gate control circuit 19 outputs a data latch signal to cause the write data gate 11 to latch the write data, and the response circuit 21 returns an acknowledge signal to the bus master to complete the first write operation.

At this time, since the bus request circuit 16 receives the 2-word switching signal, it remembers that this is the first access at this stage. Subsequently, when the second write signal comes, the bus request circuit 16 outputs the bus request signal 18-1.

Here, the bus determining means 30 performs the following operation based on the timing shown in FIG. For convenience, FIG. 5 shows that bus master "1" (for example, external device 21) accesses 2 words, bus master "2" (for example, external device 22) accesses no requests, and bus master "3" (for example, external device 23) accesses 1 word.
Make it a word request. However, these bus masters rlJ
r2J.

As shown in FIG. 5, when the request set/reset circuit 35 sends out a request latch signal based on the word switching signal 7-6 at the beginning of the cycle of the access right, the request latch circuit 31 Latch the request signal 18-1. This latched bus request signal is sent to the priority encoder 32 and assigned to a predetermined bus master "1".

Requests are issued in the order of "2", . . . . here,
Based on the output of the encoder 32, the word switching signal, the output of the word counter 34, etc., the selector circuit 33 grants bus permission for 2 words to the bus request/gate control means 10 corresponding to the bus master "1" that made the bus request. Signal 18-2
At the same time as sending out the word number 2 of the word counter 34, the request set reset circuit 35 resets the latch of the bus request signal of the request latch circuit 31. Note that in FIG. 5, since there is no request from bus master "2", the request from bus master "3" is subsequently sent to the priority encoder 32 and similar processing is performed.

In the bus request gate control means, two
When the bus request circuit 16 receives the word bus permission signal 18-2, a control signal is sent from the common memory control circuit 17 to the control line 1-3 of the common memory 4.

Further, the gate control circuit 19 sends out a gate control signal 20 based on the first bus permission signal 18-2, and sends out a gate control signal 20 to the write data gate 11 and the address gate 15.
and then the second bus permission signal 1 that is sent.
8-2, the write data gate 12 and address gate 15 are opened to perform the process of writing two words of data into the common memory 4 in succession.

(3) Read operation Next, the read operation is almost the same as the write operation, but the difference is that when the bus request circuit 16 receives the first access from the bus master side, the common memory control circuit 1
When the bus request signal 18-1 is outputted via the bus request signal 18-1 through the bus determining means 30, the control signal 20 is outputted from the gate control circuit 19 in accordance with the next access, and the read data gate 13. 1
4, the data in the common memory 4 is read twice in succession and latched into the read data gates 13 and 14.

That is, the gate control circuit 19 sends the contents of the read data gate 13 to the local data line 7-1, and also sends an acknowledge signal 7-7 to the bus master side via the response circuit 21 to complete the first read operation. do.

During the second access, the gate control circuit 19 opens the read data gate 15 and the response circuit 21 returns an acknowledge signal to the bus master, thereby completing the read operation.

The above series of operations has been described for write/read operations of two words, but in the case of one word, it can be considered that only the operation when accessing the common memory 4 among them occurs.

It should be noted that the present invention is not limited to the above-mentioned embodiments, but can be applied to all asynchronous access systems that share the common memory 4.

Further, if the bus throughput is sufficient, it is possible to guarantee continuous data up to N words. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

[Effects of the Invention] As detailed above, according to the present invention, the common memory can be reliably accessed asynchronously without a protocol, and one word or two data can be accessed without deterioration of responsiveness.
A data transmission device capable of continuously writing or reading data of one word or more can be provided.

[Brief explanation of the drawing]

1 to 6 are shown to explain an embodiment of the data transmission device according to the present invention, FIG. 1 is a schematic configuration diagram of the device of the present invention, and FIG. Specific configuration diagram of bus request/gate control means, Part 3
The figure shows a specific configuration diagram of the bus determination means, FIG. 4 is a timing diagram of the write operation of the bus request/gate control means, FIG. 5 is an operation timing diagram of the bus determination means, and FIG. 6 is a bus request/gate control diagram. FIG. 7 is a timing diagram of the read operation of the means, and is a schematic configuration diagram of the device for explaining the conventional common memory method. 1...Common bus, 2. ．． 22. ... External device, 3... Main device, 4... Common memory, 5...
Main unit basic section, 6... Additional circuit, 1.0-... Bus request/gate control means, 11.12... Write data gate, 13° 14... Read data gate, 15.
... Address gate, 16... Bus request circuit, 17.
. . . Common memory control circuit,] 9 . . . Gate control circuit, -1" - . . Bus determining means, 31
...Request latch circuit, 32...Priority encoder, 33...Selector circuit, 34...Word counter, 35...Request set/reset circuit.

Claims (1)

[Scope of Claims] A data transmission device in which a plurality of bus masters use a common bus to write data to or read data from a common memory using an asynchronous access method, wherein the data transmission device is provided for each bus master and reads data from a common memory based on access from the bus master. Outputs a request signal and selectively gates multiple write data gates and read data gates in units of words in response to a bus permission signal and a word count designation signal to write one word or multiple words of data to the common memory. Or a bus request to read one word or multiple words of data from common memory.
The gate control means and the number of words specified are commonly provided to these bus request/gate control means and are used to permit access at a fixed rate in priority order when a bus request signal is received from the bus request/gate control means. A data transmission device comprising: bus determining means for transmitting one or more of the bus permission signals based on a signal.