JPH01122229A - Supervisory circuit for out-of-synchronism of random number - Google Patents

Abstract

PURPOSE:To automatically supervisory the out-of-synchronism random numbers by certainly generating a frame check sequence error in case of the out-of- synchronism of the random numbers in a ciphering mechanism of a communication line. CONSTITUTION:A random number out-of-synchronism supervisory circuit consists of a HDLC(high level data like control) input control circuit 10, a FCS extracting circuit 11 which extracts only a FCS(frame check sequence) part from the input of HDLC, a HDLC output control circuit 12 which outputs the output of HDLC, a FCS switching circuit 13 which switches recalculated FCS to inputted FCS and transmits this FCS, and a microcomputer circuit 14 which controls circuits 10-13 and ciphers and deciphers an input data part. The monitor circuit stores FCS at the time of reception of unciphered data and ciphers the data part and adds stored FCS as FCS of ciphered data and ciphered data reception and deciphers ciphered data at the time of reception of this data to add this data as FCS of unciphered data.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a random number synchronization monitoring circuit for a cryptographic machine used in a communication line, and is particularly applicable to a field where the validity of data content in a communication line using HDLC procedures is required. The present invention relates to a suitable random number desynchronization monitoring circuit.

[Conventional technology]

Conventional high-level data link control (HDLC) procedure communication control simply uses a general-purpose LSI as described in JP-A-60-102038;
When the data part in the frame of the DLC procedure is encrypted or decrypted, FC is applied to the encrypted or decrypted data.
S (frame check sequence) was recalculated and sent to the line. Therefore, no consideration was given to the issue of erroneous data being exchanged due to random number synchronization errors.

[Problem that the invention seeks to solve]

This is because the above-mentioned conventional technology is a method of recalculating a new KPO3 for encrypted or decrypted data.

Even if the cryptographic agency loses synchronization of random numbers and cannot reproduce the correct data, the FCS is determined to be correct, resulting in incorrect data being exchanged.

The object of the present invention is to provide a random number out-of-synchronization monitoring circuit that detects when correct data cannot be reproduced due to out-of-synchronization of random numbers in a cryptographic institution, and monitors and controls the transmission of incorrect data to a terminal device or exchange facility. is to provide.

[Means for solving the problem] The above purpose is to use HDLC (high level data link control)
Flags, addresses, commands, etc. in received data having the frame format of the HD LC procedure, in a cryptographic machine inserted to conceal non-encrypted data passing through a communication line between terminal devices or exchanges, etc. that have the HD LC procedure. An HDLC input control circuit that can distinguish between the data part and FCS, an FCS extraction circuit that extracts only the FCS from the data, and a button that extracts the outputs of the HDLC input control circuit and FCS extraction circuit and if the data part is non-encrypted data. is a microcomputer circuit that performs encryption using random numbers, etc., and decrypts it using random numbers, etc. if the data part is encrypted data, and the previously received flag, address, command, and microcomputer circuit.
Each data is transmitted in the order of encrypted data or non-encrypted data after encrypted or decrypted by the micro combinator circuit, and FCS is recalculated for new data after encrypted or decrypted by the micro combinator circuit. HDLC that transmits the recalculated FSC next to the encrypted data or non-encrypted data.
By providing an output control circuit and an FCS switching circuit that switches and transmits the FCS extracted from the FCS extracting circuit instead of the recalculated Fe12, random numbers can be monitored for synchronization deviation of random numbers from FCS error K. This is achieved by an out-of-sync monitoring circuit.

[Effect]

The random number synchronization monitoring circuit stores the FCS when unencrypted data is received, encrypts the data part using random numbers, etc., adds the stored FCS as the FCS of the encrypted data, and FCS when received
After decoding the data part using random numbers, etc., the above memorized FCS is added as the FCS of the unencrypted data, so that if the data part becomes incorrect data due to a synchronization error of the random numbers, the terminal Since the system operates so as to always generate an FCS error and stop data exchange between devices, exchanges, etc., there is no possibility of erroneous data exchange when random numbers are out of synchronization.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 to 4.

FIG. 2 is a schematic configuration diagram of a switching network having an HDLC procedure, showing an embodiment of the random number desynchronization monitoring circuit according to the present invention. In FIG. 2, reference numerals 1 and 2 represent terminal devices or exchanges that communicate based on HDLC (high level data link control) procedures. Encryptors 100 and 200 are inserted to conceal unencrypted data passing through the communication line between the terminals or the exchanges 1 and 2, and encrypt and decrypt the data portion. Reference numeral 3 designates an encryption unit that encrypts the data portion of the encryption machine 100, and 4 designates a decryption unit that also decrypts the data portion. 5 is cipher machine 2
00 is a data encryption section, and 6 is a data decryption section. 7.8 is a modem and 9 is a communication line.

FIG. 1 shows an embodiment of the random number synchronization monitoring circuit according to the present invention.
5 and a circuit configuration diagram of decoding units 4 and 6. FIG. In FIG. 1, 10 is an HDLC input control circuit that controls the HDLC input, 11 is an FCS extraction circuit that extracts only the FCS part from the HDLC input, 12 is an HDLC output control circuit that controls the HDLC output, and - boat fishing. HDLC
The input control circuit 10 and the HDLC output control circuit 12 are constructed from a general-purpose one-chip LSI. 13 is the entered FC
F to switch and send S instead of recalculated FCS
CS switching circuit, 14 is HDLC input control circuit io and FC
S extraction circuit 11 and HDI, C output control circuit 12 and F
This is a microcomputer circuit that controls each of the CS switching circuits 13 and encrypts and decrypts the input data portion.

FIG. 3 shows the encryption unit 3 of the encryption machines 100 and 200 in FIG.
．． 50 functional diagram. In FIG. 3, when non-encrypted data is input from the terminal device or switch 1.2 of FIG. 2 to the encryption unit 3.6 of the encryption machine 100.200, encrypted data is output. Figure 4 shows the encryption machine 100 in Figure 2.
, 200 is a functional diagram of the decoding unit 4.5 of . In FIG. 4, when encrypted data is input to the decryption units 4 and 5 of the encryption machine Zoo 200 from the modem devices 7 and 8 connected to the communication line in FIG. shows.

Next, the operation of the random number synchronization monitoring circuit with the configuration and functions shown in Figures 1 to 4 will be explained using terminal equipment, switching equipment, etc.
When data is transferred from the cipher 100 to the exchange 2 via the communication line 9, and the random numbers are out of synchronization between the cryptographic machines 100 and 200 due to a mistake in the rules that are the source of the random numbers or a malfunction of the microcomputer circuit 14, etc. I will explain about it.

The data currently transmitted from the terminal device or exchange 1 having the HDLC procedure is sent to the HD of the encryption unit 3 of the encryption machine 100.
It is input to the LC input control circuit 10 and the FCS extraction circuit 11. Then, the input data is separated by the IDLC input control circuit 10 into flags, addresses, commands, and non-encrypted data in data having a frame format of the HDLC procedure, and is input to the microcomputer circuit 14.

Furthermore, the FCS of the input data is determined by the FCS extraction circuit 12.
is extracted and inputted to the microcomputer circuit 14. The microcomputer circuit 14 encrypts only the input non-encrypted data using random numbers, and
Flags, addresses, and commands of data received earlier to the DLC output control circuit 12.

and output each data in the order of encrypted encrypted data. Then, the HDLC output control circuit 12 outputs the data in the order in which it was input, and outputs the recalculated FCS at the end of transmitting the final data. At this time, the microcomputer circuit 14 operates the FCS switching circuit 13 to output the FCS extracted by the FCS extraction circuit 11 instead of the recalculated FCS.

As described above, the data output from the encryption unit of the encryption machine 100 is transferred to the modem device 71 communication line 9. The signal passes through the modulation/demodulation device 8 and is input to the HDLC input control circuit 10 and FCS extraction circuit 11 of the decoding section 5 of the encryption machine 200. The input data is then classified into flags, addresses, commands, and coded data by the HDLC input control circuit 10 and input to the microcomputer circuit 14. Further, the FCS of the input data is extracted by the FCS extraction circuit 12,
It is input to the microcomputer circuit 14. The microcomputer circuit 14 decrypts only the input encrypted data using random numbers, and the HDLC output control circuit 1
Each data is output to 2 in the order of the flag, address, command, o, and decrypted non-encrypted data that were received first. Then, the HDLC control circuit 12 outputs the input busy data, and outputs the final data at the end of transmission.

Output the recalculated FCS. At this time, the microcomputer circuit 14 operates the FCS switching circuit 13.

Then, the FCS extracted by the extraction circuit 11 is output in place of the recalculated Fe12. The data outputted from the decryption unit 5 of the encryption machine 200 is inputted to the terminal device or exchange 2, etc. as described above. However, in this operation example, the random numbers are out of synchronization 1 between the encryption machines 100 and 200, so the non-encrypted data decrypted above is incorrect in content with the non-encrypted data sent from the IK such as the terminal device or exchange. ing. However, since both FCSs are the same, an FCS error occurs in the terminal device or exchange 2, and the input non-encrypted data is discarded at the terminal device or exchange 2. Therefore, according to this embodiment, data is not exchanged when the random numbers are out of synchronization and the data is incorrect.

〔Effect of the invention〕

According to the present invention, when the cryptographic authority of one communication line is out of synchronization of random numbers, the system operates in such a way that an FCS error is always generated, so that it is possible to automatically monitor the out of synchronization of random numbers.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an encryption section and a decryption section of a cryptographic machine showing an embodiment of a random number synchronization monitoring circuit according to the present invention;
Figure 2 is the same (schematic configuration diagram of an exchange network with HDLC procedure, Figure 3 is a functional diagram of the encryption unit of the cryptographic machine in Figure 2,
The figure is a functional diagram of the decryption section of the encryption machine shown in FIG. 2. 1.2...Terminal equipment or switchboard, etc. 100, 200... Encryption machine, 3.6... Encryption unit. 4.5...Decoding unit, 7,8...Modulation/demodulation device. 9...Communication line. lO...HDLC input control circuit. 11...FCS extraction circuit. 12...HDLC output control circuit. , 13...FCS switching circuit. 14...Microcomputer circuit.

Claims (1)

[Claims] 1. In an encryption machine inserted to conceal non-encrypted data passing through a communication line between terminal devices or exchanges having an HDLC procedure, flags and addresses in received data having a frame format of the HDLC procedure, An HDLC input control circuit that can distinguish between commands, data parts, and FCS, and an F that extracts only the FCS from the above data.
The outputs of the CS extraction circuit, the HDLC input control circuit, and the FCS extraction circuit are extracted, and if the data section is non-encrypted data, it is encrypted using random numbers, etc., and when the data section is encrypted data, it is encrypted using random numbers. etc., the previously received flag, address, command, and encrypted data or non-encrypted data after being encrypted or decrypted by the microcomputer circuit. an HDLC output control circuit that recalculates an FCS for new data that has been encrypted or decrypted in a microcomputer circuit and transmits the recalculated FCS next to the encrypted data or non-encrypted data; Random number synchronization shift monitoring characterized in that random number synchronization shift is monitored by FCS error by providing an FCS switching circuit that switches and transmits the FCS extracted from the extraction circuit instead of the recalculated FCS. circuit.