JPH01122176A - Photo-diode - Google Patents

Photo-diode

Info

Publication number
JPH01122176A
JPH01122176A JP62279675A JP27967587A JPH01122176A JP H01122176 A JPH01122176 A JP H01122176A JP 62279675 A JP62279675 A JP 62279675A JP 27967587 A JP27967587 A JP 27967587A JP H01122176 A JPH01122176 A JP H01122176A
Authority
JP
Japan
Prior art keywords
layer
type
depletion layer
light
junction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62279675A
Other languages
Japanese (ja)
Inventor
Yoshinari Enomoto
良成 榎本
Yoshio Tsuruta
鶴田 芳雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP62279675A priority Critical patent/JPH01122176A/en
Publication of JPH01122176A publication Critical patent/JPH01122176A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To eliminate free carrier absorption and photoelectric conversion loss due to the annihilation, etc., of electrons and holes generated by lowering the impurity concentration of another conductivity type layer to a proper value in relation to the position of a junction and spreading a depletion layer into the whole light-receiving region in an impurity introducing layer. CONSTITUTION:A p-type diffusion layer 21 and a high-concentration p<+> layer 22 which is connected to the p-type diffusion layer 21 and brought into ohmic- contact with an aluminum wiring 4 are formed to an n-type silicon substrate 1, and the surface is coated with a transparent insulating film 5. The p-type layer 21 is shaped in impurity concentration and depth where a depletion layer is formed extending over the whole light-receiving region. Consequently, the depletion layer 3 is shaped into the whole light-receiving surface region in the p-type layer 21 when a reverse bias is applied to a p-n junction between the n-type semiconductor element assembly 1 and the p-type layer 21. Accordingly, incident light is not absorbed to the p-type layer 21 before it reaches the depletion layer 3, thus minimally inhibiting free carrier absorption and photoelectric conversion loss due to the annihilation of electron-hole pairs.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体素体内のp−n接合に逆バイアスをか
けることによって生ずる空乏層への光の入射により生ず
る光電流によって光電変換するフォトダイオードに関す
る。
Detailed Description of the Invention [Industrial Application Field] The present invention relates to a photovoltaic device that performs photoelectric conversion using a photocurrent generated by the incidence of light into a depletion layer created by applying a reverse bias to a p-n junction in a semiconductor element. Regarding diodes.

〔従来の技術〕[Conventional technology]

従来この種のフォトダイオードとしては第2図(Ml〜
(0)に示した構造がよく知られている。(a)はフォ
トダイオードの平面図、(bl、(C1はそれぞれ(a
)のc−c’線、D−D’線に沿うた矢視断面図である
Conventionally, this type of photodiode is shown in Figure 2 (Ml~
The structure shown in (0) is well known. (a) is a plan view of the photodiode, (bl and (C1) are respectively (a
) is a cross-sectional view taken along line c-c' and line DD'.

図において、n形シリコン基板1に高濃度p゛層2を拡
散させて形成したp゛−n接合によって空乏層3が生じ
ているところを示している。p膨拡散層2が高濃度p+
層になっているのは、通常、工数低減のためMO3IC
のpチャネルソース・ドレイン形成工程などの浅い拡散
層の形成工程を利用して形成するためであり、また浅い
拡散層形成工程を利用するのは、空乏層により多くの光
をとり入れるためである。アルミニウム配置4は、p−
n接合に逆バイアスをかけたり、光電流をとり出したり
するための電極で、高濃度p゛層2にオーム性接触して
いる。上面には透明絶縁膜5が被覆されている。
The figure shows a depletion layer 3 created by a p'-n junction formed by diffusing a highly doped p' layer 2 into an n-type silicon substrate 1. The p-swelling diffusion layer 2 has a high concentration of p+
The layers are usually MO3IC to reduce man-hours.
This is because it is formed using a shallow diffusion layer formation process such as the p channel source/drain formation process, and the reason why the shallow diffusion layer formation process is used is to introduce more light into the depletion layer. Aluminum arrangement 4 is p-
This is an electrode for applying a reverse bias to the n-junction and extracting photocurrent, and is in ohmic contact with the high concentration p' layer 2. A transparent insulating film 5 is coated on the upper surface.

n形シリコン基板1の不純物濃度を1.4×10IS/
−1高温度p゛層2の不純物濃度を1.4 X 10”
/−として、この両扉画形層間に4逆バイアス5vを印
加すると、n形シリコン基板1中に幅dg−2,4−の
空乏層3が発生する。ここに光6が入射すると、電子・
正孔対を発生し、光電流が流れる。
The impurity concentration of the n-type silicon substrate 1 is set to 1.4×10IS/
-1 Impurity concentration of high temperature p layer 2 is 1.4 x 10"
/-, and when a 4 reverse bias voltage of 5V is applied between the two gate-shaped layers, a depletion layer 3 with a width dg-2, 4- is generated in the n-type silicon substrate 1. When light 6 enters here, electrons and
Hole pairs are generated and photocurrent flows.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

ところがこの構造の場合、次のような問題点かった。す
なわち、第2図ta+において通常高濃度p′″[2の
面積は空乏層3の基板1上面への露出面積よりもはるか
に大きく、この高濃度p゛層2に吸収された光の一部は
フリーキャリア吸収され熱となってしまい、光電流とな
らない、残りの光は高濃度99層2内で電子・正孔対を
発生するが、そのうちの一部はすぐに消滅して空乏層3
まで到達せずやはり光電流とならない、さらに高濃度9
0層2の接合深さを1−とすると、特に波長500n−
以下の短波長光は、高濃度24層2内でほとんど吸収さ
れてしまう0以上のような損失は光電変換効率を著しく
低下させる。
However, this structure had the following problems. That is, in ta+ of FIG. 2, the area of the normally highly doped p'''[2 is much larger than the area of the depletion layer 3 exposed to the upper surface of the substrate 1, and a portion of the light absorbed by the highly doped p' layer 2 is is absorbed by free carriers and becomes heat, and does not become a photocurrent.The remaining light generates electron-hole pairs in the highly concentrated 99 layer 2, but some of them quickly disappear and form a depletion layer 3.
At even higher concentration 9, the photocurrent does not reach 9
If the junction depth of 0 layer 2 is 1-, especially at a wavelength of 500n-
The following short wavelength light is almost absorbed within the high concentration layer 2, and a loss of 0 or more significantly reduces the photoelectric conversion efficiency.

本発明の目的は、上述のような欠点を除き、波長500
nm以下の短波長光を含む入射光のフリーキャリア吸収
を最小限に減らし、発生した電子・正孔対を光電流とし
て最大限有効に利用できるようにするフォトダイオード
を提供することにある。
The object of the present invention is to eliminate the above-mentioned drawbacks and to
It is an object of the present invention to provide a photodiode which can reduce free carrier absorption of incident light including short wavelength light of nm or less to a minimum and make maximum effective use of generated electron-hole pairs as photocurrent.

〔問題点を解決するための手段〕[Means for solving problems]

上記の目的を達成するこめに、本発明は、一導電形の半
導体素体の受光面側に形成された他導電形の層との間の
p−n接合に逆バイアスを印加して空乏層を生成させ、
その空乏層への光の入射により光電流を生じさせるフォ
トダイオードにおいて、他導電形の層が受光域全域にわ
たって空乏層が生ずるような不純物濃度および深さを有
するものとする。
In order to achieve the above object, the present invention applies a reverse bias to a p-n junction between a layer of another conductivity type formed on the light-receiving surface side of a semiconductor element of one conductivity type to create a depletion layer. generate,
In a photodiode that generates a photocurrent by the incidence of light into its depletion layer, the layer of the other conductivity type has an impurity concentration and depth such that a depletion layer is formed over the entire light-receiving region.

〔作用〕[Effect]

一導電形の半導体素体と他導電形の層との間のpn接合
に逆バイアス印加時に他導電形の層の受光面全域に空乏
層が生ずることによって入射光は空乏層に達する前に他
導電形の層に吸収されることがなく、フリーキャリア吸
収や電子・正孔対の消滅による光電変換損失が最小限に
押さえられる。
When a reverse bias is applied to the pn junction between the semiconductor element of one conductivity type and the layer of the other conductivity type, a depletion layer is generated over the entire light-receiving surface of the layer of the other conductivity type. It is not absorbed by conductive layers, and photoelectric conversion losses due to free carrier absorption and annihilation of electron-hole pairs are kept to a minimum.

さらに、空乏層容量が低下して電子・正孔生成効率が増
加する。
Furthermore, the depletion layer capacity decreases and the electron/hole generation efficiency increases.

〔実施例〕〔Example〕

第1図tar〜(C1は本発明の一実施例を第2図と共
通の部分に同一の符号を付して示し、図(a)はフォト
ダイオードの平面図、図(b)、(0)はそれぞれ図1
mlのA−A″線、B−8’線に沿った矢視断面図であ
る。
Figure 1 (C1) shows an embodiment of the present invention with the same reference numerals attached to parts common to Figure 2, Figure (a) is a plan view of the photodiode, Figure (b), (0 ) are shown in Figure 1, respectively.
ml is a cross-sectional view taken along lines A-A'' and B-8'.

不純物濃度ND/−のn形シリコン基板lに不純物濃度
NA/cd、接合深さ1nのp膨拡散層21およびp形
拡散N21に接続してアルミニウム配線4にオーム性接
触させるための高濃度p″″Ji22を形成する。第2
図と同様、表面は透明絶縁膜5で覆われている。
An n-type silicon substrate l with an impurity concentration ND/- has an impurity concentration NA/cd, a p-swelled diffusion layer 21 with a junction depth of 1n, and a high-concentration p layer for connecting to the p-type diffusion N21 and making ohmic contact with the aluminum wiring 4. ""Ji22 is formed. Second
As in the figure, the surface is covered with a transparent insulating film 5.

階段接合近似において不純物濃度N勤(3−”)。Impurity concentration N(3-'') in the step junction approximation.

N a (cm−”)のN形半導体とP形半導体の間に
逆バイアスをVい(V)を印加したときの空乏層幅x4
(1)は、 で表される。ただし、6sはStの比誘電率で12゜6
oは真空の誘電率で8.85 X 10−目F/am、
qは電子の電荷で1.6 XIO” Cである。V41
は拡散電位で次の式で表される。
Depletion layer width x4 when a reverse bias (V) is applied between an N-type semiconductor and a P-type semiconductor of Na (cm-”)
(1) is expressed as. However, 6s is the relative dielectric constant of St, which is 12°6
o is the dielectric constant of vacuum, 8.85 x 10-th F/am,
q is the electron charge and is 1.6 XIO”C.V41
is the diffusion potential and is expressed by the following formula.

ただし、kはボルツマン定数、Tは絶対温度+niは真
性キャリア密度である。ここでND−1,4X10” 
/−として、逆バイアス5■を印加したときにp膨拡散
層21の濃度NAを変えていくと第1表に示すような空
乏層幅X、になる。
However, k is the Boltzmann constant, T is the absolute temperature + ni is the intrinsic carrier density. Here ND-1,4X10”
/-, and when the concentration NA of the p-swell diffusion layer 21 is changed when a reverse bias of 5 .mu. is applied, the depletion layer width X becomes as shown in Table 1.

第1表 第3図は第1表を図示したものである。従って、x、−
3,3tnaの1/2の幅dt、1.7−の空乏層が生
じ、深さ1−のpi21はすべて空乏層となる。
Table 1, Figure 3 illustrates Table 1. Therefore, x, −
A depletion layer with a width dt of 1/2 of 3.3tna and a depth of 1.7- is generated, and the entire pi21 with a depth of 1- becomes a depletion layer.

但し、高濃度20層22の回りのみは第1図(al、 
+1lt)に示すように基板1側に幅d、−2,4μの
空乏層が生じる。このフォトダイオードに光6が入射す
ると、受光領域は表面から深さ2.7 nまですべて空
乏層なので、導電層での光吸収による光電変換損失、す
なわちフリーキャリア吸収や発生した電子・正札対の消
滅などは表面では起こらず、2.7−以上侵入する長波
長光のみについて基板1内で生じるだけになる。さらに
空乏層の増加により空乏層容量が減少するので、光電流
発生効率が増加し、第2図の場合にくらべ大幅な感度の
向上になる。なお2層21の深さは第2図の場合と同じ
であるが、これを浅くすれば不純物濃度を高めることも
できる。
However, only the area around the high concentration 20 layer 22 is as shown in Figure 1 (al,
As shown in +1lt), a depletion layer with a width d and -2.4μ is generated on the substrate 1 side. When light 6 is incident on this photodiode, the entire light receiving region from the surface to a depth of 2.7 nm is a depletion layer, so there is a photoelectric conversion loss due to light absorption in the conductive layer, that is, free carrier absorption and the generated electron/genuine plate pair. Disappearance does not occur on the surface, but only occurs within the substrate 1 for long wavelength light that penetrates 2.7- or more. Furthermore, since the depletion layer capacitance decreases due to the increase in the depletion layer, the photocurrent generation efficiency increases, resulting in a significant improvement in sensitivity compared to the case shown in FIG. Although the depth of the second layer 21 is the same as in the case of FIG. 2, the impurity concentration can be increased by making it shallower.

第4図は別の実施例を示し、n形シリコン基板1にp膨
拡散層23が埋め込まれた構造のフォトダイオードであ
うでp−n接合が表面に露出せず、表面のもれ電流が少
ない利点がある。この実施例でもp形拡散M23の不純
物濃度と接合位置を調節してp膨拡散層23の上部の基
板1の表面までの部分およびp膨拡散層23自身をすべ
て空乏層3とすることにより、光6の入射の際に同じ効
果を得られることは明らかでなる。2層23は図示しな
い部分で表面に引き出され、配線に接続されている。
FIG. 4 shows another embodiment of the photodiode, which has a structure in which a p-swelled diffusion layer 23 is embedded in an n-type silicon substrate 1, in which the p-n junction is not exposed on the surface, and the surface leakage current is small. There are advantages. In this embodiment as well, by adjusting the impurity concentration and junction position of the p-type diffusion M23, the upper part of the p-swelling diffusion layer 23 up to the surface of the substrate 1 and the p-swelling diffusion layer 23 itself are all made into the depletion layer 3. It becomes clear that the same effect can be obtained upon incidence of light 6. The second layer 23 is drawn out to the surface at a portion not shown and connected to wiring.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、一導電形の基板と他導電形の層との間
のp−n接合を利用したフォトダイオードの他導電形層
の不純物濃度を接合位置と関連して適当な値に下げ、空
乏層が不純物導入層の受光域全域に広がるようにしたの
で、入射光は他導電形層に吸収されずに空乏層に到達す
ることになり、その間のフリーキャリア吸収や、発生し
た電子・正孔の消滅などによる光電変換損失がほとんど
なくなる。また空乏層幅が大きくなるので空乏層容量は
減り、電子・正孔対生成効率が増加する。これにより、
短波長光に対する感度を含めて感度が向上したフォトダ
イオードが得られる。
According to the present invention, the impurity concentration of the other conductivity type layer of a photodiode using a p-n junction between a substrate of one conductivity type and a layer of another conductivity type is reduced to an appropriate value in relation to the junction position. Since the depletion layer is made to spread over the entire light-receiving region of the impurity-introduced layer, the incident light reaches the depletion layer without being absorbed by the other conductivity type layer, and the free carrier absorption and the generated electrons and Photoelectric conversion loss due to disappearance of holes is almost eliminated. Furthermore, since the depletion layer width becomes larger, the depletion layer capacitance decreases and the electron/hole pair generation efficiency increases. This results in
A photodiode with improved sensitivity including sensitivity to short wavelength light can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(al 、 (bl 、 (C1は本発明の一実
施例を示し、talが平面図、 (b)が+II)のA
−A’線矢・挽断面図1(C)がTa)のB−8’線矢
視断面図、第2図+a+、 (bl、 (C)は従来の
フォトダイオードで、同様にta)が平面図、 (b)
が(alのc−c’線矢視断面図、(C)がTa)のD
−El’l矢線断面図、第3図はn層の不純物濃度を一
定にした場合のpn接合を形成するp層の不純物濃度を
空乏層幅との関係線図、第4図は本発明の別の実施例の
断面図である。 1:n形シリコン基板、21.23: p拡散層、22
:高濃度p層層、4:配線。 第1図
A of FIG.
1 (C) is a sectional view taken along the B-8' line of Ta), Figure 2 +a+, (bl, (C) is a conventional photodiode, and similarly ta) is Plan view, (b)
is a sectional view taken along the c-c' line of (al), (C) is D of Ta)
-El'l arrow sectional view, Figure 3 is a relationship between the impurity concentration of the p-layer forming a p-n junction and the depletion layer width when the impurity concentration of the n-layer is constant, and Figure 4 is a diagram of the present invention. FIG. 3 is a cross-sectional view of another embodiment of the invention. 1: n-type silicon substrate, 21. 23: p diffusion layer, 22
: High concentration p-layer layer, 4: Wiring. Figure 1

Claims (1)

【特許請求の範囲】 1)一導電形の半導体素体と該素体の受光面側に形成さ
れた他導電形の層との間のp−n接合に逆バイアスを印
加して空乏層を生成させ、該空乏層への光の入射により
光電流を生じさせるものにおいて、他導電形の層が受光
域全域にわたって空乏層が生ずるような不純物濃度およ
び深さを有することを特徴とするフォトダイオード。 2)特許請求の範囲第1項記載のダイオードにおいて、
他導電形の層と一導電形の層の不純物濃度がほぼ等しい
ことを特徴とするフォトダイオード。
[Claims] 1) A depletion layer is created by applying a reverse bias to the p-n junction between a semiconductor element of one conductivity type and a layer of another conductivity type formed on the light-receiving surface side of the element. A photodiode in which a layer of another conductivity type has an impurity concentration and depth such that a depletion layer is generated over the entire light-receiving region, in which a photocurrent is generated by the incidence of light into the depletion layer. . 2) In the diode according to claim 1,
A photodiode characterized in that a layer of another conductivity type and a layer of one conductivity type have approximately the same impurity concentration.
JP62279675A 1987-11-05 1987-11-05 Photo-diode Pending JPH01122176A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62279675A JPH01122176A (en) 1987-11-05 1987-11-05 Photo-diode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62279675A JPH01122176A (en) 1987-11-05 1987-11-05 Photo-diode

Publications (1)

Publication Number Publication Date
JPH01122176A true JPH01122176A (en) 1989-05-15

Family

ID=17614301

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62279675A Pending JPH01122176A (en) 1987-11-05 1987-11-05 Photo-diode

Country Status (1)

Country Link
JP (1) JPH01122176A (en)

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