JPH01122169A - Semiconductor device for power - Google Patents
Semiconductor device for powerInfo
- Publication number
- JPH01122169A JPH01122169A JP62279358A JP27935887A JPH01122169A JP H01122169 A JPH01122169 A JP H01122169A JP 62279358 A JP62279358 A JP 62279358A JP 27935887 A JP27935887 A JP 27935887A JP H01122169 A JPH01122169 A JP H01122169A
- Authority
- JP
- Japan
- Prior art keywords
- well
- type
- semiconductor
- control
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 150000002500 ions Chemical class 0.000 abstract description 4
- 239000002131 composite material Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000001514 detection method Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000005855 radiation Effects 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 230000003213 activating effect Effects 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/0883—Combination of depletion and enhancement field effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
この発明は、１チツプの半導体基板に本来の機能を発揮
する能動素子と共に、例えば温度、電圧、電流等の検出
機能ざらに保ｍｍ能等を有する制御要素を内蔵させた複
合型の電力用半導体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention provides active elements that perform their original functions on a single chip semiconductor substrate, as well as detection functions such as temperature, voltage, current, etc. The present invention relates to a composite power semiconductor device incorporating a control element having a built-in control element.
［従来の技術］
電力用の半導体装置にあっては、ＤＭＯ８（Ｄｕｂｌｅ
Ｄｉｆｆｓｅｄ ＭＯＳ） ＦＥＴ構造が知られ
ているものであり、このような能動素子に対して、同一
半導体チップ内に温度、電圧、電流等の検出機能、およ
びこれらを用いた保［１能等を有する制御要素を内蔵設
定するようにした複合素子が考えられている。[Prior Art] In power semiconductor devices, DMO8 (Double
The Diffsed MOS) FET structure is known, and for such an active element, it has detection functions such as temperature, voltage, and current, as well as protection functions using these within the same semiconductor chip. Composite devices with built-in control elements have been considered.
すなわち、電力用半導体装置は負荷電流をｌ１ｌｔｌｌ
する能動機能を有する半導体素子を含み構成されている
ものであるが、この半導体素子の接合部にあっては、負
荷電流が流れることによって発熱するようになる。この
ため、例えば負荷の短絡時等にあっては、上記接合部に
大電流が流れ、この接合部の温度が異常に上昇されるよ
うになり、半導体素子が破壊されるようになるおそれが
ある。このような問題点を解決する手段として、半導体
基板の異常温度状態までの上昇を検知し、例えば上記能
動動作をする半導体素子をオフ制御するような保護動作
が要求され、このような保護動作を行う制ｗＪ要素部を
、上記能動動作を行う半導体素子゛と同一チップ内に形
成させるようにするものである。In other words, the power semiconductor device reduces the load current to l1ltll.
The semiconductor device includes a semiconductor element having an active function of activating the semiconductor element, and heat is generated when a load current flows at the junction of the semiconductor element. For this reason, for example, when a load is short-circuited, a large current flows through the junction, causing the temperature of this junction to rise abnormally, which may damage the semiconductor element. . As a means to solve these problems, a protective operation is required that detects the rise in temperature of the semiconductor substrate to an abnormal state, and turns off the active semiconductor element, for example. The controlling wJ element section to perform the above-mentioned active operation is formed in the same chip as the semiconductor element which performs the active operation.
このような複合素子を構成するための素子としては、Ｐ
Ｎ接合分離、誘電体分離等の非常に？！雑な素子構造に
よるものが多く、またこれらの素子は寄生動作を生じ易
いものであり、製造工程も複雑化する傾向にある。した
がって、１チツプに制御要素をに内蔵させた複合素子と
する効果が充分に発揮できないものであった。As an element for configuring such a composite element, P
N-junction isolation, dielectric isolation, etc.? ! Many of them have complicated element structures, and these elements tend to cause parasitic operation, and the manufacturing process tends to become complicated. Therefore, the effect of constructing a composite device in which control elements are built into one chip cannot be fully exhibited.
［発明が解決しようとする問題点］
この発明は上記のような点に鑑みなされたもので、例え
ば負荷電流を制御するような能動機能を有する半導体素
子の形成される半導体基板上に、さらに上記能動機能以
外の制御機能を発揮する制御要素を形成するような半導
体装置において、充分に簡易化した素子構造によって、
また製造工程も特に複雑にすることなく上記制御要素が
能動素子と共に同一半導体チップに内蔵設定されるよう
にする複合機能を有する電力用半導体装置を提供しよう
とするものである。[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned points. In semiconductor devices that form control elements that perform control functions other than active functions, a sufficiently simplified element structure enables
Another object of the present invention is to provide a power semiconductor device having multiple functions in which the control element and the active element are built into the same semiconductor chip without complicating the manufacturing process.
［問題点を解決するための手段］
すなわち、この発明に係る電力用半導体装置にあっては
、能動素子が形成されるようになる半導体基板にＰある
いはＮ型のウェルを形成し、このウェルに形成されたＮ
チャンネルあるいはＰチャンネルのみのエンハンスメン
ト型およびディプレッション型のＭＱＳ Ｆ Ｅ Ｔを
用いて、上記制御要素が構成されるようにしているもの
である。[Means for Solving the Problems] That is, in the power semiconductor device according to the present invention, a P or N type well is formed in a semiconductor substrate on which an active element is to be formed, and a P or N type well is formed in this well. formed N
The control element is configured using enhancement type and depletion type MQS FET of channel or P channel only.
［作用］
上記能動素子と同一の半導体チップ内に形成されるよう
になるａ制御要素にあっては、通常の能動機能を有する
半導体素子と同様の製造工程によって簡単に形成される
ようになる。そして、例えばエンハンスメント型ＭＯ３
ＦＥＴに対して、その閾値を変更するために１枚のマス
クが必要とされるのみである。ここで、ディプレッショ
ン型ＭＯ８ＦＥＴにあっては、それ自体自己発熱が問題
となるものであるが、このディプレッション型ＭＯ８Ｆ
ＥＴと同一半導体チップには、より大きく発熱する電力
用半導体素子が形成されているものであるため、充分な
放熱対策がとられているものであるため、問題は無い。[Function] The a control element to be formed in the same semiconductor chip as the active element can be easily formed by the same manufacturing process as a semiconductor element having a normal active function. For example, enhancement type MO3
Only one mask is required for the FET to change its threshold. Here, depletion type MO8FET itself has a problem of self-heating, but this depletion type MO8FET
Since a power semiconductor element that generates more heat is formed on the same semiconductor chip as the ET, sufficient heat dissipation measures have been taken, so there is no problem.
［発明の実施例］ 以下、図面を参照してこの発明の一実施例を説明する。[Embodiments of the invention] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図は半導体装置の断面構造を示したもので、半導体
基板１１はＮ＋型の低抵抗層１１１と、Ｎ−型のａ抵抗
＠ １１２とによって構成されるもので、この半導体基
板１１上には負荷電流の制御を行う能動機能を有する半
導体素子１２等が形成されるパワー領域１３が設定され
ている。そして、このパワー領域１３とは区分されるよ
うにして、上記半導体基板１１上に制御ｍ領域１４が設
定されるもので、この制御領域１４に各種制、御動作を
行うコンパレータ、電流検出器、電圧検出器等が形成さ
れるようになっている。この制御領域１４は、半導体基
板１１の表面部に対応して形成されたＰウェル１５に対
応して設定されるもので、このＰウェル１５にはＮチャ
ンネルＭＯ３ＦＥＴ１６および１７が形成されるように
なる。この場合、ＭＯ８ＦＥＴ１６はエンハンスメント
型に構成されるものであり、マスクを用いてＮ４″イオ
ン１８を打ち込むことによって、ＭＯ８ＦＥＴ１７はデ
ィプレッション型に構成されるようになる。FIG. 1 shows a cross-sectional structure of a semiconductor device. A semiconductor substrate 11 is composed of an N+ type low resistance layer 111 and an N- type a resistor @ 112. A power region 13 is set in which semiconductor elements 12 and the like having an active function of controlling load current are formed. A control region 14 is set on the semiconductor substrate 11 so as to be separated from the power region 13, and this control region 14 includes a comparator, a current detector, and a current detector for performing various control and control operations. A voltage detector etc. are formed. This control region 14 is set corresponding to a P-well 15 formed corresponding to the surface portion of the semiconductor substrate 11, and N-channel MO3FETs 16 and 17 are formed in this P-well 15. . In this case, the MO8FET 16 is configured as an enhancement type, and by implanting N4'' ions 18 using a mask, the MO8FET 17 is configured as a depletion type.
また、上記制御領域１４を形成するＰウェル１５の表面
部には、シリコン酸化膜による絶縁ＷｊＪ１９が形成さ
れ、この絶縁層１９上にはポリシリコン層２０を形成し
、このポリシリコン９２０部分にＰＮ接合を形成するこ
とによってダイオード２１が形成されるようにする。ま
た、上記絶縁層１９上にポリシリコンによる抵抗層２２
を形成することによって抵抗素子２３が形成されるよう
にしているものであり、ざらにＰウェル１５上にツェナ
ーダイオード２４が形成されるようにしている。そして
、これらＰウェル１５に対応するＩＩＪＩＩｌ領域１４
において、パワー領域１３に形成された半導体素子１３
等とは異なる機能の制御ｌｌ＃ｈ作を実行する１７１１
８回路が形成されるようにしている。Furthermore, an insulation WjJ19 made of a silicon oxide film is formed on the surface of the P well 15 forming the control region 14, a polysilicon layer 20 is formed on this insulation layer 19, and a PN layer is formed on this polysilicon 920. By forming a junction, a diode 21 is formed. Further, a resistance layer 22 made of polysilicon is provided on the insulating layer 19.
The resistive element 23 is formed by forming a Zener diode 24 roughly on the P well 15. IIJIIIl regions 14 corresponding to these P wells 15
, the semiconductor element 13 formed in the power region 13
1711 to control functions different from etc.
Eight circuits are formed.
第２図は上記のような電力用半導体装置において、その
制御領域１４に形成される制御回路の一例で、コンパレ
ータを示している。このコンパレータはＮチャンネルＭ
Ｏ８ＦＥＴのみによって構成されるようになるものであ
り、Ｍｌ 、Ｍ４ 、ＭＳがディプレッション型ＭＯ８
ＦＥＴであり、Ｍ２、Ｍ３ 、ＭＳ 、Ｍ７がエンハン
スメント型ＭＯ３ＦＥＴである。ここで、上記ディプレ
ッション型およびエンハンスメント型ＭＯ８ＦＥＴは基
本的には同じ構造であり、ディプレッション型ＭＯ８Ｆ
ＥＴの場合、前記したようにゲート酸化膜の下のＰ層に
Ｎ＋イオンが注入されるものである。そして、その製造
工程においては、このイオン注入のために１枚のマスク
が使用されるようになる。FIG. 2 shows an example of a control circuit formed in the control region 14 of the power semiconductor device as described above, and shows a comparator. This comparator is N channel M
It is composed only of O8FETs, and Ml, M4, and MS are depletion type MO8
M2, M3, MS, and M7 are enhancement type MO3FETs. Here, the depression type MO8FET and the enhancement type MO8FET have basically the same structure, and the depression type MO8FET
In the case of ET, N+ ions are implanted into the P layer below the gate oxide film, as described above. In the manufacturing process, one mask is used for this ion implantation.
上記のように構成される電力用半導体装置にあっては、
同一の半導体チップ内にこの半導体装置の保護回路、あ
るいは外部との入出力信号のやり取りを扱うｉ制御回路
等が内蔵されるようになる。In the power semiconductor device configured as described above,
A protection circuit for this semiconductor device, an i-control circuit that handles exchange of input/output signals with the outside, and the like are built into the same semiconductor chip.
この場合、この制御回路部の素子構造としては、ＰＮ接
合分離、誘電体分離等を採用すると、０ＭＯ３さらにバ
イポーラ素子を作り込むことが可能となるものであるが
、これでは非常に複雑な構造となってコストアップは避
けられない。In this case, if PN junction isolation, dielectric isolation, etc. are adopted as the element structure of this control circuit section, it will be possible to incorporate 0MO3 and even bipolar elements, but this would result in a very complicated structure. As a result, cost increases are unavoidable.
しかし、実施例で示したようにディプレッション型ＭＯ
８ＦＥＴを採用することによって、回路をＮチャンネル
のみによって構成することによって、複雑な素子構造と
する必要が無くなる。ここで、エンハンスメント型ＭＯ
８ＦＥＴに対して、その閾値を変更するためのディプレ
ッション用のマスクを追加しＮ０イオンを注入すること
によって、ディプレッション型にすることが可能であり
、その製造工程が複雑化されることがない。However, as shown in the example, depression type MO
By employing 8FETs, the circuit is configured with only N channels, thereby eliminating the need for a complicated element structure. Here, enhancement type MO
By adding a depletion mask to change the threshold value of the 8FET and implanting N0 ions, it is possible to make the 8FET into a depletion type, without complicating the manufacturing process.
また、−膜内にディプレッション型
ＭＯ８ＦＥＴは、ノーマル オンのタイプであるので、
この素子の自己発熱が問題となる。しかし、この制御回
路部が内蔵設定される電力用の半導体素子の場合、この
電力用の能動素子自身の発熱が、上記ディプレッション
型ＭＯ８ＦＥＴの自己発熱よりはるかに大きなものであ
り、この電力用半導体装置に設定される放熱機構以外に
、さらに放熱対策を施す必要がなく、このディプレッシ
ョン型ＭＯ８ＦＥＴの自己発熱に対する問題は実質的に
存在しない。Also, since the depletion type MO8FET in the membrane is a normally on type,
Self-heating of this element poses a problem. However, in the case of a power semiconductor device in which this control circuit section is built-in, the heat generated by the power active element itself is much larger than the self-heating of the depletion type MO8FET, and this power semiconductor device There is no need to take any further heat radiation measures other than the heat radiation mechanism set in , and there is virtually no problem with self-heating of this depletion type MO8FET.
上記実施例では、半導体基板１１の制御領域１４にコン
パレータを内蔵設定するように説明しているが、第１図
で示したようにダイオード、抵抗素子、ツェナーダイオ
ード等も同時に組み込み設定できるものであるため、さ
らにインバータ、オペアンプ、基準電圧発生器等、これ
まで知られている回路を、上記能動素子と同一半導体チ
ップ内に内蔵設定し、各種複合機能素子が構成できるよ
うになるものである。In the above embodiment, it is explained that a comparator is installed in the control area 14 of the semiconductor substrate 11, but as shown in FIG. 1, a diode, a resistive element, a Zener diode, etc. can also be installed at the same time. Therefore, it is possible to incorporate conventionally known circuits such as inverters, operational amplifiers, reference voltage generators, etc. into the same semiconductor chip as the active elements, thereby making it possible to construct various multifunctional elements.
例えば、基準電圧源等を電力用半導体装置内に取り込み
形成することによって、部品点数が充分に削減されるよ
うになり、信頼性の向上が効果的に図れるようになり、
製造工程数の増加を最少限に止どめることが可能となる
。For example, by incorporating a reference voltage source, etc. into a power semiconductor device, the number of parts can be sufficiently reduced, and reliability can be effectively improved.
It is possible to minimize the increase in the number of manufacturing steps.
また、上記実茄例にあっては、半導体基板に形成された
ＰウェルにＮチャンネルのエンハンスメント型およびデ
ィプレッション型のＭＯＳＦＥＴを形成するように説明
したが、半導体基板にＮウェルを形成゛し、Ｐチャンネ
ルのみのエンハンスメント型およびディプレッション型
のＭＯＳＦＥＴを構成し、これらＭＯＳＦＥＴで上記制
御＋要素が構成されるよにしてもよい。Furthermore, in the above practical example, it has been explained that N-channel enhancement type and depletion type MOSFETs are formed in a P-well formed in a semiconductor substrate, but it is also possible to form an N-well in a semiconductor substrate and to form a P-type MOSFET. Channel-only enhancement type and depletion type MOSFETs may be configured, and these MOSFETs may constitute the control + element.
［発明の効果］
以上のようにこの発明に係る電力用半導体装置にあって
は、能動機能を有する半導体素子と共に、上記能動機能
とは異なる機能を発揮する制御要素が同一半導体チップ
内に形成される複合機能半導体装置が構成されるもので
あり、この場合特に上記制御要素は充分に簡単な工程で
能動機能を有する半導体素子と共に製造できるものであ
り、構造および製造工程の簡易化と共に信頼性の向上に
も大きな効果が発揮されるようになる。[Effects of the Invention] As described above, in the power semiconductor device according to the present invention, a control element that exhibits a function different from the active function is formed in the same semiconductor chip together with a semiconductor element having an active function. In this case, the above-mentioned control element can be manufactured together with a semiconductor element having an active function in a sufficiently simple process, and the structure and manufacturing process can be simplified and reliability can be improved. It will also have a great effect on improvement.
第１図はこの発明の一実施例に係る電力用半導体装置の
断面構造を説明する図、第２図は上記半導体装置に制御
要素として組み込まれる回路の例を示す図である。
１１・・・半導体基板、１２・・・半導体素子、１３・
・・パワー領域、１４・・・制御領域、１５・・・Ｐウ
ェル、１６、Ｍｌ、Ｍ３ 、Ｍ６ 、Ｍ７・・・エンハ
ンスメント型ＭＯ８ＦＥＴ、１５、Ｍｌ 、Ｍ４ 、Ｍ
５−・・デ４７Ｌ／ッション型ＭＯ８ＦＥＴ。
出願人代理人 弁理士 鈴江武彦
！Ｉ２図FIG. 1 is a diagram illustrating a cross-sectional structure of a power semiconductor device according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating an example of a circuit incorporated as a control element in the semiconductor device. 11... Semiconductor substrate, 12... Semiconductor element, 13.
... Power region, 14... Control region, 15... P well, 16, Ml, M3, M6, M7... Enhancement type MO8FET, 15, Ml, M4, M
5-...De47L/shock type MO8FET. Applicant's representative Patent attorney Takehiko Suzue! I2 diagram
Claims (1)
と、この半導体基板に上記能動素子と共に形成され、こ
の能動素子とは異なる他の機能素子を備えた制御要素と
を有する半導体装置において、 上記制御要素は、上記半導体基板に形成されたＮあるい
はＰウェルに形成されたＰチャンネルあるいはＮチャン
ネルのみのディプレッション型およびエンハンスメント
型のＭＯＳＦＥＴによって構成されるようにしたことを
特徴とする電力用半導体装置。[Scope of Claims] A semiconductor comprising a semiconductor substrate on which a semiconductor element having an active function is formed, and a control element formed on the semiconductor substrate together with the active element and equipped with another functional element different from the active element. In the device, the control element is constituted by a P-channel or only N-channel depletion type and enhancement type MOSFET formed in an N or P well formed in the semiconductor substrate. Semiconductor equipment for use.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62279358A JPH07120797B2 (en) | 1987-11-06 | 1987-11-06 | Power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62279358A JPH07120797B2 (en) | 1987-11-06 | 1987-11-06 | Power semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01122169A true JPH01122169A (en) | 1989-05-15 |
| JPH07120797B2 JPH07120797B2 (en) | 1995-12-20 |
Family
ID=17610056
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62279358A Expired - Lifetime JPH07120797B2 (en) | 1987-11-06 | 1987-11-06 | Power semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07120797B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0479379A (en) * | 1990-07-23 | 1992-03-12 | Fuji Electric Co Ltd | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58134474A (en) * | 1982-02-05 | 1983-08-10 | Sony Corp | Semiconductor circuit device |
-
1987
- 1987-11-06 JP JP62279358A patent/JPH07120797B2/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58134474A (en) * | 1982-02-05 | 1983-08-10 | Sony Corp | Semiconductor circuit device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0479379A (en) * | 1990-07-23 | 1992-03-12 | Fuji Electric Co Ltd | Semiconductor device |
| JP2890725B2 (en) * | 1990-07-23 | 1999-05-17 | 富士電機株式会社 | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH07120797B2 (en) | 1995-12-20 |
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