JPH01121771A - Characteristic impedance measuring circuit - Google Patents

Characteristic impedance measuring circuit

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Publication number
JPH01121771A
JPH01121771A JP27975887A JP27975887A JPH01121771A JP H01121771 A JPH01121771 A JP H01121771A JP 27975887 A JP27975887 A JP 27975887A JP 27975887 A JP27975887 A JP 27975887A JP H01121771 A JPH01121771 A JP H01121771A
Authority
JP
Japan
Prior art keywords
output
impedance
transmission line
circuit
characteristic impedance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27975887A
Other languages
Japanese (ja)
Inventor
Noboru Shoji
庄子 昇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP27975887A priority Critical patent/JPH01121771A/en
Publication of JPH01121771A publication Critical patent/JPH01121771A/en
Pending legal-status Critical Current

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  • Measurement Of Resistance Or Impedance (AREA)

Abstract

PURPOSE:To measure the characteristic impedance of a transmission line with high accuracy by driving the transmission line with low output impedance to a large amplitude, and making the output impedance high and increasing a reflected wave when a reflected wave returns from the distant terminal of the line. CONSTITUTION:The circuit consists of a driving circuit 1 which inputs a pulse signal from an input terminal 5, a measurement terminal 2 connected to its output, the transmission line 3 to be measured, and a variable resistance circuit 4 provided between its distant terminal and a positive electrode voltage. In this constitution, the circuit 1 has output impedance larger than the characteristic impedance of the line 3 at the time of low output level, but sufficiently large output impedance is provided at the time of high output level. The line 3 is an unbalanced type and both terminals of its return wire are grounded. An inverter 11, a resistance 12 and a transistor(TR) 13 are provided between the input terminal 10 and output terminal 14 of the circuit 1 and the output terminal 14 is placed in the low-output or high-output impedance state according to the output of the inverter 11.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は特性インピーダンス測定回路、特にパルスを用
いて伝送線路の特性インピーダンスを測定する測定回路
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a characteristic impedance measuring circuit, and particularly to a measuring circuit that measures the characteristic impedance of a transmission line using pulses.

〔従来の技術〕[Conventional technology]

従来のこの種の特性インピーダンスの測定回路は、出力
レベルに無関係に一定な出力インピーダンス(一般には
50【lが多い)t−持つ駆動回路により、ステップパ
ルスあるいはパルス巾を持つtパルスで被測定伝送線路
を駆動し、伝送線路の遠端に接続し九可変抵抗回路を調
整して、伝送線路遠端での反射波がなくなったときの可
変抵抗回路の抵抗値を伝送線路の特性インピーダンスと
する回路が一般【用いられる。反射波の観測は駆動回路
の出力で行なう。
Conventional characteristic impedance measuring circuits of this type use a drive circuit with a constant output impedance (generally 50l) regardless of the output level to transmit the signal to be measured using step pulses or pulses with a pulse width of t. A circuit that drives a transmission line, adjusts a variable resistance circuit connected to the far end of the transmission line, and sets the resistance value of the variable resistance circuit when there is no reflected wave at the far end of the transmission line as the characteristic impedance of the transmission line. is commonly used. Observation of reflected waves is performed using the output of the drive circuit.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、上述し九従来の特性インピーダンス測定回路は
、駆動回路の出力インピーダンスが伝送線路の特性イン
ピーダンスと同等があるいは小さいために、駆動回路の
出力端で観測する電圧は到来する反射電圧と同等かある
いは小さくなる。それは駆動回路の出力端での反射係数
が零の付近かあるいは負になるためである。この結果、
反射波の有無の判定が難かしく特性インピーダンスの測
定精度が悪いという欠点があった。
However, in the nine conventional characteristic impedance measurement circuits mentioned above, the output impedance of the drive circuit is equal to or smaller than the characteristic impedance of the transmission line, so the voltage observed at the output end of the drive circuit is equal to or smaller than the incoming reflected voltage. becomes smaller. This is because the reflection coefficient at the output end of the drive circuit is close to zero or negative. As a result,
It has the disadvantage that it is difficult to determine the presence or absence of reflected waves and the accuracy of measuring characteristic impedance is poor.

−万、出力端での反射係数を正にして反射波を大きくす
るために駆動回路の出力インピーダンスを大きくすると
、駆動回路の駆動電圧は出方インピーダンスと特性イン
ピーダンスとで分圧されるため、伝送線路の駆動電圧が
小さくなり、しtがって反射電圧も小さくなって測定精
成は上らない。
- If the output impedance of the drive circuit is increased in order to make the reflection coefficient positive at the output end and increase the reflected wave, the drive voltage of the drive circuit will be divided by the output impedance and the characteristic impedance, so the transmission The driving voltage of the line becomes small, and therefore the reflected voltage also becomes small, and measurement accuracy does not improve.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の特性インピーダンス測定回路は、低出力レベル
時く伝送線路の特性インピーダンスより小さい出力イン
ピーダンス含有し又高出力レベル時1c%性インピーダ
ンスより十分大きい出力インピーダンスを有し、又、伝
送線路の往復伝搬遅延時間より小さいパルス巾の負極性
のパルス信号を伝送線路に駆動する駆動回路と、伝送線
路の遠端に接続し又片端に正極電圧が印加され九可変抵
抗回路と、駆動回路の出力に接続される測定端子とを有
している。
The characteristic impedance measurement circuit of the present invention has an output impedance smaller than the characteristic impedance of the transmission line at low output levels, an output impedance sufficiently larger than the 1c% characteristic impedance at high output levels, and A drive circuit that drives a negative polarity pulse signal with a pulse width smaller than the delay time onto the transmission line, a variable resistance circuit connected to the far end of the transmission line, and a positive voltage applied to one end, and a nine variable resistance circuit connected to the output of the drive circuit. It has a measurement terminal.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示す回路図であり、入力端
子5からのパルス信号を入力する駆動回路1と、駆動回
路1の出力に接続する測定端子2と、測定対象の伝送線
路3と、伝送線路3の遠端と正極電圧VCとの間に接続
される可変抵抗回路4とから構成される。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, showing a drive circuit 1 that receives a pulse signal from an input terminal 5, a measurement terminal 2 connected to the output of the drive circuit 1, and a transmission line to be measured. 3, and a variable resistance circuit 4 connected between the far end of the transmission line 3 and the positive voltage VC.

駆動回路1は低出力レベル時には伝送線路3の特性イン
ピーダンスより小さい出力インピーダンス含有し、又高
出力レベル時には特性インピーダンスより十分大きい出
力インピーダンス含有している。伝送線路3は不平衡型
を例としており帰線の両端は接地している。
The drive circuit 1 has an output impedance smaller than the characteristic impedance of the transmission line 3 at a low output level, and has an output impedance sufficiently larger than the characteristic impedance at a high output level. The transmission line 3 is an unbalanced type, and both ends of the return line are grounded.

第2図は駆動回路1の一実施例の詳細回路である。FIG. 2 is a detailed circuit diagram of one embodiment of the drive circuit 1.

入力端子10はインバータ回路11の入力に接続され、
インバータ回路11の出力は抵抗12を通してNPNの
トランジスタ130ペースに接続される。
The input terminal 10 is connected to the input of the inverter circuit 11,
The output of the inverter circuit 11 is connected through a resistor 12 to an NPN transistor 130 pace.

トランジスタ13のエミッタは接地され、コレクタは出
力端子14に接続される。
The emitter of transistor 13 is grounded, and the collector is connected to output terminal 14.

入力電圧が低レベルの場合は、インバータ回路11の出
力は高レベルとなり、トランジスタ13はONKなり、
出力端子14は低レベルになるとともに低出力インピー
ダンスになる。入力電圧が高レベルの場合は、インバー
タ回路11の出力は低レベルになり、トランジスタ13
はOF’FlCなり出力端子14は高出力インピーダン
ス状態となる。
When the input voltage is at a low level, the output of the inverter circuit 11 is at a high level, and the transistor 13 is turned ON.
The output terminal 14 becomes low level and has a low output impedance. When the input voltage is at a high level, the output of the inverter circuit 11 is at a low level, and the transistor 13
becomes OF'FlC, and the output terminal 14 becomes in a high output impedance state.

@3図は本実施例の動作を説明するための電圧波形を示
したものであり、第3図(a)は測定端子2での波形、
第3図(blは伝送線路3の遠端での反射パルスをそれ
ぞれ示している。
@Figure 3 shows voltage waveforms for explaining the operation of this example, and Figure 3 (a) shows the waveform at measurement terminal 2,
FIG. 3 (bl indicates the reflected pulse at the far end of the transmission line 3, respectively).

伝送線路3の往復の伝搬遅延時間T2よりも小さいパル
ス巾TIの負極性のパルス信号を入力端子5!/c入力
すると、駆動回路1は出力が低レベルの時すなわちパル
ス巾T1の時間だけ低出力インピーダンスで伝送線路3
を駆動し、その他の時は高出力インピーダンスになり、
伝送線路3は可変抵抗回路4を通して正極電圧VCに接
続されている友め、駆動回路1の出力は高レベルとなる
A negative pulse signal with a pulse width TI smaller than the round-trip propagation delay time T2 of the transmission line 3 is input to the input terminal 5! When /c is input, the drive circuit 1 connects the transmission line 3 with low output impedance only when the output is at a low level, that is, during the pulse width T1.
At other times, it becomes a high output impedance,
Since the transmission line 3 is connected to the positive voltage VC through the variable resistance circuit 4, the output of the drive circuit 1 is at a high level.

g3図(a)に示す駆動パルスVDは、伝送線路3を伝
搬してゆき可変抵抗回路4に到達する。伝送線路3の特
性インピーダンスt’Ze、可変抵抗回路4の抵抗値1
1(、Vとし、説明をわかりやすくするために、伝送線
路3は無損失とすると、伝送線路30遠端での反射パル
スVault と表わされる。
The driving pulse VD shown in FIG. 3(a) propagates through the transmission line 3 and reaches the variable resistance circuit 4. Characteristic impedance t'Ze of transmission line 3, resistance value 1 of variable resistance circuit 4
1 (, V), and assuming that the transmission line 3 is lossless for ease of explanation, the reflected pulse at the far end of the transmission line 30 is expressed as Vault.

反射パルスVRIは逆方向に伝搬してゆき測定端子21
1C到達する。測定端子2には、反射パルスVR,tと
その駆動回路1の出力での再反射パルスが重なり之電圧
が現われる。駆動回路1の出力インピーダンス金几りと
すると、測定端子2で測定される測定パルスVa2は と表わされる。
The reflected pulse VRI propagates in the opposite direction and reaches the measurement terminal 21.
Reach 1C. At the measuring terminal 2, a voltage appears due to the superposition of the reflected pulse VR,t and its re-reflected pulse at the output of the drive circuit 1. Assuming that the output impedance of the drive circuit 1 is set to 1, the measurement pulse Va2 measured at the measurement terminal 2 is expressed as follows.

反射パルスvR1が駆動回路lの出力に戻る時には、す
でに駆動回路1の出力は高レベルにしているため、出力
インピーダンスRLは特性インピーダンス2・に比べて
十分大きい。この結果により、(2)式の第2項はほぼ
反射パルスVB、1となるので、 VPLz  ”:; zVRt           
    (31となり、測定端子2における測定パルス
VB、2は反射パルスVRIの2倍の値で測定できるこ
とになる。
When the reflected pulse vR1 returns to the output of the drive circuit 1, the output of the drive circuit 1 is already at a high level, so the output impedance RL is sufficiently larger than the characteristic impedance 2. According to this result, the second term of equation (2) becomes approximately the reflected pulse VB, 1, so VPLz ”:; zVRt
(31, which means that the measurement pulse VB,2 at the measurement terminal 2 can be measured at twice the value of the reflected pulse VRI.

特性インピーダンスZ・は、可変抵抗回路4f:可変し
て1反射パルスvR1がなくなったときの抵抗値RV1
<測定することにより求められる。そのとき抵抗値kL
vは特性インピーダンスZeに等しくなり、(1)式よ
り反射パルスV几1は零となり。
The characteristic impedance Z is the variable resistance circuit 4f: resistance value RV1 when one reflected pulse vR1 disappears after being varied.
<Determined by measurement. At that time, the resistance value kL
v becomes equal to the characteristic impedance Ze, and from equation (1), the reflected pulse V1 becomes zero.

(3)式より測定パルスV几2は同じく零となる。From equation (3), the measurement pulse V2 is also zero.

抵抗値几Vと特性インピーダンス2Gとの差による反射
パルス■几1の2倍の電圧値が測定端子2で測定できる
ということは、特性インピーダンス2・の測定精度も2
倍に向上するということである。
Reflected pulse due to the difference between the resistance value ⇠V and the characteristic impedance 2G ■The fact that a voltage value twice that of ⇠1 can be measured at the measurement terminal 2 means that the measurement accuracy of the characteristic impedance 2 is also 2.
This means that the improvement will be doubled.

駆動回路lの低出力レベル時の出力インピーダンスは小
さい九め、伝送線路3の駆動電圧を大きくすることがで
きる。出力インピーダンスと特性インピーダンスとの分
圧による駆動電圧の低下が小さいからである。
Since the output impedance of the drive circuit 1 at a low output level is small, the drive voltage of the transmission line 3 can be increased. This is because the drop in drive voltage due to voltage division between the output impedance and the characteristic impedance is small.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、伝送線路を駆動するとき
は低出力インピーダンスとして大きな振巾で駆動し、又
伝送線路の遠端からの反射波が戻るときには高出力イン
ピーダンスにして反射波を大きくする駆動回路を使うこ
とにより、伝送線路の特性インピーダンスを高精度で測
定できる効果がある。
As explained above, in the present invention, when driving a transmission line, the transmission line is driven with a low output impedance and with a large amplitude, and when the reflected wave from the far end of the transmission line returns, it is set to a high output impedance and the reflected wave is increased. By using a drive circuit, the characteristic impedance of the transmission line can be measured with high precision.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す回路図%第2図は第1
図の駆動回路1の詳細回路図、第3図は動作を説明する
ための電圧波形を示す。 l・・・・・・駆動回路、2・・・・・・測定端子、3
・・・・・・伝送線路、4・・・・・・可変抵抗回路、
5.10・・・・・・入力端子、11・・・・・・イン
バータ回路、12・・・・・・抵抗、13・・・・・・
トランジスタ、14・・・・・・出方端子。 代理人 弁理士  内 原   音 第 1 目 石2 図 石 3 図
Figure 1 is a circuit diagram showing one embodiment of the present invention. Figure 2 is a circuit diagram showing one embodiment of the present invention.
A detailed circuit diagram of the drive circuit 1 shown in the figure, and FIG. 3 shows voltage waveforms for explaining the operation. l...Drive circuit, 2...Measurement terminal, 3
...Transmission line, 4...Variable resistance circuit,
5.10... Input terminal, 11... Inverter circuit, 12... Resistor, 13...
Transistor, 14... Output terminal. Agent Patent Attorney Uchihara Otodai 1 Meishi 2 Zuishi 3 Diagram

Claims (1)

【特許請求の範囲】 低出力レベル時に伝送線路の特性インピーダンスより小
さい出力インピーダンスを有し又高出力レベル時に前記
特性インピーダンスより十分大きい出力インピーダンス
を有し、又、前記伝送線路の往復伝搬遅延時間より小さ
いパルス巾の負極性のパルス信号を前記伝送線路に駆動
する駆動回路と、 前記伝送線路の遠端に接続し又片端に正極電圧が印加さ
れた可変抵抗回路と、 前記駆動回路の出力に接続される測定端子 とから構成されることを特徴とする特性インピーダンス
測定回路。
[Scope of Claims] It has an output impedance that is smaller than the characteristic impedance of the transmission line at low output levels, and has an output impedance that is sufficiently larger than the characteristic impedance at high output levels, and has an output impedance that is sufficiently larger than the characteristic impedance at high output levels, and is smaller than the round-trip propagation delay time of the transmission line. a drive circuit that drives a negative polarity pulse signal with a small pulse width to the transmission line; a variable resistance circuit connected to the far end of the transmission line and having a positive voltage applied to one end; and a variable resistance circuit connected to the output of the drive circuit. A characteristic impedance measuring circuit comprising: a measuring terminal for measuring impedance;
JP27975887A 1987-11-04 1987-11-04 Characteristic impedance measuring circuit Pending JPH01121771A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP27975887A JPH01121771A (en) 1987-11-04 1987-11-04 Characteristic impedance measuring circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27975887A JPH01121771A (en) 1987-11-04 1987-11-04 Characteristic impedance measuring circuit

Publications (1)

Publication Number Publication Date
JPH01121771A true JPH01121771A (en) 1989-05-15

Family

ID=17615496

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27975887A Pending JPH01121771A (en) 1987-11-04 1987-11-04 Characteristic impedance measuring circuit

Country Status (1)

Country Link
JP (1) JPH01121771A (en)

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