JPH01120866A - Semiconductor device - Google Patents

Abstract

PURPOSE:To shorten manufacturing steps and to improve yield of a semiconductor device by employing a superconducting material for at least a gate insulating film and a gate electrode. CONSTITUTION:A gate insulating film 4, a gate electrode 5 and an interelement isolation layer 2 are formed of a superconducting material, the films are formed at once, and the films 4, the electrode 5 and the layer 2 are then formed. An interlayer insulating film 6 is formed of an SiO2, and source, drain electrodes 7 are formed of the superconducting material. The electrodes 5, 7 for forming an electrode section, the film 4 for forming an insulation section and the layer 2 of sections formed of the superconducting material are so altered in its composition that the critical temperature of the electrode section is higher than that of the insulation section. Accordingly, when a TFT is operated at a temperature between the critical temperatures of the electrode section and the insulation section, the electrode section exhibits superconductivity, and the insulation section exhibits insulation. Thus, manufacturing steps are shortened, and its yield is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device in which at least a gate insulating film and a gate electrode are formed of a superconducting material.

[Prior art]

MOS type TFTs formed on semiconductor substrates are widely used in various integrated circuits and the like. In these MO8 type TFTs, as shown in FIG. It is composed of a gate insulating film 4, a gate electrode 5 formed thereon, an interlayer insulating film 6 made of Sio, and source/drain electrodes 7. Conventional TF like this
In T, the gate electrode 5 is usually formed of poly-5i with low resistance by diffusion of impurities, and the source/drain electrode 7 is formed of metal. The high-speed followability of the memory circuit or memory circuit and its degree of integration are currently issues. In particular, with regard to high-speed followability, parasitic capacitance and parasitic resistance occur in the wiring portion, which hinders the operation.

On the other hand, research on superconducting materials has made remarkable progress in recent years.
As an application of this, it has been considered to apply superconducting material to the electrode wiring part of TFT, but in this case, the superconducting material must be formed separately, which not only complicates the process but also reduces yield. There was a problem.

〔the purpose〕

The present invention uses a superconducting material for at least the gate insulating film and the gate electrode portion of a MOS TFT formed on a semiconductor substrate, and this can shorten the process.
It is an object of the present invention to provide a semiconductor device with improved yield.

〔composition〕

The present invention provides an MO8 type TFT formed on a semiconductor substrate, in which at least the gate insulating film and the gate electrode are formed of a superconducting material, and the critical temperature of each superconducting material used for the electrode part and the insulating part is set at the electrode part. The insulating part is made higher than the insulating part, and the insulating part is operated between the critical temperatures of the two parts.

FIG. 1 shows an embodiment of the present invention. In this embodiment, a gate insulating film 4, a gate electrode 5, and an isolation layer 2 are formed of superconducting materials, and these are formed at the same time. , and then a gate insulating film 4. Gate electrode 5
And element isolation M2 is formed. The interlayer insulating film 6 is made of Sin as usual, and the source/drain electrodes 7 are made of a superconducting material.

Among the parts formed of these superconducting materials, the gate electrode 5 and source/drain electrode 7 which form the electrode part, and the gate insulating film 4 and the element isolation layer 2 which form the insulating part have a critical temperature that is higher than that of the electrode part. The composition has been changed so that the insulation part is higher than the insulation part. Therefore, when the TFT is operated at a temperature between the critical temperatures of the electrode portion and the insulating portion, the electrode portion exhibits a superconducting material and the insulating portion exhibits insulating properties.

In addition, in FIG. 1, the inter-element isolation layer 2 is also formed of a superconducting material, but this shows a configuration for further shortening the process.
It may be made of 5 in 2 like the conventional one, but in the present invention, it is sufficient that at least the gate insulating film 4 and the gate electrode 5 are made of a superconducting material.

Here, what is the superconducting material used in the present invention?

General formula RrXxZzDδAa (However, in the above formula, R is Sc, Y, La, and at least one element from the lanthanide group.

X is at least one element of group ■a.

Z is at least one transition metal element.

D is at least one group VIa element, A is B, C, N
, at least one of the elements F.

r is approximately 1.0 X is 164-2.1 2 is 2.4-3.2 δ is 5.9-9.0 α is O-0,5 May contain elements at the same time. ) (hereinafter referred to as compound S) can be used.

Compound S can be produced by various methods. For example, from the oxides and carbonates of the above-mentioned elements, dry method,
Mix fine powder by wet method. Next, it is calcined at a desired temperature and for a desired period of time in a furnace having a normal atmospheric atmosphere or an atmosphere with a controlled oxygen partial pressure. After cooling to room temperature and carefully grinding and mixing, approximately 30K
Pressure molded at a pressure equivalent to g, and in the same atmosphere and temperature as above.
Bake in time. These methods are outlined in the following documents.

■C,, Michel and B, Raeau,
Rev, ChimicMinera12i, 407
(1984) ■ J., G., Berdnorz and
K., A., Müller, Z.

Phys, Dan 64, 189 (1986) 0M, Wu
, J., R., Ashburn, C.J., Torng.
.

P, H, Hor, R, L, Meng, L, Gao;
Z, J, Huang, Y+Q, Wang and C,
W,Chu,Phys,Rev.

Lett, 58, 908 (1987) Another manufacturing method involves dispersing the compound S in a so-called binder such as alcohol or a water-soluble polymer with respect to the powder before or after calcination, and molding it into an arbitrary shape. Thereafter, other methods that can be used for baking under the conditions described above include screen printing, sputtering, single molecular beam epitaxial method, and plasma spraying. In these methods, by selecting the type and properties of the substrate, it is possible to improve the performance of the product due to the effect of epitaxy. Further, the properties of the product can be improved by further heat treating it under the above-mentioned firing conditions.

Compound S obtained in this way is described in the previous literature ■, ■
As is known in the art, it has good electrical conductivity and exhibits superconductivity when cooled to a certain temperature or lower. That is, at this time, in addition to superconductivity, it exhibits perfect diamagnetism and the Josephson effect.

Next, the manufacturing process of the MO8 type TFT shown in FIG. 1 will be explained with reference to the process flow shown in FIG.

A compound 5M11 consisting of Y-Ba-Cu-0 was deposited on a semiconductor substrate 1O to a thickness of 6000 by sputtering under conditions of peritoneal pressure of 1 and 0 Torr (Fig. 3(a)).
.

A resist was formed on the part of this compound S)H other than the element isolation layer, and o゛ ion implantation energy was 50 KeV.
Dose 5X10”/aJ and implant energy 120
Ion implantation is performed at a dose of 5 x 101 s/a# to form an isolation layer 12 (see Fig. 3).
b)) As a result, if the critical temperature of the initially formed compound S layer 11 is T, the composition changes due to o0 ion implantation, and the critical temperature becomes T□, which is lower than T.

Next, a portion of the inter-element isolation layer 12 is covered with a resist, and 0° ions are implanted at an energy of 12 (lKeV, a dose of 5).
By performing ion implantation with such high energy (FIG. 3(c)), the 0° ions are implanted into the deep part of the compound S layer 11,
In other words, the gate insulating film 13 is formed by reaching the part on the semiconductor substrate 10 side, changing the composition of the compound S layer 10 in that part, and setting the critical temperature to T2, which is lower than T.

In this way, the O° ion implantation is carried out into a relatively deep part of the compound 5M11, and therefore the ○° ion implantation is not carried out into a relatively shallow part of the compound S layer 11.

The compound S layer 11 remains. In other words, a gate electrode 14 having a critical temperature T is formed (see FIG. 3).
d)).

The surfaces that are to become the interelement isolation layer 12 and the gate electrode 14 are covered with resist, and the remaining compound S layer 11 is removed by etching (FIG. 3(e)). Next, P ion implantation energy of 50 KeV was applied to the entire surface.

Ions are implanted at a dose of 5×10 1 s/a# to form an n diffusion layer 15 (FIG. 3(f)).

A film forming pressure of 0.1 was applied to these surfaces by low pressure CVD method.
-10 Torr, film forming temperature 350℃ 2 reaction residue SiH4
Interlayer insulating film 16 made of SiO2 under the condition of +020N2
3(g)), a contact hole is opened in this interlayer insulating film 16 (FIG. 3(h)), and Y-Ba-Cu
Compound S consisting of -0 was prepared by sputtering,
The source/drain electrodes 17 are formed by forming a film with a thickness of 6,000 yen (FIG. 3(j)). Next, a 1 μm thick protective film 18 made of 5102 is formed on the entire surface under the same conditions as for forming the first interlayer insulating film 16 (FIG. 3 (j)). Here, a MOS type active element TFT as shown in FIG. 1 is obtained. It will be done.

FIG. 4 shows an example of application of the present invention, in which the gate insulating film, gate electrode, and source/drain electrodes are made of compound S in an SOI TFT in which the TFT is formed on a transparent insulating substrate.
The critical temperature of the gate electrode and source/drain electrode is higher than that of the gate insulating film.

In the process flow shown in Fig. 3, the critical temperature of the element isolation layer and gate insulating film was lowered by O゛ ion implantation, but the critical temperature could be lowered by changing the composition of the compound S, not just O゛ ions. Any ion implantation, metal or non-metal ions, may be used as long as it lowers the resistance.

As described above, the key point of the present invention is to form the compound S layer at one time, and then form the electrode portion separately in a subsequent step.

〔effect〕

According to the present invention as described above, at least the gate insulating film and the gate electrode of the MO3 type TFT can be formed at the same time, the process can be shortened, and the yield can be improved. Furthermore, by using a superconducting material, it is possible to impart superconducting characteristics to the electrode section, allowing the switching element section and peripheral wiring section to be integrally formed, and the zero resistance characteristic makes it possible to further route the wiring. This can be said to pave the way for three-dimensional wiring and one-way computers. Furthermore, since a single element can be manufactured with a size of 40 μm or less, various types of LS1. When applied to COD, 1x sensors, liquid crystal displays, liquid crystal printers, etc., it has the effect that these can be miniaturized.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view ζ showing one embodiment of the present invention. FIG. 2 is a cross-sectional explanatory diagram of a conventional example. FIG. 3 is a process flow for manufacturing the example device shown in FIG. 1. FIG. 4 is an explanatory cross-sectional view showing an application example of the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate 2... Inter-element isolation layer 3... Diffusion layer 4... Gate insulating film 5... Gate electrode 6... Interlayer insulating film 7... Source/drain electrode 10. ...Semiconductor substrate 11...Compound S layer 12...
- Inter-element isolation layer 13...gate insulating film 14...gate electrode 15...diffusion layer 16...interlayer insulating film 17
...Source/drain electrode 18...Protective film

Claims (1)

[Claims] 1. In a MOS TFT formed on a semiconductor substrate, at least the gate insulating film and the gate electrode are formed of a superconducting material, and the critical temperature of each superconducting material used for the electrode part and the insulating part is set to 1. A semiconductor device characterized in that the insulating part is higher than the insulating part, and the semiconductor device is operated between the critical temperatures of these two parts.