JPH01120860A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To reduce additional capacity of an input terminal or an output terminal and allow overvoltage protection without degradation of performance of a protective circuit by providing a new p-n junction between the input terminal or the output terminal in a semiconductor circuit and an overvoltage protective means and arranging the new p-n junction in the forward direction with respect to a prescribed constant voltage power source. CONSTITUTION:A first p-n junction between a p<+> dispersion area 32 of an NPN transistor 22 and a N<+> dispersion layer 33 and a second p-n junction between an epitaxis 30 of a transistor 23 and the p<+> dispersion area 32 are connected between an output terminal SOUT and the minimum voltage in series. Further, on the p-n junction the first p-n junction has the forward direction with respect to a prescribed constant voltage source (for example, earth potential) and the second p-n junction has the reverse direction. Thus, the second p-n junction forms a conducting overvoltage protective means 35 when the voltage more than breakdown voltage is applied on the output terminal SOUT. Therefore, additional capacity CB attached to the output terminal SOUT is only comparatively small, the additional capacity can be reduced and performance degradation of the protecting target circuit can be avoided.

Description

[Detailed description of the invention] [Summary] Semiconductor circuits, especially ESD (ESD: E
lectr.

5tatic Discharge (electrostatic discharge) The purpose of this is to reduce the additional capacitance of the input terminal or output terminal and provide overvoltage protection without deteriorating the performance of the circuit to be protected. An overvoltage protection means is inserted between the output terminal and the lowest potential, and when the voltage applied to the terminal exceeds the breakdown characteristics of the PN junction, the PN junction becomes conductive and connects the voltage to the lowest potential. In the semiconductor circuit, a new PN junction is provided between the input terminal or the output terminal and the overvoltage protection means, and the new PN junction is arranged in a forward direction with respect to a predetermined constant voltage source.

[Industrial application field]

The present invention relates to semiconductor circuits, and particularly to ESD (ESD)
: Electro 5tatic Discharg
e) Regarding semiconductor circuits for which countermeasures have been taken against electrostatic discharge.

In recent years, the degree of integration of semiconductor circuits has been increasing with advances in microfabrication technology, but on the other hand, miniaturization of circuits tends to reduce the electrostatic breakdown resistance. Throughout the course, so-called ESD countermeasures have become increasingly important.

[Conventional technology]

An example of a conventional semiconductor circuit in which this type of ESD countermeasure has been taken is shown in FIG.

In this example, the collector of an NPN transistor 2 is connected to the output terminal 5oot of a predetermined logic circuit (ie, a target circuit to be protected from ESD) 1, and the base of the NPN transistor 2 and the emitter are commonly grounded. This N
PN) transistor 2 acts as a collector-base Zener diode and becomes conductive when a voltage higher than the breakdown voltage is applied between the collector and base. That is, during normal operation, the logic output of the logic circuit I is below the breakdown voltage of the NPN transistor 2, so the NPN transistor 2 does not conduct, but an extremely excessive voltage due to electrostatic discharge from the outside is applied to the output terminal S. When applied to ur, it becomes conductive and protects the logic circuit 1 by bypassing this overvoltage.

Therefore, it is desired that the NPN transistor 2 operates quickly when an excessive voltage is applied, and that the performance of the logic circuit 1 is not deteriorated during other normal times. In addition, in FIG. 5, Tr+ and Trt are logic circuit 1.
, R1 is a resistor, and Vcc is a constant power supply.

[Problem that the invention seeks to solve]

However, in such conventional semiconductor circuits, overvoltage due to electrostatic discharge is handled by a single NPN transistor 2.
Since the configuration was to bypass using
There were problems such as an increase in the additional capacity of the circuit, leading to a deterioration of the slew rate.

FIG. 6 is a conceptual diagram showing the structure of the NPN transistor 2. NPN) transistor 2 is mounted on a p-type single crystal substrate (hereinafter referred to as substrate) 3.

A buried layer 4 is formed, and an n-type layer (hereinafter referred to as epitaxial layer) 5 is grown on the upper surface of the substrate 3, and this epitaxial layer 5 is partitioned with a p-type isolation layer (hereinafter referred to as isolation layer) 6. It forms two islands. An n° diffusion region 7 and a p diffusion region 8 are formed in this one island, and further, an n° diffusion region 9 is formed in the p diffusion region 8.

Each of these diffusion regions is connected to an output terminal S as shown in FIG. u
The collector electrode wiring 10 connected to the T, the base electrode wiring 11 and the emitter electrode wiring 12 to be grounded are deposited, whereby the epitaxial layer 5 and the n' diffusion region 7 are connected to the collector region and the p diffusion region 8. is the base area,
The n'' diffusion region 9 becomes an emitter region, and one island as a whole constitutes an NPN transistor 2. Note that the substrate 3 is grounded.

In this way, in the transistor 2 formed on the common substrate 3 and consisting of one island separated by the isolation 6, in order to separate the substrate 3 and the island, the epitaxial 5 and the substrate 30 is used with reverse bias. ``Therefore, a capacitive reactance CI is generated in the reverse biased PN junction between the buried layer 4 and the substrate 3, and a reverse bias is also generated between the epitaxial layer 5 and the p diffusion region 8, that is, between the collector base. A capacitive reactance Ct is also generated in the PN junction between the levers.

These CI and C2 are inserted in parallel between the collector and ground, and as a result, this parallel combined capacitance Ca
(Ca = C+ + Cz) is collector electrode wiring 1
0 to the output terminal 5our in FIG. 5, deteriorating the signal output characteristics of the logic circuit 1.

That is, a part of the output of the logic circuit 1 is connected to the parallel composite capacitor 1c.
Since it is used to charge and discharge A, there are problems such as deterioration of the output frequency characteristics and rounding of the waveform, and furthermore, the signal slew rate is deteriorated due to the charging and discharging time constant.

The present invention was made in view of these problems, and
The purpose is to reduce the additional capacitance attached to the input or output terminals and provide overvoltage protection without deteriorating the performance of the protected circuit.

[Means for solving problems]

In the present invention, in order to achieve the above object, a terminal is inserted between an input terminal or an output terminal and the lowest potential (substrate potential), and when the voltage applied to the terminal exceeds the breakdown characteristics of the PN junction. , in a semiconductor circuit equipped with an overvoltage protection means in which a PN junction conducts and connects the voltage to a predetermined constant voltage source, a new PN junction is provided between the input terminal or the output terminal and the overvoltage protection means; The new PN junction is arranged in the forward direction with respect to a predetermined constant voltage source.

[For production]

In the present invention, a new PN junction is provided between the input terminal or output terminal and the overvoltage protection means, and the capacitance between this PN junction and the lowest potential (substrate potential) becomes the additional capacitance of the input terminal or output terminal. .

In other words, the overvoltage protection means are normally (when no overvoltage is applied)
, is non-conducting, and therefore the new PN junction is also non-conducting, separating the input or output terminal from the overvoltage protection means, so that the relatively large capacitance of this overvoltage protection means is not connected to the input or output terminal. is not added to.

In addition, the new PN junction has a smaller pattern than the overvoltage protection means, so its capacitance is also smaller, and therefore,
By reducing the additional capacitance attached to the input terminal or output terminal, it is possible to improve the slew rate, etc. of the circuit to be protected.

Furthermore, when an overvoltage is applied, since the new PN junction is in the forward direction, this voltage can be quickly transmitted to the ONL and the overvoltage protection means. Therefore, even though a new PN junction is added, there is no problem in the function of protecting the circuit from overvoltage caused by electrostatic discharge or the like.

〔Example〕

Hereinafter, the present invention will be explained based on the drawings.

1 to 4 are diagrams showing one embodiment of a semiconductor circuit according to the present invention, and are examples in which the present invention is applied to a semiconductor circuit formed on one chip.

First, the configuration will be explained. In FIG. 1, 20 is a circuit to be protected, and the circuit 20 to be protected is, for example, a pull-up transistor T between a constant power supply Vcc and the ground.
'r21, has an output stage in which a pull-down transistor Tr2□ and a pull-down resistor R21 are connected as a totem pole, and outputs a TTL level logic signal to an output terminal S. Output from LIT to outside the chip. Output terminal S. An electrostatic protection circuit 21 is connected to U7, and the electrostatic protection circuit 21 consists of two NPN)
It is composed of transistors 22 and 23. In addition,
C3 is an additional capacitance of the output terminal 5out.

FIG. 2 is a conceptual diagram partially showing the structure of the chip. In the figure, on a common p-type vehicle crystal substrate (hereinafter referred to as substrate) 24, there are an n+ buried layer 25, 25' and a p-type
9 isolation layer (hereinafter referred to as isolation) 26.27
．． Two n-type layers (hereinafter referred to as epitaxial layers) 29.30 partitioned into 28 are formed, and each of these epitaxial layers 29.30 has an n1 diffusion region 31.31.
', p diffusion region 32.32' and n+ diffusion region 33.
33' is formed.

Then, the epitaxial layer 29 covers the collector region C along with the n diffusion region 31. The n diffusion region 32 is the base region B.
, the n+ diffusion region 33 forms an emitter region E to constitute the NPN transistor 22 in FIG. 1, and
The epitaxial layer 30 together with the n+ diffusion region 31' forms a collector region C', the n diffusion region 32' forms a base region B', and the n° diffusion region 33' forms an emitter region E'. It constitutes 23. Note that Cff' is the capacitance of the NPNI transistor 22.

The collector C and base B of the NPN l-transistor 22 are made common and output terminal S in FIG. The emitter E is connected to the collector C' of an NPN transistor 23. And NPN transistor 2
The base B' and emitter E' of No. 3 are commonly connected to the lowest potential (ground potential in this embodiment).

In other words, there is an N between the output terminal 5O(l and the lowest potential).
PN) p diffusion region 32 of transistor 22 and n" diffusion 1i
33 (hereinafter referred to as the first PN junction),
Two PN junctions (hereinafter referred to as second PN junctions) between the epitaxial layer 30 of the NPN transistor 23 and the p' diffusion region 32' are connected in series. Further, in these PN junctions, the tenth PN junction is in the forward direction with respect to a predetermined constant voltage source (ground potential in this embodiment), while the second
The N junction is in the opposite direction.

Therefore, the second PN junction is the output terminal S. . The second PN junction forms a new PN junction 36 arranged in the forward direction with respect to a predetermined constant voltage source. is formed.

Note that the pattern area ratio of the NPN) transistor 22 and the NPN) transistor 23 is set to be larger on the NPN transistor 23 side, as shown in the respective pattern diagrams in FIG. 3.4.

Next, the effect will be explained.

Now output terminal S. In the normal state where no overvoltage is applied to uT, the NPN transistor 23 is in the OFF state, and the NPN transistor 22 and the NPN transistor 2
It is separated from 3 in terms of DC. Therefore, if the pull-up transistor TrH of the circuit 20 to be protected is turned on,
output terminal S. Even if U7 rises to the constant power supply Vce, the bias voltage (constant power supply Vcc) is applied between the epitaxial layer 30 of the NPN transistor 23 and the substrate
) is not applied and no capacitance is generated.

On the other hand, a bias voltage (constant power supply V
cc) is applied, which generates a capacitance C1', but the size of this capacitance C,/ is NPN)
Since the pattern area of transistor 2 is smaller than that of NPN transistor 23, it is sufficiently small. Therefore, the output terminal s
The additional capacitance C3 attached to out is only this relatively small capacitance C8', and the additional capacitance can be significantly reduced compared to the conventional case, and performance deterioration of the circuit to be protected can be avoided.

Also, the output terminal S. When an overvoltage is applied to 1,
When this overvoltage exceeds the breakdown characteristic of the overvoltage protection means 34, the new PN junction 36 disposed in the forward direction and the overvoltage protection means 35 are immediately brought into conduction, and the output terminal S is connected. Connect Ua to the lowest potential. Therefore, overvoltage is not applied to the circuit 20 to be protected, but is absorbed by the lowest potential side, and as a result, as in the past, the circuit 20 to be protected from overvoltage
0 can be protected.

In the above embodiment, the electrostatic protection circuit 21 is connected to the output terminal 5 (10?), but the electrostatic protection circuit 21 is not limited to this, and it goes without saying that the output terminal 5 (10?) may be connected to the input terminal, for example.

〔Effect of the invention〕

According to the present invention, when no overvoltage is applied to the input or output terminals: 1. Since the new PN junction and overvoltage protection means are separated, the additional capacitance attached to the input terminal or output terminal can be reduced to only the new PN junction capacitance, significantly increasing the additional capacitance compared to conventional methods. can be reduced.

Therefore, the performance of the circuit to be protected, such as the slew rate, can be improved.

Furthermore, since the new PN junction is in the forward direction with respect to overvoltage, it does not interfere with the operation of the overvoltage protection means.

[Brief explanation of the drawing]

1 to 4 are diagrams showing one embodiment of a semiconductor circuit according to the present invention, FIG. 1 is a circuit diagram thereof, and FIG. 2 is a diagram showing an NPN) transistor 22 and an NPN
FIG. 3.4 is a conceptual diagram showing the structure of the transistor 23, FIG. 3.4 is a pattern diagram of each of the NPN) transistor 22 and NPN) transistor 23 in FIG. 1, and FIG. 5.6 is a diagram showing a conventional semiconductor circuit. FIG. 5 is a circuit diagram thereof, and FIG. 6 is a conceptual diagram showing the structure of the NPN transistor 2 shown in FIG. " 21... Electrostatic protection circuit, 35...
・Overvoltage protection means (PN junction), 36... New PN junction, 5out... Output terminal.

Claims (1)

[Claims] When the voltage applied to the terminal inserted between the input terminal or output terminal and the lowest potential (substrate potential) exceeds the breakdown characteristic of the PN junction, the PN junction becomes conductive. In a semiconductor circuit equipped with an overvoltage protection means for connecting a voltage to a lowest potential, a new PN junction is provided between the input terminal or the output terminal and the overvoltage protection means, and the new PN junction is connected to a predetermined constant voltage source. A semiconductor circuit characterized in that it is arranged in a forward direction relative to the semiconductor circuit.