JPH01120649A - Cache memory control system - Google Patents

Abstract

PURPOSE:To improve the cache hit rate of the data requiring a high access speed by transferring the information that limits an access range when an access is given to a cache memory and deciding the mishit. CONSTITUTION:A request address received from a host device is stored in an address register 2 of a cache memory. At the same time a level showing a specific level of the cache memory that is desired by the relevant request is stored in a level designation register 1. Then a comparator 6 compares the contents of the register 2 with those of an address array 5. The valid conditions are secured between each output of the comparator 6 and the output of the register 1 via a gate group 7. In case the coincidence is secured between both outputs at a level designated at the register 1, the relevant level 1 is stored in a hit level register 8 and used as an access level of the next data array 10.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device, and particularly to a cache storage control method.

[Conventional technology]

A concept called cache is used to bridge the difference between the processing cycle of a processor (for example, CPU) and the access speed of mass storage (for example, main memory). This concept involves preparing a memory that has a relatively small capacity but whose access speed matches the processing cycles of the processor, and stores a copy of the contents of the mass storage in that memory. Typically, cache storage is organized into blocks, with each block holding a copy of the mass storage.

[Problem that the invention seeks to solve]

The policy of which main memory contents to hold in this block of cache storage is that when the requested mass storage contents are not contained in any block in cache storage, the most recently accessed block is Instead, a method is often used to buffer blocks containing the requested mass storage contents in cache storage.

This is LRU” (Least Recently
This is called the (Used) management method.

However, in conventional cache storage, the above management method is applied equally to all access requests and all blocks, so even if the access frequency is not high, the storage content (where access speed determines system performance) For example, interrupt handlers for real-time control, etc.) have a low probability of being present in the cache memory when they are needed according to the LRU principle described above, and the performance of the system may deteriorate.

Furthermore, when data with high locality of access (for example, instructions) and data with low locality of access (for example, pointer structures) coexist, access to the latter causes frequent cache misses, which in turn reduces the cache hit rate of the former. There is a possibility that

In this case, cache storage has little effect on the latter access, and cache capacity is often not an important factor for the latter access.

[Means for solving problems]

The cache storage control method of the present invention sends, along with an access request to a cache storage device, information that limits the existence range in the cache storage device of the storage content that the access request attempts to access. limits the buffering range of the contents of the mass storage using information that limits the existence range, and
This is to enable a signal indicating the existence of the storage content to be accessed within the existence range.

[For production]

Therefore, it is possible to increase the cache hit rate of data that is not accessed frequently, but whose access speed determines system performance, and improve system performance. Even in cases where there is a mixture of accesses, by separating data with high locality from data with low locality, the latter accesses will not cause frequent cache misses, and the latter accesses will not disturb the former accesses. be able to.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of a cache storage device to which the cache storage control method of the present invention is applied. Here, a four-level set associative cache storage will be explained as an example.

In the cache memory, a request address from a higher-level device (for example, an arithmetic unit) is stored in an address register 2, and a level indicating which level of the cache memory the request is directed to is stored in a level specification register 1. Store. Next, the contents of the address register 2 are checked for coincidence with the contents of the address array 5 by the comparator group 6 in a set-associative manner. Validity conditions are taken for each output of the comparator group 6 by the output of the level designation register 1 and the gate group 7. Here, if a match is found among the levels specified in level specification register 1 (cache hit), that level is stored in hit level register 8, and in the next step data array IO Used as an access level. The data read from the data array IO is stored in the cache read register 13, and the data is returned to the request source.

If the output of each level of the comparator group 6 does not indicate a match among the levels specified by the level specification register 1 when the valid condition is taken in the gate group 7, the cache memory is determined as a "cache miss" condition. Swaps the blocks within. At this time, which block to replace is determined by the LRU of each level within the set, which is uniquely determined by the request address.
Assume that it is a block. Therefore, at the time of a cache hit, the LRURAM 9 is rewritten using the contents of the address register 4 and the hit level register 8 in the cycle in which the data array 10 is accessed so that the level stored in the hit level register 8 is the latest access level. There is.

At the time of a cache miss, the LRURAM 9 is read and the level most recently accessed by the decoding circuit 11 (LRU level) is outputted and stored in the replacement level register 12. However, in the conventional cache memory device, the LRU level among all levels is replaced, but in the present invention, the LRU level is determined within the level indicated by the level designation register 3 at the same stage as the address register 4. That is, in the past, the LRU level was determined from the context of accesses of all levels stored in the LRURAM 9, but in the present invention, the decoding circuit II determines the context of accesses between levels specified by the level designation register 3. The LRU level is determined from This allows data to be stored only at a particular level within cache storage by always accompanying a certain type of request with the same level specification. A level that is not specified is, from the point of view of the request,
It looks as if they are separated.

〔Effect of the invention〕

As explained above, the present invention sends, along with an access request to a cache storage device, information that limits the existence range in the cache storage device of the storage content that the access request attempts to access. By determining hits and misses within the information and determining the replacement level, we can increase the cache pit rate for data that is accessed infrequently but requires high access speed when accessing, and improve data that has high locality of access. By separating low and low data, it is possible to prevent the latter access from disturbing the former access.

[Brief explanation of the drawing]

FIG. 2 is a configuration diagram of an embodiment of a cache storage device to which the cache storage control method of the present invention shown in FIG. 1 is applied. 1.3--Level specification register, 2.4--Address register, 5--Address array, 6--Comparator group, 7--Gate group, 8...
・Hira level register, 9-LRURAM, lO-・data array, 11-・decode circuit, 12--replacement level register, 13--cache read register.

Claims (1)

[Scope of Claims] In a relatively high-speed, small-capacity cache storage device that associatively buffers the contents of relatively low-speed, large-capacity mass storage, the access Sending information that limits the existence range of the storage content that the request attempts to access in the cache storage device;
The cache storage device limits the range in which the content of the mass storage is buffered based on the information that limits the existence range, and enables a signal indicating the existence of the storage content to be accessed within the existence range. cache control method.