JPH01119994A - Sample-and-hold circuit - Google Patents

Abstract

PURPOSE:To decrease an A/D conversion error due to the generation of a noise by sufficiently enlarging the area of the P-N linking part of a diode laid between an input terminal and the power source of a circuit and/or a ground compared with the area of the P-N linking part of a source diffusion layer of a MOS electric field effect transistor (TR) consisting of an analog switch. CONSTITUTION:Between analog input terminals AN0 and AN1 and a power source VDD of a sample holding circuit and/or a ground, diodes D11-D14 are laid. For the P-N linking part of the diodes D11-D14, the area is sufficiently larger compared with the P-N linking part of the source diffusion layer of MOS electric field effect TRs T11-T14. Thus, even when the voltage higher than a supply voltage or lower than the grounding potential is impressed to one of an analog input terminal due to the generation of the noise during an A/D conversion, the generation of the A/D conversion error can be evated.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to an analog voltage sample-and-hold circuit installed on a semiconductor substrate, and more specifically, for example, to a sample-and-hold circuit for analog voltage used in an A/D converter. If the fluctuation of the sampled and held analog voltage is small, C
The present invention relates to an analog voltage sample and hold circuit made up of MOS.

BACKGROUND OF THE INVENTION FIG. 4 shows the configuration of an A/D converter including a conventional analog voltage sample and hold circuit realized on a semiconductor substrate.

The illustrated A/D converter has two analog input terminals A
It is equipped with N o and A N l. The two analog input terminals ANo and A N + are connected to an input resistor R4.
1 and one end of R42 are connected to each other.

The other end of the input resistor R41 is commonly connected to the anode of the diode D41 and the cathode of the diode D42. The cathode of the diode D41 is connected to the power supply VOO, and the anode of the diode D4□ is connected to the ground. That is, two guides D0 and D4
□ is the power supply V. It is connected in series between 0 and ground.

The other end of the input resistor R4□ is commonly connected to the anode of the diode D43 and the cathode of the diode D44. The cathode of the diode D43 is connected to the power source V o .

The anodes of the diodes D44 are respectively connected to ground. That is, two diodes D
43 and D44 are power supply V. , are connected in series between , and ground.

The illustrated A/D converter includes an A/D conversion circuit 41. One input of the A/D conversion circuit 41 and the input resistance R
41, an N-channel type MOS field effect transistor T41 and a P-channel type MO8 field effect transistor T42 are connected in parallel. Transistor'I
"41 and T42 constitute one 0MOS.A/
An N-channel M○S field effect transistor T4 is connected between one input of the D conversion circuit 41 and the other end of the input resistor R42.
3 and a P-channel type MO8 field effect transistor T44 are connected in parallel. Transistors T43 and T44
constitutes one 0MOS.

One output signal 43 of the control circuit 42 is connected directly to the gate of the transistor T41 and via an inverter 45 to the gate of the transistor T42.

The other output signal 44 of the control circuit 42 is connected directly to the gate of the transistor T43 and via an inverter 46 to the gate of the transistor T44.

The output signal 47 of the control circuit 42 is input to the other input of the A/D conversion circuit 41. A capacitor C for sampling and holding analog pressure is connected between one input of the A/D conversion circuit 41 and the ground. A'
/D conversion circuit 41 outputs digital signal 48.

The A/D converter configured as described above operates as follows.The control circuit 42 receives the signal 43 from the analog input terminal AN.

This is a sampling signal for sampling the analog voltage applied to the transistor T41, and is input to the gate of the transistor T41 and the inverter 45. The output of the inverter 45 is input to the gate of the transistor T42. When the sampling signal 43 becomes high level, the transistor T41 is turned on, and the output of the inverter 45 becomes low level, and the transistor T4□ is turned on. In this way, the analog voltage applied to the analog input terminal ANo is applied to the input resistor R41, the transistor T4. and is charged to capacitor C via T4□.

Similarly, the signal 44 is a sampling signal for sampling the analog voltage applied to the analog input terminal A N + and is input to the gate of the transistor T43 and the inverter 46. The output of the inverter 46 is input to the gate of the transistor T44.

When the sampling signal 44 becomes high level, the transistor T43 is turned on, and when the output of the inverter 46 becomes low level, the transistor T44 is turned on. In this way, the capacitor C is charged via the input resistor R4□ and the transistors T41 and T44.

Sampling signals 43 and 44 are selectively generated by control circuit 42. A signal 47 is a signal that causes the A/D conversion circuit 41 to start converting the analog voltage sampled and held by the capacitor C into a digital value. A control circuit 42 generates a sampling signal 43 or 44 and outputs a sampling signal 43 or 44 to an analog input terminal ANO or AN.

Sample and hold the analog voltage of
Get 8.

FIG. 5 shows cross sections of semiconductor substrates of N-channel type and P-channel type MO8 field effect transistors T43 and T44. Figure 5 shows the circuit from analog input terminal AN1 to sample hold capacitor C, and transistor T4.
3 and T44 cross sections are shown. The N-channel field effect transistor T43 includes an NPN parasitic transistor Tr43, and the P-channel field effect transistor T4L
A PNP parasitic transistor Tr44 is formed at.

Therefore, in the following cases, each parasitic transistor has the following adverse effects. Below, the analog voltage of analog input terminal ANo is sampled and held,
Assume that A/D conversion is in progress.

(1) The power supply voltage V is applied to the analog input terminal A Nl due to noise, etc. , if a higher voltage is applied.

The applied voltage is the power supply voltage V. , when the forward voltage of the diode (about 0.7V) increases, the parasitic transistor T
The emitter current of r44 flows. Since this parasitic transistor Tr44 operates with a common base, a collector current that is α (common base current amplification factor <1) times the emitter current flows. This collector current causes the analog voltage value sampled and held in the capacitor C to fluctuate.

(2) When a voltage lower than the ground potential is applied. When the voltage becomes lower than the ground potential by the forward voltage (about 0.7V),
A negative current flows through the emitter of the parasitic transistor Tr43. In this case, as in (1), it operates with a common base, so a collector current that is α times the emitter current flows.
After all, the sampled and held analog voltage value fluctuates.

The above voltage fluctuation causes an error in A/D conversion.

Problems to be Solved by the Invention As mentioned above, in A/D converters including conventional analog voltage sample and hold circuits, CMOS field effect transistors are formed. Therefore, due to the occurrence of noise, etc., the power supply voltage VDD
There is a problem in that when a higher voltage or a voltage lower than ground potential is applied to the analog input terminal, the parasitic transistor has an adverse effect on the analog voltage value. Although the above-mentioned A/D converter is equipped with a diode, the diode is originally for electrostatic discharge protection, and cannot exhibit the effect of reducing emitter current.

Therefore, the present invention is not only used for electrostatic damage protection.
The above diode has the effect of improving noise resistance performance, and when used in an A/D converter, for example, it is a CMO with small fluctuations in the sampled and held analog voltage.
The present invention aims to provide an analog voltage sample and hold circuit composed of S.

Means for solving the problem, that is, according to the present invention, an analog switch composed of an input terminal, an input resistor, and a CMOS, and a capacitor for sampling and holding the analog voltage applied to the input terminal are mounted on a semiconductor substrate. In the analog voltage sample and hold circuit provided above, a diode is provided between the input terminal and the power supply and/or ground of the circuit, and the PN junction of the diode connects to the MOS that constitutes the analog switch. A sample and hold circuit is provided which is characterized by having a sufficiently larger area than a PN junction of a source diffusion layer of a field effect transistor.

Embodiments Hereinafter, embodiments of an A/D converter including an analog voltage sample and hold circuit of the present invention will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of an A/D converter including an analog voltage sample and hold circuit according to the present invention.

The illustrated A/D converter has two analog input terminals A
N, ) and A N +. One ends of input resistors R1+ and RI2 are connected to the two analog input terminals ANII+ and AN, respectively.

The analog input terminal ANo is further commonly connected to the anode of the diode D1 and the cathode of the diode D1□. The cathode of diode DI+ is the power supply VDf
1 and the anode of the diode D1□ are connected to ground, respectively. That is, two diodes D1
1 and D1□ are connected in series between the power supply VDD and ground.

The analog input terminal A N + is further connected to the diode D
It is commonly connected to the anode of I3 and the cathode of diode DI4. The cathode of the diode DI3 is connected to the power supply VB, and the anode of the diode DI4 is connected to the ground. That is, two diodes D
13 and DI4 are connected in series between the power supply Vt1Ill and ground.

The illustrated A/D converter includes an A/D conversion circuit 11. One input of the A/D conversion circuit 11 and the input resistance R
11, an N-channel type MO8 field effect transistor Tll and a P-channel type MOS field effect transistor TI2 are connected in parallel. N is connected between one input of the Δ/D conversion circuit 11 and the other end of the input resistor RI□.
A channel type MOS field effect transistor TI3 and a P channel type MOS field effect transistor TI4 are connected in parallel. Transistors Tl+ and 'I''+2 are 1
transistors TI3 and TI4.
constitutes one CMO8.

A capacitor C for sampling and holding analog pressure is connected between the above-mentioned one input of the A/D conversion circuit 11 and the ground.

One output signal 13 of the control circuit 12 is connected directly to the gate of the transistor T11 and via an inverter 15 to the gate of the transistor T+2.

The other output signal 14 of the control circuit 12 is connected directly to the gate of the transistor TI3 and via an inverter 16 to the gate of the transistor TI4.

The output signal 17 of the control circuit 12 is input to the other input of the A/D conversion circuit 11. A/D conversion circuit 11 outputs digital signal 18.

The A/D converter configured as described above operates as follows.

The signal 13 is a sampling signal used by the control circuit 12 to sample the analog voltage applied to the analog input terminal ANO, and is input to the gate of the transistor Tll and the inverter 15. The output of the inverter 15 is input to the gate of the transistor T+□. When the sampling signal 13 becomes high level, the transistor TI+ is turned on, the output of the inverter 15 becomes low level, and the transistor T1□ is turned on. In this way, the analog voltage applied to the analog input terminal ANo is charged to the capacitor C via the input resistor R11 and the transistors T+□ and T1°.

Similarly, the signal 14 is a sampling signal for sampling the analog voltage applied to the analog input terminal A N + and is input to the gate of the transistor TI3 and the inverter 16. The output of the inverter 16 is input to the gate of the transistor TI4.

When the sampling signal 14 becomes high level, the transistor TI3 is turned on, and the output of the inverter 16 becomes low level, turning on the transistor T1.4. In this way, the capacitor C is charged via the input resistor R1□ and the transistors TI3 and TI4.

Sampling signals 13 and 14 are selectively generated by control circuit 12. The signal 17 is a signal that causes the A/D conversion circuit 11 to start converting the analog voltage sampled and held by the capacitor C into a digital value. The control circuit 11 generates a sampling signal 13 or 14 and outputs a sampling signal 13 or 14 to an analog input terminal A No or AN.

Sample and hold the analog voltage of
Get 8. As described above, the basic operation of the A/D converter is the same as in the conventional example.

Next, it is assumed that the analog voltage at the analog input terminal A N o is sampled and held and A/D conversion is being performed, and the influence when noise is added to the analog voltage at the analog input terminal A N + will be described in detail.

(1) When a voltage higher than the power supply voltage VDD is applied to the analog input terminal A N + due to noise generation, etc.

FIG. 2 shows a diode DI3 and a transistor TI4.
A circuit diagram from the analog input terminal A N + to the sample-and-hold capacitor C is shown, including a cross-sectional view of (the diode DI4 and the transistor T13 are not shown). As in the conventional example, a PNP parasitic transistor Tr+4 is formed in the transistors T and 4.

The diode DI3 is easily connected to the analog input terminal AN and the power supply VIIID, and the PN of the diode DI3 is connected to the analog input terminal AN and the power supply VIIID.
The junction is formed to be sufficiently larger (for example, 10 times) than the PN junction of the source diffusion layer of transistor TI4.

When a voltage higher than the power supply voltage Vt1tl by the forward voltage of the diode (approximately 0.7 V) is applied to the analog input terminal AN, the resistance of the diode DI3 is R913, and the current is 1.13. Let REI4 be the emitter resistance of the parasitic transistor T r +4, and I E+4 be the emitter current flowing through the input resistor R1□. In this case, as mentioned above, the area ratio of the PN junction is 10 times, so Rtl13
is negligibly small compared to REI4, so R
11: , +R, □”RDll.

In this way, by dividing the resistance, 1□, ci, .

Therefore, the emitter current 11!11 becomes very small.

Therefore, the collector current also becomes very small, and fluctuations in the analog voltage sampled and held in the capacitor C also become negligibly small.

(2) When a voltage lower than the ground potential is applied.

FIG. 3 shows diode D14 and transistor TI3.
The circuit from the analog input terminal A N + to the sample-and-hold capacitor C is shown, including a cross-sectional view of (the diode D I 3 and the transistor TI 4 are not shown). A parasitic transistor Tr+3 is formed in the transistor TI3. Diode DI4 is analog input terminal A N
+ and ground, and the diode DI4
PN junction of transistor T:.

It is formed to be sufficiently larger (for example, 10 times) than the PN junction of the source diffusion layer.

Therefore, the resistance of the diode DI4 is R914, the current is 1014, and the emitter connections of the parasitic transistors Tr, , are R1! l8, the emitter current flowing through the input resistor RI2 is 11! If +3, the area ratio of the PN junction is 10 times as described above, so Rnx is negligibly small compared to RF:I3, and RI! + 3 + Rr□
)RIll14. As a result, the shunt ratio of this resistor becomes i, , (i, , ,), and the emitter current 1
8.3 becomes very small. In this way, the collector current becomes very small, and the fluctuations in the analog voltage sampled and held in the capacitor C become negligibly small.

As described above, the A/D conversion error caused by the generation of noise becomes negligibly small.

The analog voltage sample and hold circuit of the present invention can also be applied to other integrated circuit devices having the same circuit, such as analog comparators.

As described in detail, in the A/D converter including the analog voltage sample and hold circuit of the present invention, during A/D conversion, one analog input terminal receives a voltage higher than the power supply voltage or Even if a voltage lower than ground potential is applied, no significant A/D conversion error occurs.

Therefore, the analog voltage sample and hold circuit of the present invention can be utilized in a wide range of fields.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of one embodiment of an A/D converter including an analog voltage sample and hold circuit of the present invention, and FIG. 2 is a cross-sectional view of the diode DI3 and transistor TI4 in FIG. Analog input terminal AN including. 3 is a circuit diagram from analog input terminal AN to capacitor C, which also includes a cross-sectional view of diode DI4 and transistor TI3, and FIG. 4 is a circuit diagram of conventional analog voltage 5 is a block diagram showing the configuration of an A/D converter including a sample and hold circuit of transistors T43 and T4. 2 is a circuit diagram from analog input terminal AN to capacitor C, including a cross-sectional view of FIG. (Main reference numbers) A No, A N r ...Analog input terminal,
DIl~DI4・・Diode, van・・
Power supply, RI+, 'R1□...Input resistance, Rs l, R42...Input resistance, C...Sample and hold capacitor, Tll, TI
3...N-channel type MOS field effect transistor, TI2. TI4...P channel type MOS field effect transistor, T<+, T4s...N channel type MOS field effect transistor, T4□, T44...P channel type MOS field effect transistor,

Claims (1)

[Claims] (1) In an analog voltage sample-and-hold circuit equipped on a semiconductor substrate with an analog switch composed of an input terminal, an input resistor, and a CMOS, and a capacitor that samples and holds the analog voltage applied to the input terminal, A diode is provided between the input terminal and the power supply and/or ground of the circuit, and the PN junction of the diode connects to the MOS that constitutes the analog switch.
A sample hold circuit characterized in that its area is sufficiently larger than that of a PN junction of a source diffusion layer of a field effect transistor.