JPH01118967A - Picture processor - Google Patents

Abstract

PURPOSE:To increase the picture processing speed by obtaining a wire frame picture in the optional direction of a 3-dimensional binary picture via the 2-dimensional gradation picture processing. CONSTITUTION:The binary pictures w1-wn of each section (n sections) of a 3-dimensional binary picture are stored in the frame memories 15-1-15-n in the form of the 8-bit picture data whose value is equal to 0 or 1 for each picture element. Then the contour lines of each section of the 3-dimensional binary picture are stacked on each other and a wire frame picture ww is obtained in the optional direction where the line (hidden line) overlapping another section is erased with a 2-dimensional gradation picture defined as a subject in case the binary pictures of the hitherto sections, e.g., the pictures ww for w1-wi-1, for example, are obtained in a frame memory 16-2. Thus a 2-dimensional picture processor can be applied to the picture processing jobs and the picture processing speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to an image processing device suitable for obtaining a wire frame image of a three-dimensional binary image from any direction.

(Prior Art) In recent years, attempts have been made to construct three-dimensional images (three-dimensional images) from tomographic images obtained from CT and the like. As one method for displaying this type of 3D binary image on a display screen with a three-dimensional effect, a so-called YA7-frame is created in which the outlines of each section of the 3D binary image are stacked. It is known to ask for images. However, the amount of calculation required to find and stack the contours of each cross section is enormous, so to obtain one wireframe image,
There was a problem that took a long time.

(Problems to be Solved by the Invention) As described above, conventionally, it has been difficult to quickly obtain a wire frame image from a three-dimensional binary image.

The present invention has been made in view of the above circumstances, and its purpose is to provide an image processing device that can easily and quickly perform processing to obtain a wire frame image from any direction of a three-dimensional binary image using two-dimensional grayscale image processing. Our goal is to provide the following.

[Structure of the Invention] (Means for Solving the Problems) This invention transforms a binary image of one cross section of a three-dimensional binary image into a designated projection plane by affine-transforming the binary image including the density value O.
An affine transformation processing means is provided that performs processing for obtaining a two-dimensional first image expressed by the density value of the species in order from the section farthest from the projection plane for each cross section, and the first image is obtained by this affine transformation processing means. Each time, a third image is obtained based on this first image and a second image having the minimum density value in the initial state, and a fourth image showing the outline of the same image is obtained based on the first image. It was designed to be obtained.

The density value of each pixel in the third image matches the density value of the corresponding pixel in the second image if the density value of the corresponding pixel in the first image is O, and indicates the minimum value if it is not O. The present invention further provides that each time the third and fourth images are obtained, a bit-by-bit OR of the density values of each corresponding pixel of both images is taken, and the OR result is held as the density value of the corresponding pixel. A fifth image is obtained to be used as a new second image.

(Operation) According to the above configuration, by repeatedly obtaining the fifth image to be used as the second image by sequentially switching the cross sections of the three-dimensional binary image,
The contour lines of each cross section of the dimensional binary image are stacked, and the I! A wireframe image with il (hidden lines) removed can be obtained. Moreover, since the processing up to obtaining this wire frame image can be performed on a two-dimensional image, a two-dimensional image processor can be applied, and therefore the processing speed can be increased.

(Embodiment) FIG. 2 shows a block configuration of an image processing apparatus according to an embodiment of the present invention. In the figure, 11 is a CPLl that controls the entire device, and 12 is a main memory.

13 is a CRT monitor with a keyboard for displaying images, etc., and 14 is a display controller for the CRT monitor 13. 15-1.15-2.・15-n, 16-1.
16-2°...16-5 is, for example, an 8-bit lil!
A two-dimensional frame memory having iyA, and 17 a table memory used to store a data conversion table for 12-bit to 8-bit data conversion.

21 is a frame memory (here, frame memory 15-
An affine transformation processor (hereinafter referred to as AFN processor) 22 is a two-dimensional image processor that performs affine transformation on the image above (1 to 15-n) and outputs it to another frame memory (frame memory 16-1 here). This is a data conversion processor (hereinafter referred to as DCv processor) which is a two-dimensional image processor that converts a 12-bit image (12-bit image data) into an 8-bit image (8-bit image data) using the table memory 16. 23 is a frame memory (frame memory 16-1 in this case) whose density value is a region other than 0.
5 is a two-dimensional image processor that outputs a contour line processor (hereinafter referred to as BDR processor); 24 is a two-dimensional image processor that outputs two frames (here frame memory 16-3,
4) A logical sum processor (hereinafter referred to as an OPR processor) is a two-dimensional image processor that calculates a bitwise logical sum for each corresponding pixel of the above image and outputs it to another frame memory (frame memory 16-5 in this case). ). 25, the CPU 11 is connected to the display controller 14, frame memories 15-1 to 15-n, and 1B-1 to 16-5.
, a control bus used to control the table memory 17 and the processors 21 to 24; 26 is the display controller 14; frame memories 15-1 to 15-n, 16-1;
~16-5, table memory 11 and processor 21
This is an image bus used for image data transfer between .

Next, the operation of the configuration shown in FIG. 2 will be described with reference to the flowchart shown in FIG. 1 for the case where a wire frame image of a three-dimensional binary image is obtained from an arbitrary direction.

Here, for each cross-section of a three-dimensional binary image, the following ■ to ■
The following processing is performed.

Now, the frame memories 15-1 to 15-n contain binary images W1 to wn of each cross section (n cross section in this case) of the three-dimensional binary image (8-bit image data with a value of O or 1 for each pixel). It is assumed that a binary image of the cross section so far, for example, a wire frame image 9ww for w1 to wi-1, is obtained in the frame memory 16-2.

■ First, CP tJ 11 is determined by any three points that are not aligned on the same straight line on the binary image wi of the cross section next to the projection plane after the previous cross section, for example, the four vertices of wi as shown in Figure 3. Select three points P1, P2, and P3, and select points P1, P
2, the intersection point Q1 of the projection plane and a straight line passing through P3 and perpendicular to the projection plane. Q2. Q3 (here, affine transformation points 01 to Q3 of points P1 to P3 onto the projection plane) is determined. Then, the CPU 11 selects the input image (3 on g1wi).
Known affine transformation coefficients are determined from the relationships between points P1 to P3 and three points 01 to Q3 on the projection image (affine transformation image) wp of Wl, which becomes the output image, and affine transformation of image W1 is performed using these coefficients. Processing is instructed to the AFN processor 21 via the control bus 25.

As a result, the AFN processor 21 controls the frame memory 1
Binary image W1 stored in 5-i (1≦i≦n)
is subjected to affine transformation using affine transformation coefficients given from the CPU 11, and an affine transformed image Wp is obtained in the frame memory 16-1. The image data (density value) of each pixel of this wp is 8-bit data with a value of O or 1.

■ The AFN processor 21 uses the frame memory 16-1
When the affine-transformed image Wp is found in the image, the CPU 11 is notified of this via the control bus 25.

Upon receiving the notification from the AFN processor 21, the CPU 11 sets a data conversion table in the table memory 17, and then starts the DCv processor 22.

In the data conversion table set in the table memory 17, as shown in FIG.
0”) or 1 (“0001”) 12-bit density @(
It has an entry specified by the input density), and among the entries, the entry whose upper 4 bits are indicated by O has an 8-bit output image with the same value as the lower 8 bits (0 to 255). 8-bit output image data (output density) with a value of 0 is set in each entry whose data (output density) is indicated by a value of 1 in the upper 4 bits. Note that the above data conversion table may be set in the table memory 11 in advance.

Now, when the DCv processor 22 is activated by the CPU 111C, the image w in the frame memory 16-1 is
The lower 4 bits (lil is O or 1) of the 8-bit image data (density value) of each pixel of p are set as the upper entry address, and the 8-bit image data (111 The data conversion table in the table memory 17 is referred to using the 12-pit entry address whose lower entry address is
The lower 4 bits of the 8-hit 11 degree value from p and the image W
The 12-bit density value in which the 8-bit density values from W are concatenated is converted into the setting value (8-bit density value) of the corresponding entry in the data conversion table in the table memory 17. Then, the DC ■ processor 22 writes this converter lf value into the corresponding pixel position of the frame memory 16-3. As is clear from the data conversion table contents shown in Fig. 4, when the concentration value on the wp side is O, this conversion a stands
It is the same as the direct value, and becomes O when the concentration value on the wp side is 1. Therefore, the AFN processor 21 repeats the above processing for all pixels of the images @wp and ww, so that the wire frame image (l1ww) for the previous cross section is stored in the frame memory 16-3. Picture 1wd with the internal part of the frame erased (hidden line erasure) is found in the frame memory 16-3.The 8-bit density value of each pixel in picture [+WW is all 0 in the initial state. be.

■ The DCV processor 22 uses the frame memory 16-3
When the image lewd is determined within the range, the CPU 11 is notified of this via the control bus 25. When the CPU 11 receives the notification from the DC processor 22, it starts the SDR processor 23. As a result, the BDR processor 23
8 showing the outline of the image wp in the frame memory 16-1
The density value of each pixel corresponding to the boundary of the area where the value is other than O (in this case, the area where the value is 1) in the bit image wb, that is, the image wp, is 255, and the density value of all other pixels is 8, which is O.
Bit image 1wb is found in frame memory 16-4. This image wb is a wire frame image of only the current cross section.

■ The BDR processor 23 uses the frame memory 16-4
When the image wb is obtained within the image, the CPU 11 is notified of this. Upon receiving the notification from the BDR processor 23, the CPU 11 activates the OPR processor 24. This causes the OPR processor 24 to control the frame memory 16-
For the 8-bit density values of each pixel of the image wd in the frame memory 16-4 and the image wb in the frame memory 16-4, perform a logical OR between the same pixels and for each same bit, and create a new 8-bit density that is the result of the logical sum. Write the value to the corresponding pixel location in frame memory 16-5. and OPR processor 24
By repeating the above logical sum operation processing for all pixels of images wd and wb, the following information is stored in the frame memory 16-5.
New wireframe drawing including this cross section 1) lol
' is required.

(2) When the wire frame image ww' is found in the frame memory 16-5, image data is transferred from the frame memory 16-5 to the frame memory 16-2. As a result, frame memory 16-5 is
The image ww′ obtained in 2008 becomes the wire frame image WW up to the latest cross section, instead of the previous image WW.

The above processing of ■ to ■ is performed on the frame memories 15-1 to 15
By repeating the binary images of all sections of the 3-dimensional binary image stored in -n in order from the section farthest from the given projection plane, Wireframe image with hidden lines removed WW
can be found.

In the above embodiment, the frame memory 16-2 is used for storing the image WW, and the frame memory 16-5 is used for storing the image WW', but it is also possible to use them by switching alternately. . In this case, there is no need to transfer the image from the frame memory 1B-5 to the frame memory 16-2. Furthermore, in the embodiment described above, the binary images of each section of the three-dimensional binary image are stored in different frame memories, but the present invention is not limited to this.

For example, if the depth of the frame memory is 8 bits, in order to effectively use the memory capacity, two
Value images may be stored in one frame memory.

[Effects of the Invention] As detailed above, according to the present invention, a wire frame can be created from any direction by stacking the contour lines of each cross section of a three-dimensional binary image and eliminating lines (hidden lines) that overlap with other cross sections. Since the image obtaining process can be performed on a two-dimensional grayscale image, a two-dimensional image processor can be applied to this image processing, and the processing speed can be increased.

[Brief explanation of the drawing]

FIG. 1 is a flowchart showing an example of wire frame image acquisition processing directly related to the present invention, FIG. 2 is a block diagram of an image processing device that implements the processing in FIG. 1, and FIG. FIG. 4 is a diagram illustrating affine transformation for a given projection plane on a cross section of a value image, and is a diagram showing a data conversion table set in the table memory of FIG. 2. 11-CP LJ, 15-1 to 15-n, 16-
1 to 16-5 - Frame memory, 17 Table memory, 21 Affine transformation (AFN) processor, 22 Data conversion (DCv) processor, 23
- Contour line (BDR) 70 setters, 24... Logical OR (OPR) processor. Applicant's agent Patent attorney Takehiko Suzue Figure 1 Figure 2 Figure 3 Figure 4;

Claims (1)

[Claims] A two-dimensional first image expressed by two types of density values including a density value of 0, obtained by affine transforming a binary image of one cross section of a three-dimensional binary image onto a designated projection plane. an affine transformation processing means that executes processing for obtaining the first image on each cross section of the three-dimensional binary image in order from the cross section farthest from the projection plane; If the density value of the pixel on the first image side is 0, the density value of the pixel on the second image side is the concatenated data of the density value of each corresponding pixel of the second image that has the minimum density value in one image and the initial state. image data conversion processing means for converting the density value of the pixel on the first image side into the minimum density value if it is not 0, and obtaining a third image having this converted density value as the density value of the corresponding pixel. and a contour processing means for calculating a fourth image showing the contour of the first image every time the first image is calculated by the affine transformation processing means; and a contour processing means for calculating the fourth image by the contour processing means. is,
Every time the third image is obtained by the image data conversion processing means, the bitwise logical sum of the density values of the corresponding pixels of the fourth and third images is calculated, and the logical sum result is used as the density value of the corresponding pixel. a logical sum processing means for obtaining a fifth image to be used as the new second image; An image processing device characterized in that an image is obtained as a wire frame image.