JPH01118193A - Access apparatus for image memory - Google Patents

Abstract

PURPOSE: To fix the processing time for painting-out of the inside of a picture memory regardless of increase of the number of layers of the picture memory by providing each picture memory with one arithmetic unit which extends picture data of one picture element into plural picture elements and selects which part should be written in the picture memory. CONSTITUTION: Picture memories 101 to 10N are provided with arithmetic units 111 to 11N. A bidirectional register 201 provided in each of arithmetic units 111 to 11N extends picture data of one picture element to only picture elements selected from plural picture elements, which can be operated by the data bus width, and designates color information of one designated picture element to the data bus width and designates which part of plural extended picture elements should be written in a picture memory 1. Thus, write of picture data for painting-out in a single color or the like is quickly performed, and increase of the time required for change of the picture memory is prevented regardless of increase of the number of layers of the picture memory.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for reading and writing a multi-layered image memory at high speed. Multi-layer + suitable for high-speed processing
The present invention relates to an access device for an image memory having an rI structure.

[Prior art]

A conventional color image display control device will be explained with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing a method in which a control device 401 such as a microprocessor accesses image memo 1J407, 408, 4.09, which is composed of NWI and has color information of 1 pixel and N bits, in image memory units of each layer. It is.

The control device 401 specifies one word of the image memory using the image memory address signal 402. address signal 4
02 is input to the memory control switch 405 from the data switch 406, and the memory control signal 403 from the control device 401 and the data line 4
04 is connected to one of the N-layer amphoteric memories 407, 408°4o9. One word data specified in this way is controlled by the memory control signal 40 of the control device 401.
3, reading and writing are performed. The data in the image memories 407, 408, and 409 are always read out by a display controller 410 and displayed on a display device 411 such as a CRT.

FIG. 2 shows a block diagram of an image memory control circuit that accesses the image memory one image at a time.

N-bit data line 404 coming out of controller 401
are connected to each layer 412, 413, 4111 of the image memory by -bit. The address signal 402 specifies one bit in each layer 412, 413, and 414 of the image memory, and the N-bit signal, that is, the data of one pixel, is written or read using the memory control signal 403.

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, in the former memory access method, in order to write one pixel, the number of layers of the image memory, that is, memory access must be performed N times, and the number of memory accesses of the image memory increases. The disadvantage is that as the number of layers increases, the processing time also increases.

However, in this method, if the number of bits constituting one word is W, then W pixels arranged horizontally can still be accessed by N times of memory access.

On the other hand, the latter memory access method is effective when drawing straight lines, but is not suitable for raster-based processing such as filling. This is because the image memories 4-12, 413, and 414 are normally connected to the display controller 1-
When read out by the roller 410, a plurality of pixels are read out and displayed on the display device 411. Therefore, for one plane of image memory, there is actually one data line.
There are multiple bits instead of bits, and only one of them is used when accessing the image memory, so
When performing memory access in the raster direction, the same memory address is accessed multiple times, resulting in poor efficiency.

An object of the present invention is to enable each layer of the image memory to read, change, and write image data in parallel when writing image data such as filling with a single color.
To provide an image memory access device in which the time for changing an image memory does not increase even if the number of layers of the image memory increases.

[Means to solve the problem]

The above purpose is to provide an arithmetic unit in each layer of the image memory, and in each of the arithmetic units, a means for expanding image data for one pixel into multiple pixels, and a means for selecting which part of the multiple pixels is to be written to the image memory. This is achieved by providing means for

[Effect]

The means for expanding the image data of one pixel provided in each processing unit to multiple pixels is to transfer the color information of a specified pixel to only the selected pixel from among the multiple pixels that can be calculated for the width of the data bus. By specifying which part of the expanded plurality of pixels is to be written into the image memory, the selection means can quickly write image data such as filling with a single color, Even if the number of calendars in the image memory increases, the time required to change the image memory can be prevented from increasing.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 3, 4, and 5.

Figure 3 shows that the data width for reading and writing is 8 pixels and 10 pixels.
The structure of the single-layer image memory, for example 101 in FIG. shows. Control signal bus 4
1 includes a read/write signal, and the read/write signal is connected to a read/write terminal of a memory element constituting the image memory 1 .

FIG. 4 shows an example of the configuration of a color image display device for realizing the image memory access device of the present invention.

An image memory 102 having the same configuration as the image memory 101 shown in FIG. ....

1ON and 111, 112. . . , 11N, each has an 8-bit width local data bus 121 .
122. ..., connected by 12N.

Control device 5 and arithmetic devices 111, 112. ....

The ILNs are connected by an 8-bit data bus 2 and a control signal bus 41. The data bus 2 sequentially transmits the data input/output signal 21, which is the first bit, to the first arithmetic unit 111, and the second bit to the second arithmetic unit 111.
The 8th bit is connected to the 8th arithmetic unit. If N is 9 or more, the Nth bit data is (N mod 8)
Connected to the bit-th arithmetic unit.

FIG. 5 is a diagram showing the configuration of the first arithmetic device 111 in FIG. 4, and the second to Nth arithmetic devices 112.
..., 11N also have the same configuration. Arithmetic device 1
11, a first register 202 that latches 8-bit data on the local data bus 121; a second register 203 that latches the contents of the first register 202;
A barrel shifter 204 shifts these 16-bit data by 15 bits from O and outputs the lower 8 bits, and the output of this barrel shifter 204 is connected to the local data bus 12.
an arithmetic unit 205 that performs a logical operation with a third register 208 that latches the data on the first register;
a mask selector 206 that selects the contents of the third register 208 bit by bit; a fourth register 207 that latches the output of the mask selector 206 and is connected to the local data bus 121;
and a fifth bidirectional register 201 that interfaces with the data bus 2. Fifth bidirectional register 2
01 has the function of latching the 1-bit data input/output signal 21 and the 1-bit data “0” and “1” to generate 8-bit “oooooooo”” 1111
1111'' and control sending it to the local data bus 121; a function to latch 1 bit of the 8-bit data on the local data bus 121; of,
It consists of two D-type flip-flops,
It can be easily configured with one 8-to-1 selector and nine 3-state buffers.

By the way, the control signal bus 41 includes a 1-bit read/write signal from the image memory 1 mentioned above, a 1-bit signal to take in 1-bit data of the data input/output signal 21 to the fifth bidirectional register 201, and a 1-bit signal to decompress the taken data. A 1-bit signal that controls sending to the local data bus 121, 3-bit data that determines which 1-bit data to select from among the 8-bit data on the local data bus 121, and the selected 1-bit data are sent to a fifth controller. The 1-bit signal taken into the direction register 201 and the 1-bit data taken into it are sent to the data output signal 2.
A control signal 21 of 7 bits in total for the fifth bidirectional register 201 consisting of 1 bit
3 and.

A latch signal 210 of the first register and a latch signal 211 of the second register.

A 4-bit control signal 212 that controls the number of shifts of the barrel shifter 204, and a function (TTL IC74L) of the arithmetic unit 205.
A 4-bit control signal 214 that determines the logical operation mode (according to the logical operation mode of S181), and an 8-bit control signal 215 that controls the bit-by-bit selection of each input of the mask selector 206.
and.

A total of 2 bits of the fourth register, consisting of a latch signal 217 of the third register 208, a 1-bit latch signal of the fourth register 207, and a 1-bit signal for controlling sending of the fetched data to the local data bus 121, is provided. and a control signal 216 for the register 207. Among these control signal buses 41, a signal for controlling sending of the data of the fifth bidirectional register 201 in the control signal 213 to the local data bus 121, and which one bit of the 8-bit data of the local data bus 121 is selected. Decide whether to select 3
The bit data and its signal are transferred to the fifth bidirectional register 20.
1, and latch signals 210 and 211
, 217 and control signals 212, 214, 215, 21
6 is each arithmetic device 111, 112 . . . , are all commonly connected to 11N. Also, a signal that takes in the data input/output signal 21 in the control signal 213 of the control signal bus 41 into the fifth bidirectional register 201, and a signal that inputs the contents of the fifth bidirectional register 201 into the data input/output signal 213 When the number of image memories N is 8 or less, the signal to control transmission to each arithmetic unit 111, 112 .・
..., commonly connected to 11N. If N exceeds 8, then every 8 these two signals are divided into the largest integer not exceeding (N-1)/8+1. That is, the control device 5 is the arithmetic device 111, 112 . ...When accessing the fifth bidirectional register of IIN, data bus 2
Since these are 8 bits, these control signals are divided so as to access eight fifth bidirectional register units. In the following description, for convenience, N is assumed to be 8 or less.

Now, in FIG. 4, screen memories 101, 102. ....

1ON, video signals 151, 152 . ....

15N is read out, converted into a color video signal 14 by the color conversion circuit 13, and displayed on the color CRT 6 in the following manner.

First, serial data 151,'1 from the image memory
52, . . . , 15N are the CRT control device 7 (for details, see
The display address 71 from the HD46505 (see the HD46505 section in the Hitachi Microcomputer System Device Data Book) is sent to the image memory address signal 9 via the selector 9.
1 to one image memory, and the image data read out from each image memory is converted into serial data by a parallel-to-serial converter 8.

The obtained N-bit data is the color code of one pixel,
The RGB video signal 1 is input to the color conversion circuit 13.
Converted to 4. This video signal 14 and a periodic signal 72 output from the CRT control device 7 are sent to the color CRT 6, and a color image is displayed on the CRT.

A method in which the control device S accesses the image memory 1 in the screen memories 101, 102°, . . . , 1ON via the arithmetic units 111, 112°, .

First, in order to bring information for one pixel consisting of N bits from an image memory to the data bus 2, the control device 5 sends the address of the image memory containing the pixel to be read to the address bus 3. Then, the address selection signal 42 is set on the address bus 3 side. Next, the 3-bit signal that selects 1 bit from the 8-bit data of the control signal 213 is set to the number of the 8 pixels read out for the image to be read, and the local Provides a latch signal that takes in data from the data bus 121. At the same time, the data input/output signal 21 of the control signal 213
The fifth bidirectional register 201
The target pixel information taken in is sent to the data bus 2.

Next, in order to write N bits of pixel information to a certain point on the image memory, the control device 5 first sends out the pixel information to be written onto the data bus 2, and uses the control signal 213 to It is taken into the direction register 201. The 1-bit data taken in is expanded into 8-bit data, sent to the local data bus 121 by the same control signal 213, and taken into the first register 202 by the control signal 210. Then, the 4-bit control signal 212 of the barrel shifter is set to a shift number of 0 so that one input of the arithmetic unit 205 has the same data as the first register 202.

On the other hand, the control circuit 5 gives the address of the image memory 1 containing the target writing point to the address bus 3, sets the address selection signal 42 to the address bus 3 side, and sends the data of the image memory to the local data bus 121. At the point when the data is sent to the third register 208, the latch signal 21
7. At this time, the fifth bidirectional register 20
1 output to the local data bus.

In order to avoid conflict with the output of the image memory, the control device 5 uses the address selection signals 42 . Control signal 213 is controlled.

In addition, the control device 5 gives a control signal 214 indicating what kind of logic is used to calculate the pixel information to be written and the pixel information of the point to be written currently in the image memory, so that the point to be written is The position of the 8 pixels corresponding to the address of the image memory containing the image is given to the control signal 215 of the mask selector 206 as 8-bit information. For example, if the second pixel from the left is the pixel to be written, the control signal 215 will be a binary number "01000000". Now, after the output of the mask selector 206 is determined, the output of the mask selector 206 is taken into the fourth register 207 according to the control signal 216, and the taken data is sent to the local data bus 121. By setting the read/write signal of the control signal bus 41 to write, the control device 5 writes the result of a logical operation between the given pixel information and the pixel information that existed before being written to the point to be written. By appropriately changing the control signal 215 in this process, it is possible to write the same image information to up to eight pixels.

Next, a method will be described in which eight arbitrary pixels arranged horizontally on the image memory are transferred by performing a logical operation on each eight pixels specified for one address in the image memory. First, the eight pixels to be transferred are specified by two addresses across two words. The address with one word on the left side of the screen is called the source address. on the other hand,
The addresses of the 8 pixels to which the data is transferred are called destination addresses.

The control device 5 first sends a source address to the address bus 3 and sends an address selection signal 42 to the address bus 3.
Set on the side. When the image memory data corresponding to the source address is sent to the local data bus 211,
Image data is loaded into the first register 210 by the latch signal 210. At the same time, the control device 5 sends to the address bus 3 an address obtained by adding 1 to the source address (on the right side on the screen).

When data in the image memory at an address obtained by adding 1 to the source address is sent to the local data bus 121, the contents of the first register 202 are latched into the second register 203 by the latch signal 211 and the latch signal 210. At the same time, data on the local data bus 121 is taken into the first register 202. Next, the control device 5
The control signal 212 is given as a 4-bit signal a value representing in binary notation the position of the leftmost pixel of the 8 pixels to be transferred from the left of the 8 pixels of the source address. Furthermore, the control signal 214 is set to determine what kind of logical operation is to be performed. Next, the control device 5 gives a destination address to the address bus 3, and when the data of the image memory is sent to the local data bus 121, it is taken into the third register 208 by the control signal 217. All the control signals 215 are set to "1", all outputs of the arithmetic unit 205 are set to be the outputs of the mask selector 206, and the outputs of the barrel shifter 204 and the third register 208 are
After the logical operation result is determined as the input to the fourth register 207, the control signal 216 causes the fourth register 20
7, the output of the mask selector 206 is taken in and simultaneously sent to the local data bus 121. By setting the read/write signal of the control signal bus 41 to write, image data of any consecutive 8 pixels out of the 16 consecutive pixels at the source address and the source address plus 1 on the image memory is generated. The result of performing a logical operation on the 8-pixel image data that was at the destination address before being transferred is written to the destination address. With this process, the mask selector 20
By giving mask information to the control signal 215 of 6,
It is possible to transfer masked images.

In this way, according to this embodiment, each image memory is provided with an arithmetic unit, and by accessing the single image memory 1 in parallel, the number of image memories is several times that of the conventional method shown in FIG. High-speed processing can be performed, which is eight times faster than the method shown in FIG. In addition, the arithmetic unit includes first and second registers that hold pixel information of the transfer source, a barrel shifter that shifts them by an arbitrary number of bits, a third register that holds pixel information of the transfer destination, and the output of the barrel shifter. and a third register, a mask selector that can select bit by bit between the output of the arithmetic unit and the third register, and a fourth register that holds pixel information to be transferred. This significantly speeds up the transfer of images in the image memory.

〔Effect of the invention〕

According to the present invention, for each image memory of a multilayered image memory, there is a means for expanding image data for one pixel into a plurality of pixels, and selecting which part of the expanded plurality of pixels is to be written to the image memory. By having one arithmetic unit with the means, it is possible to read, change, and write image data consisting of multiple pixels in the horizontal direction in each column, so even if the number of layers of image memory increases, The processing time for filling in the image memory becomes constant.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a display control device that accesses the image memory layer by layer in word units, FIG. 2 is a block diagram of a display control device that accesses the image memory pixel by pixel, and FIG. 3 is a block diagram of a display control device that accesses the image memory in units of pixels. FIG. 4 is a block diagram of one image memory of a color image display control device according to an embodiment of the present invention. FIG. 5 is a block diagram of a calculation device. be. DESCRIPTION OF SYMBOLS 1... Image memory, 2... Data bus, 3... Address bus, 41... Control signal bus, 42... Address selection signal, -5... Control device, 6... Color C
RT, 7...CRT control circuit, 71...Display address, 72...Synchronization signal, 8...Parallel-serial converter, 9
...Selector, 101.102.・、ION...
1st to Nth screen memories, 111, 112.・・・
・, IIN... 1st to Nth arithmetic units, 13.
...Color conversion circuit, 204...Barrel shifter, 20
5... Arithmetic unit, 206-(=L/ Lid, 207,
208, 210° 211...Register, 401...
Memory control device, 402...Address signal, 403.
...Memory control signal, 404...Data line, 407,408°409.412,413,414
. . . Image memory, 410 . . . Disable controller, 411 . . . CRT. Agent Patent Attorney Katsuma Ogawa ' 1, 1S1 Figure 4 Figure 5

Claims (1)

[Claims] 1. An image memory having a multilayer structure for storing color image data, and reading out the image memory sequentially in a raster direction;
A color device comprising means for transmitting data to a display device, and a control device that generates an address of the image memory and controls reading and writing of the image memory, the color device comprising: a control device that generates an address of the image memory and controls reading and writing of the image memory; An arithmetic device comprising means for holding the image data composed of a plurality of pixels, means for shifting the image data, and means for performing logical operations on the image data is provided between the control device in each layer of the image memory. and means for expanding pixel data of one pixel into a plurality of pixels, and means for selecting which portion of the expanded plurality of pixels is to be written into the image memory, in the arithmetic unit. An image memory access device characterized in that: