JPH01117401A - Coplanar circuit - Google Patents

Coplanar circuit

Info

Publication number
JPH01117401A
JPH01117401A JP19571588A JP19571588A JPH01117401A JP H01117401 A JPH01117401 A JP H01117401A JP 19571588 A JP19571588 A JP 19571588A JP 19571588 A JP19571588 A JP 19571588A JP H01117401 A JPH01117401 A JP H01117401A
Authority
JP
Japan
Prior art keywords
line
coplanar
conductor
circuit
coupling slot
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19571588A
Other languages
Japanese (ja)
Other versions
JPH0373167B2 (en
Inventor
Hirotsugu Ogawa
博世 小川
Kazunori Yamamoto
和紀 山本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP19571588A priority Critical patent/JPH01117401A/en
Publication of JPH01117401A publication Critical patent/JPH01117401A/en
Publication of JPH0373167B2 publication Critical patent/JPH0373167B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Waveguides (AREA)

Abstract

PURPOSE:To constitute the title circuit on a semiconductor substrate only by constituting a connection part between a coupling slot line and a coplanar line in a multi-layer structure. CONSTITUTION:A coplanar line 24 is formed in crossing with a connection point between coupling slot lines 41, 42 and connected to a conductor layer 27 constituting the coupling slot lines 41, 42 through a center conductor 25 and strip conductor 26. Moreover, conductors 28, 29 are connected by a conning piece 35 at the coupled part of the coupling slot lines 41, 42 and the coplanar line 24 by a connecting piece 35, furthermore center conductors 43, 44 of the coupling slot lines 41, 42 are connected by a connecting piece 45 and insulation layers 36, 46 are interposed between the connecting pieces 35, 45 and the bottom of slots at both sides of the strip line 26 and between them and the line 26. Thus, the circuit coupling the coplanar lien 24 and the coupling slot lines 41, 42 on a semiconductor substrate 21 is manufactured by the etching process only.

Description

【発明の詳細な説明】 この発明はマイクロ波回路として用いられ、共平面線路
で構成された共平面回路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a coplanar circuit that is used as a microwave circuit and is composed of coplanar lines.

〔従来技術〕[Prior art]

従来の共平面線路を用いて構成した回路は第1図に示す
ように誘電体基板11の一面にマイクロストリップ線路
12が形成され、誘電体基板11の他面に互に連結され
た結合スロット線路13゜14が形成され、誘電体基板
ll内に設けたスルーホール内の導体15によってマイ
クロストリップ線路12と結合スロット線路13.14
とが結合されていた0例えばボート16からの入力波は
マイクロストリップ線路12を伝搬し、スルーホール内
導体15によって結合スロット線路13゜14の伝搬(
偶モードで伝搬)に変換され、それぞれボート17.1
8から出力が得られる。
As shown in FIG. 1, a circuit constructed using a conventional coplanar line has a microstrip line 12 formed on one side of a dielectric substrate 11, and coupled slot lines connected to each other on the other side of the dielectric substrate 11. 13° 14 are formed, and the microstrip line 12 and the coupled slot line 13.14 are connected by the conductor 15 in the through hole provided in the dielectric substrate ll.
For example, the input wave from the boat 16 propagates through the microstrip line 12, and is propagated through the coupled slot line 13, 14 by the through-hole conductor 15 (
propagating in even mode), each boat 17.1
Output is obtained from 8.

誘電体基板11のスルーホールは通常はドリルまたはレ
ーザ等により形成される。このため、高い工作精度が要
求され、製造コストが高くなる問題がある。また、使用
周波数が高くなった場合スルーホール内導体15の寄生
素子により伝送特性が劣化するため適用周波数には限界
があった。またこの構成を半導体基板上で形成するモノ
リシッり集積回路に適用した場合、半導体基板の裏面に
対してもパターンを形成しなければならないため、エツ
チング工程数の増加、裏面を用いることによる基板寸法
の増加等によりモノリシック化によるマイクロ波回路の
経済化、小形化を実現することは難しい。
The through holes in the dielectric substrate 11 are usually formed using a drill, laser, or the like. For this reason, there is a problem that high machining accuracy is required and manufacturing cost increases. Furthermore, when the operating frequency becomes high, the transmission characteristics deteriorate due to the parasitic elements of the through-hole conductor 15, so there is a limit to the applicable frequency. Furthermore, when this configuration is applied to a monolithic integrated circuit formed on a semiconductor substrate, the pattern must also be formed on the back side of the semiconductor substrate, which increases the number of etching steps and reduces the substrate size by using the back side. Due to this increase, it is difficult to realize economicalization and miniaturization of microwave circuits by making them monolithic.

〔発明の目的〕[Purpose of the invention]

この発明はこれらの欠点を除去するため半導体基板上の
みで回路を構成できる共平面回路を提供することを目的
とするものである。
The object of the present invention is to provide a coplanar circuit that can be constructed only on a semiconductor substrate in order to eliminate these drawbacks.

〔実施例〕〔Example〕

第2図はこの発明の実施例を示し、半導体基板21の一
面上に導体層が形成され、その導体層に対し、結合スロ
ット線路41.42がほぼ延長するように形成され、そ
の結合スロット線路41゜42の接続点と交点してコプ
レナー線路24が形成され、コプレナー線路24の中心
導体25ストリップ導体26を通じて結合スロット線路
41.−42の接続部を通り、結合スロット線路41.
42を構成するコプレナー線路24と反対側の導体層2
7に接続される。ストリップ導体26の幅は中心導体2
5の幅より狭くされ集中定数的な接続とされてこれら線
路41.42と24とのインピーダンス整合がなされる
。かつコプレナー線路24の中心導体25及び両外導体
28.29間のスロット31.32がストリップ線路2
6の両側縁に沿って延長して結合スロット線路41.4
2に連結するように溝33.34が形成される。この結
合スロット線路41.42とコプレナー線路24との結
合部において導体28.29が連結片35で連結され、
さらに、結合スロット線路41.42の中心導体43.
44が連結片45で連結され、連結片35.45とスト
リップ線路26及びその両側の溝33.34の底との間
に例えばSin。
FIG. 2 shows an embodiment of the present invention, in which a conductor layer is formed on one surface of a semiconductor substrate 21, and coupling slot lines 41 and 42 are formed to substantially extend with respect to the conductor layer. A coplanar line 24 is formed by intersecting the connection points of 41° and 42, and a coupling slot line 41. -42 connection, and the coupled slot line 41.
42 and the conductor layer 2 on the opposite side to the coplanar line 24
Connected to 7. The width of the strip conductor 26 is the width of the center conductor 2
The width of the lines 41, 42 and 24 is made narrower than the width of 5, and the connection is made like a lumped constant to achieve impedance matching between the lines 41, 42 and 24. In addition, the slots 31 and 32 between the center conductor 25 and both outer conductors 28 and 29 of the coplanar line 24 are connected to the strip line 2.
A coupled slot line 41.4 is extended along both side edges of 6.
Grooves 33, 34 are formed so as to connect to 2. The conductors 28, 29 are connected by a connecting piece 35 at the joint between the combined slot line 41, 42 and the coplanar line 24,
Furthermore, the center conductor 43. of the coupled slot line 41.42.
44 are connected by a connecting piece 45, and for example, a Sin.

のような絶縁層36.46が介在される。連結片35.
45とストリップ線路26との対向面積はなるべく小さ
くしてこれら間の静電容量が小さくなるようにされる。
An insulating layer 36, 46 such as is interposed. Connecting piece 35.
The opposing area between the strip line 45 and the strip line 26 is made as small as possible to reduce the capacitance between them.

結合スロット線路41.42とコプレナー線路24との
各結合部と反対の端はそれぞれ入出力ボート37,38
.39とされる。
The ends opposite to the joints between the coupled slot lines 41 and 42 and the coplanar line 24 are connected to input/output boats 37 and 38, respectively.
.. It is said to be 39.

第3図は第2図の動作原理を線路の伝搬モードを用いて
説明するための図である。コプレナー線路24の伝搬モ
ードの電界の方向47は中心導体25から外側接地導体
28.29の方向に向いており、両側の接地導体の電位
は零ポテンシャルとなっている。そのため、第3図に示
す様に両側の導体を接地片35を用いて接続しても伝搬
モードへの影響は無い、すなわち、コプレナー線路から
結合スロット線路への変換部はこの特性を利用している
。結合スロット線路41.42の中心導体43.44は
コプレナー線路25の外側接地導体28.29と分離さ
れているため、結合片45によるコプレナー線路25の
伝搬モードへの影響は無い、結合スロット線路41.4
2の電界は4Bで示した方向となっている。これはコプ
レナー線路25の伝搬モードが並列分岐された後、結合
スロット線路の偶モードに変換されることを示している
。結合スロット線路の偶モードは同一の電界方向成分よ
り成っており、本回路は偶モード励振回路と言うことも
できる。結合スロット線路41゜42の特性インピーダ
ンスを適当に選択することによって、出カポ−)37.
38からは同振幅、同位相の出力が得られる。
FIG. 3 is a diagram for explaining the operating principle of FIG. 2 using the propagation mode of the line. The direction 47 of the electric field in the propagation mode of the coplanar line 24 is directed from the center conductor 25 to the outer ground conductors 28, 29, and the potentials of the ground conductors on both sides are zero potential. Therefore, as shown in Fig. 3, even if the conductors on both sides are connected using the grounding piece 35, there is no effect on the propagation mode.In other words, the conversion part from the coplanar line to the coupled slot line uses this characteristic. There is. Since the center conductor 43.44 of the coupled slot line 41.42 is separated from the outer ground conductor 28.29 of the coplanar line 25, the coupling piece 45 does not affect the propagation mode of the coplanar line 25. .4
The electric field of 2 is in the direction shown by 4B. This indicates that the propagation mode of the coplanar line 25 is branched in parallel and then converted into an even mode of the coupled slot line. The even mode of the coupled slot line consists of components in the same electric field direction, and this circuit can also be called an even mode excitation circuit. By appropriately selecting the characteristic impedance of the coupled slot lines 41 and 42, the output capacitor) 37.
38 provides outputs of the same amplitude and phase.

第4図に第2図の等価回路を示す。結合スロット線路4
1.42とコプレナー線路24とが互に接続される。コ
プレナー線路24が結合スロット線路41.42で並列
分岐された構成になっている。ストリップ線路26、連
結片35.45の交差部は半導体技術で用いられるエツ
チングで製作され、高い精度でパターンを作ることがで
きる。
FIG. 4 shows an equivalent circuit of FIG. 2. Combined slot line 4
1.42 and the coplanar line 24 are connected to each other. The coplanar line 24 is branched in parallel by coupled slot lines 41 and 42. The intersections between the strip line 26 and the connecting pieces 35, 45 are fabricated by etching, which is used in semiconductor technology, and a pattern can be created with high precision.

また、絶縁層36.46の厚みは線路間の結合が最小と
なるように、即ちストリップ線路26と連結片35.4
5との容量結合が小さく、かつ不連続部による寄生素子
を最小となるように製作することができる。したがって
、この構成による回路は高い周波数帯に適用可能であり
、また半導体基板21の片面のみを使用しているため、
片面のみのエツチングでパターンを製作でき、更に結合
スロット線路41.42とコプレナー線路24との接続
部を多層構造で構成しているため、回路の寸法を十分小
さくできる。そのため回路の経済化、小形化を達成でき
るモノリシック集積回路を高周波数帯で実現できる利点
がある。例えばハイブリット集積回路の場合は精度は数
十μm〜数百μm程度であるが、半導体製造技術(エツ
チング技術)では1μm以下の精度とすることができる
In addition, the thickness of the insulating layer 36.46 is set such that coupling between the lines is minimized, that is, the thickness of the strip line 26 and the connecting piece 35.4 is adjusted to minimize the coupling between the lines.
It can be manufactured so that capacitive coupling with 5 is small and parasitic elements due to discontinuities are minimized. Therefore, the circuit with this configuration is applicable to high frequency bands, and since only one side of the semiconductor substrate 21 is used,
Since the pattern can be manufactured by etching only one side, and since the connecting portion between the coupled slot lines 41, 42 and the coplanar line 24 is constructed with a multilayer structure, the dimensions of the circuit can be made sufficiently small. Therefore, there is an advantage that a monolithic integrated circuit can be realized in a high frequency band, which can achieve economicalization and miniaturization of the circuit. For example, in the case of a hybrid integrated circuit, the precision is on the order of tens of micrometers to several hundred micrometers, but with semiconductor manufacturing technology (etching technology), the precision can be less than 1 micrometer.

以上述べたように、この発明による共平面回路は半導体
基板上でコプレナー線路と結合スロット線路とを結合す
る回路を簡易な構成で、しかも高周波数特性が良く、エ
ツチング工程のみで製作できる利点がある。
As described above, the coplanar circuit according to the present invention has the advantage that the circuit for coupling the coplanar line and the coupled slot line on a semiconductor substrate has a simple structure, has good high frequency characteristics, and can be manufactured using only an etching process. .

〔効 果〕〔effect〕

以上説明したように、この発明による共平面回路は半導
体基板上に構成され、共平面線路、すなわち結合スロッ
ト線路及びコプレナー線路間の結合回路を機械工作なし
でエツチング工程のみで製作でき、更にパターン寸法も
エツチング精度で規定できるため、寄生素子、線路間結
合等を避けることが可能であり、したがってマイクロ波
、ミリ波回路の小形化、経済化を達成するモノリシック
集積回路として応用できる利点がある。
As explained above, the coplanar circuit according to the present invention is constructed on a semiconductor substrate, and the coplanar line, that is, the coupling circuit between the coupled slot line and the coplanar line can be manufactured only by an etching process without machining, and furthermore, the pattern size Since the etching accuracy can also be specified with etching accuracy, it is possible to avoid parasitic elements, coupling between lines, etc., and therefore there is an advantage that it can be applied as a monolithic integrated circuit that achieves miniaturization and economicalization of microwave and millimeter wave circuits.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の共平面回路を示す斜視図、第2図はこの
発明の実施例を示す斜視図、第3図は動作原理を説明す
るための図、第4図はその等価回路である。 21・−・半導体基板、24・・・コプレナー線路、2
5・・・コプレナー線路の中心導体、26・・・ストリ
ップ導体、35.45・・・絶縁層上ストリップ導体よ
りなる連結片、36.46・・・絶縁層、37.38 
。 39・・・入出力ボート、41.42・・・結合スロッ
ト線路、47.48・・・電界の方向。
Fig. 1 is a perspective view showing a conventional coplanar circuit, Fig. 2 is a perspective view showing an embodiment of the present invention, Fig. 3 is a diagram for explaining the principle of operation, and Fig. 4 is an equivalent circuit thereof. . 21... Semiconductor substrate, 24... Coplanar line, 2
5... Center conductor of coplanar line, 26... Strip conductor, 35.45... Connecting piece made of strip conductor on insulating layer, 36.46... Insulating layer, 37.38
. 39... Input/output boat, 41.42... Coupled slot line, 47.48... Direction of electric field.

Claims (1)

【特許請求の範囲】[Claims] (1)半導体基板上に第1,第2及び第3導体層により
結合スロット線路が形成され、上記半導体基板上にコプ
レナー線路が形成され、そのコプレナー線路の中心導体
は上記第1導体層に接続され、上記コプレナー線路の外
側2導体は上記第3導体層に接続され、上記中心導体と
上記第1導体層との連結部と上記第2,第3導体層との
間に絶縁層が介在されている共平面回路。
(1) A coupled slot line is formed on the semiconductor substrate by first, second and third conductor layers, a coplanar line is formed on the semiconductor substrate, and the center conductor of the coplanar line is connected to the first conductor layer. The two outer conductors of the coplanar line are connected to the third conductor layer, and an insulating layer is interposed between the connection portion between the center conductor and the first conductor layer and the second and third conductor layers. coplanar circuit.
JP19571588A 1988-08-05 1988-08-05 Coplanar circuit Granted JPH01117401A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19571588A JPH01117401A (en) 1988-08-05 1988-08-05 Coplanar circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19571588A JPH01117401A (en) 1988-08-05 1988-08-05 Coplanar circuit

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP59010498A Division JPS60153603A (en) 1984-01-23 1984-01-23 Coplanar circuit

Publications (2)

Publication Number Publication Date
JPH01117401A true JPH01117401A (en) 1989-05-10
JPH0373167B2 JPH0373167B2 (en) 1991-11-21

Family

ID=16345768

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19571588A Granted JPH01117401A (en) 1988-08-05 1988-08-05 Coplanar circuit

Country Status (1)

Country Link
JP (1) JPH01117401A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992020078A2 (en) * 1991-05-08 1992-11-12 Superconductor Technologies Inc. Superconducting delay line
US5194833A (en) * 1991-11-15 1993-03-16 Motorola, Inc. Airbridge compensated microwave conductors

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1992020078A2 (en) * 1991-05-08 1992-11-12 Superconductor Technologies Inc. Superconducting delay line
WO1992020078A3 (en) * 1991-05-08 1993-01-21 Superconductor Tech Superconducting delay line
US5194833A (en) * 1991-11-15 1993-03-16 Motorola, Inc. Airbridge compensated microwave conductors
US5387547A (en) * 1991-11-15 1995-02-07 Motorola, Inc. Process for adjusting the impedance of a microwave conductor using an air bridge

Also Published As

Publication number Publication date
JPH0373167B2 (en) 1991-11-21

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