JPH01116719A - Memory card circuit - Google Patents

Abstract

PURPOSE:To obtain a mass storage memory card circuit with a high static electricity resistant quantity and a high electromagnetic field resistant quantity by connecting the whole terminal signals of a semiconductor memory through a unilateral buffer with an analog switch and a bidirectional buffer to a terminal device without directly exposing it to the outside. CONSTITUTION:A unilateral non-inverter buffer 18 with the analog switch serially connected in respect of the terminal signal of the semiconductor memory and connected in parallel in respect of a ground is connected to the input terminal of the semiconductor memory, and a bidirectional 3 state buffer 19 is connected to an input/output terminal, a series transistor (TR) 20 is provided between a power source input and the internal power source of the memory card, a supply voltage detecting circuit 21 inputted by a card inserting/removing signal 24 and a supply voltage generated from the shortest contact 25 at a linking part between the terminal device and the memory card is provided, and by the output signal, the series TR 20, the unilateral non-inverter buffer 18 with the analog switch and the bidirectional 3 state buffer 19 are connected/disconnected. Thus, the highly reliable mass storage memory card with the high static electricity resistant quantity and the electromagnetic field resistant quantity can be realized.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to memory card circuits, and in particular, the present invention relates to memory card circuits, and in particular, the present invention relates to memory card circuits, and in particular, to the invention, it is possible to eliminate the possibility of disposing an external storage device in a semiconductor memory, and to utilize the high speed, low power consumption, and noiseless characteristics of a semiconductor memory. This invention relates to a circuit for a portable memory card that takes advantage of its features.

[Conventional technology]

FIG. 4 shows the circuit of a conventional memory card. In this figure, 1 is a static RAM group, which has a plurality of static RAMs 2. 3 is an address decoder circuit which decodes each static RAM from static RAM group 1 by address bus signal 8 and chip enable signal 9.
A static RAM selection signal 13 for selecting RAM 2 is generated.

Static RAM group 1 has a well-known chip enable signal (ττ)9. A write enable signal (WE) 10, an output enable signal (OB) 11°, and a data bus signal 12 are connected. 14 is a power supply input, which becomes an internal power supply 15 via a series diode 16. When the power source 14 is disconnected (cut off) or when the battery is carried, the battery 6 operates, and the series resistor 5. which limits the current. Current flows as an internal power supply 15 through a protection diode 4 that prevents reverse charging.

is supplied to back up the data stored in RAM2.

Further, 7 is an equivalent load capacitor, and 17 is a pull-up resistor. In addition, signals E and CE.

Wl, σ1i is “L” active (operable at “L”).

The circuit shown in FIG. 4 has the minimum necessary dark circuit configuration for a memory card circuit, and is generally well known. Each static RAM 2 of static RAM group 1
Address decoder circuit 3 is used to select. Static R which is the output of this address decoder 3
The AM1jil selection signal 13 is connected to the chip select signal of each corresponding RAM2. That is, the circuit of this conventional memory card is a circuit that outputs each terminal signal of the RAM 2 directly to the outside. Therefore, the operation of the circuit shown in this figure is basically exactly the same as that of the RAM 2 alone.

The operation of this circuit will be explained below.

First, the operation when there is no power source 14 will be explained. R.A.
M2. The voltage of a battery 6 is supplied to the address decoder 3 via a series resistor 5 and a protection diode 4. Further, the RAM selection signal 13 which is the output of the decoder 3 is all at "H" level because the resistor 17 of the chip enable signal 9 is pulled up to the internal power supply 15. Therefore,
The signal 9 of each RAM2 is at the ``H'' level, and the RA
The data bus signal 12 of M2 becomes a floating state. Therefore, the data stored in the RAM 2 does not disappear and can be maintained.

Next, the operation when the power source 14 is supplied from the terminal will be explained. Power source 14 is supplied to internal power source 15 via series diode 16 .

- During boat fishing, the voltage of the internal power source 15 at this time is set higher than that of the battery 6, so the internal power source 15 and the battery 6 are cut off by the action of the protection diode 4. Therefore, battery 6
Since no current flows through it, there is no wear and tear.

Since the read and write operations of the RAM 2 are the same as those of a single RAM, a detailed explanation will be omitted and will be briefly explained below. First, the address bus signal 8 is input from the terminal, and the decoder 3. Applied to RAM2. The decoder 3 has an R corresponding to the address bus signal 8.
The chip enable signal (CE) 9 of AM2 is decoded, but it is actually output when the chip enable signal (CE) 9 of the decoder 3 is at "L" level. Now, suppose that the corresponding RAM2 is selected by the decoder 3 and the chip enable signal σ1 of that RAM2 is "L".
When data from the data bus signal 12 is written into the storage area of M2, it is possible to do so by setting the write enable signal (WE) 10 to the "L" level during the "L" level section of the signal CE. At this time, the output enable signal (OE) 11 is set to the mHs level. Also,
Reading from the storage area of the RAM 2 can be done by setting the "L" level section signal 11 of the signal CE to the "L" level. At this time, the signal 10 is set to the "■(" level). Also, if signal 9 is set to “■(” level), RA
The data bus signal 12 of M2 is in a floating state, and neither reading nor writing is possible.

These operations are identical to those of a standalone RAM - the best known.

[Problem that the invention seeks to solve]

Conventional memory card circuits have the following problems.

1) The single terminal signal of RAM2 is directly exposed (output) to the outside, and when a memory card is inserted or removed while the terminal is operating (power supply 14 is supplied), the memory card and terminal The R
Destroy the data stored in AM2.

2) If the power supply 14 is cut off while the terminal and memory card are connected, and the chip enable signal 9 and write enable signal 10 are at "L" level on the terminal side, the series resistance 5° protection is applied. Diode 4. The current in the battery 6 flows out to the terminal side through the pull-up resistor 17, and the battery 6 is instantly discharged and consumed.

3) Since each terminal signal of RAM2 is basically output to the outside, the static electricity resistance depends on the static electricity resistance of RAM2 alone.

4) The input/output impedance of the memory card when carried is RAM2. It depends on the impedance of the address decoder circuit 3, which is very high impedance for boat fishing, so the static electricity resistance is high.

The electromagnetic field resistance will be a low value.

5) When the RAM2 increases, the input/output capacity of each signal 9 to 12 increases, and the rise and fall times of each signal become very long, and the standard value for RAM20 alone is not satisfied, and the electrical performance becomes very poor. to degrade.

This invention was made to solve the above-mentioned problems, and it is possible to directly remove or insert the memory card when the terminal and the memory card are connected in a live wire state (power-carrying state). The data recorded in semiconductor memory such as RAM can be reliably guaranteed, and the battery current of the memory card will not leak outside, making it a highly reliable large-capacity memory card circuit with high resistance to static electricity and electromagnetic fields. The purpose is to provide

[Means for solving problems]

The memory card circuit according to the present invention has a unidirectional non-inverter buffer with an analog switch connected in series to the terminal signal of the semiconductor memory and connected in parallel to the ground, and a unidirectional non-inverter buffer with the analog switch connected to the input terminal of the semiconductor memory. A three-state buffer is connected to the input/output terminal to interface between the half-quad memory and the terminal, and a series transistor is provided between the power input and the internal power supply of the memory card to connect the terminal and the memory card. A power supply voltage detection circuit is provided which takes as input the card insertion/removal signal and power supply voltage generated by the shortest contact in )/disconnection (cutoff).

[Effect]

In this invention, 1) an address bus signal which is an input signal of a semiconductor memory;
By providing unidirectional non-inverter buffers with analog switches for the signals CE, WE, and OB and bidirectional 3-state buffers with analog switches for the input/output signals, each terminal signal of the semiconductor memory of the memory card is directly exposed to the outside. Even if multiple semiconductor memories are mounted, the same electrical performance as a single one can be achieved.

2) The power supply input and internal power supply are cut/off by a series transistor, and the above-mentioned unidirectional non-inverter buffer with analog switch and bidirectional 3-state buffer are connected by a power supply voltage detection circuit that receives the power supply voltage and card insertion/removal signal as input. (Connection form B).

Or, a signal is generated to disconnect (interrupt state B).

3) The analog switches of the unidirectional non-inverter buffer with analog switch and bidirectional 3-state buffer are connected in series and in parallel to ground for each terminal signal of the semiconductor memory. When the power input is above the specified value, the analog switches connected in series are connected (connected state), and at the same time, the analog switches connected in parallel to the ground are disconnected (interrupting state I).
IE, ), and if the power input is below the specified value, the analog switch connected in series will be disconnected (blocked state), and at the same time, the analog switch connected in parallel to the ground will be connected (connection status B). .

4) By using the means for generating the card insertion/removal signal as the shortest pin contact in the connecting portion between the terminal and the memory card, the card insertion/removal signal is first set to "L" when the memory card is removed. '' level, and maintains the ``L'' level when carrying a memory card, and finally becomes the ``H'' level when inserting the memory guard.

〔Example〕

FIG. 1 shows a memory card circuit according to an embodiment of the present invention. In FIG. 0, 1 to 17 are basically the same as those in FIG. 4. In order to prevent all terminal signals of the RAM 2 from being directly exposed to the outside, the RAM 2 is connected to the outside through a unidirectional non-inverter buffer 18 with an analog switch and a bidirectional 3-state buffer 19 with an analog switch. External power source 14 from the terminal device and internal power source 15 of the memory card 22
A series transistor 20 and a power supply voltage detection circuit 21 are interposed between the two. When carrying the memory card 22, the pull-down resistor (R,) 23 is set to the ground level, that is, 1L level. A card insertion/removal signal 24 is input to activate or deactivate the detection circuit 21. Card insertion/removal signal 24-
When the level is "H", the detection circuit 21 becomes operational, and when the voltage of the power supply 14 reaches a specified value or higher, the transistor 20 becomes conductive and at the same time the detection circuit 21
The connection/disconnection signal 24a becomes "H level", and the buffer 18
．． 19 is connected (connection state A). When the voltage of the power source 14 becomes lower than the specified value, the transistor 20 is turned off (blocked state) and at the same time, the buffers 18 and 19 are also cut off (blocked state B).
When the card insertion/removal signal 24 is at "L" level, the transistor 20. Turn off buffers 18 and 19. Reference numeral 25 is connected to the card insertion/removal signal 24 through a pull-up resistor (RA) 26 on the terminal side, and is the shortest pin contact among all the connections between the terminal and the memory card 22.

FIG. 2(a) is an internal circuit diagram showing the unidirectional non-inverter buffer 18 with an analog switch, and FIG. 2(a) is an explanatory diagram of the equivalent circuit operation thereof.

FIG. 3(a) is an internal circuit diagram showing the bidirectional 3-state buffer 19 with an analog switch, and FIG.
0 is an analog switch for signal control, static R
Connected in series to all AM terminal signals. 31 is a protection analog switch, which is connected to ground. 32 is a non-inverter buffer, 33 is an inverter buffer, 34 is a 3-state buffer A135 is a 3-state buffer B136 is a NAND circuit A137 is an NA
This is ND circuit B. In addition, Fig. 2(a) and Fig. 3(a)
) buffers 18 and 19 generally incorporate N gate circuits, but the internal circuit diagram for each gate is omitted here. Further, each operation of the buffers 18 and 19 is based on truth table 1.2 shown below.

Truth Table 2 To facilitate the explanation of the operation of each part of the memory card circuit of this embodiment shown in FIG. 2 will be explained below.

As shown in FIG. 2), an analog switch 30 and a non-inverter buffer 32 are connected in series between the input terminal and the output terminal, and an analog switch 31 is connected to the ground and the input side of the buffer 32. As shown in truth table 1, when the E terminal is at “H” level, switch 30-
N (connected) and switch 3l-OFF (disconnected). When E terminal is at “L” level, switch 3O-OFF
(discontinued).

The switch 3l is turned ON (closed). In other words, Figure 2 (
In a), when the E terminal becomes "H" level, the buffer 3
2. Switch 3O-ON (connected) through 33.

The switch 3l is turned OFF (disconnected), and the input terminal and output terminal are in a connected state, allowing signal transmission.

Next, when the R terminal becomes “L” level, the buffer 32.3
3, the switch 30 is turned OFF ([) and the switch 3l is turned ON (connected), so that the input terminal and the output terminal are cut off and signal transmission is disabled.

In this case, the interface between the terminal and the memory card is in a cut-off state, but the switch 31 is turned on (connected) and is installed with a resistance value of several tens of ohms to several 100 ohms.
goes to L'' level. Therefore, the RAM
The input terminal No. 2 remains at the "L" level and enters a low impedance state.

Next, the operation of the buffer 19 will be explained.

As shown in truth table 2 in FIG. 3, when the R terminal is at "L" level, the switch 3O-ON (closed).

When the R terminal is at "H" level, the switch 3l is OFF (disconnected), and the switch 30 is OFF (disconnected).

Switch 3l becomes ON (connected), and 100 terminal -″L
If the DI R terminal is at the "L" level under the "L" level condition, the buffer 34 is turned ON (connected), and the signal can be transmitted from the input/output terminal A to the input/output terminal B. However, in the opposite direction, that is, when the input/output terminal Signal transmission from input/output terminal B to input/output terminal A is disabled. Next, when the DIR terminal is at "H'" level, the buffer 35 is turned on (connected) and the signal is transmitted from input/output terminal B to input/output terminal A. Signal transmission becomes possible. Signal transmission in the opposite direction, that is, from input/output terminal A to input/output terminal B, becomes impossible.Also, as shown in truth table 2, 0N10FF of switch 30.31 is connected to R terminal. It is determined by
It can be seen that the DIR terminal becomes effective when the E terminal is at the "L" level. Now, 100 terminals = “L” level.

When the D I Ri terminal is set to “L” level, the buffer 34 is turned on via the buffer 33 and the NAND circuits 36 and 37.
(closed) and buffer 35-Z (closed).

In addition, when the 1 terminal is at the "L" level and the DIR terminal is at the "H" level, the buffer 34 is turned on (off) and the buffer 35 is turned on (on) through the buffer 33 and the NAND circuits 36 and 37.
It turns out that °.゛From the above, if the 261ta terminal of buffer 18 and the R terminal of buffer 19 are disabled, switch 3O-OFF (off) and switch 31-0N (connection) will be established, and the interface between the terminal and the memory card will be shut off. RAM
It can be seen that the input/output terminal of No. 2 is grounded with low impedance.

Next, the operation of each part will be explained by dividing it into the following four modes according to FIG.

Operation mode 1: Operation when the terminal device and memory card are in a live line state (power-carrying state). Operation mode 2: Operation when S is in possession. Operation mode 3: The memory card is transferred from operation mode 2 to a terminal device that is in a live state. Operation when inserting the memory card 22 Operation mode 4: Operation when removing the memory card from operation mode 1 In addition, in FIG.
AM2. Decoder 3. It is assumed that all the power supplies of the buffers 18 and 19 are connected to the internal power supply 15.

First, operation mode 1 will be explained below.

While the power supply 14 is being supplied from the terminal side, the card insertion/removal 13 and 24 are supplied via the pull amplifier resistor 26. Since the card insertion/removal signal 24-H" level is normally set to RtR, the power supply voltage detection circuit 21 is in an operable state. Here, the power supply voltage detection circuit 21 is in an operable state.
When the voltage exceeds a specified value (reaches a normal voltage), the detection circuit 21 operates, connects the series transistor 20, and supplies the power source 14 to the internal power source 15. At the same time, the connection/disconnection signal 24a of the detection circuit 21 becomes @H.
" level, which is supplied to the R terminal of the buffer 18, and the buffer 18 is enabled. Therefore, truth table 1
From switch 3O-ON of buffer 18, switch 3l
- It is turned off and the terminal and memory card are ready for connection. Further, the operation of the buffer 19 is determined by the logic of the input terminals CE and OE of the buffer 18. This will be explained later. Since the voltage value of the internal power supply 15 is higher than the voltage value of the battery 6, the battery 6 is disconnected due to the action of the protection diode 4, and no current flows.In this state, the RA
Reading and writing of M2 are performed in the following steps. First, when address bus 8 is provided from the terminal, buffer 1
8 to the decoder 3. Here, connect the CE terminal “
When the L'' level is applied, the decoder 3 operates and generates the RAM selection signal 13 that selects the RAM 2 of the corresponding address. Therefore, the E terminal of the buffer 19 is enabled, and data bus 12 can be transmitted and received. In this state, if you want to occupy data bus signal 12 in RAM2, use OE
Data can be written by setting the terminal to "H" level and setting the WE terminal to "L" level. Since the signal transmission direction of the buffer 19 is E-“L” and DIR=“H”, from truth table 2, the buffer 35 of the buffer 19 is ON (connected).
It can be seen that the direction is from input/output terminal B to input/output terminal A. In this state, when reading from RAM2 to signal 12 next time, W lower - "H".

If OE-“L′” is set, the internal data of RAM 2 can be taken out to signal 12. Since the direction of signal transmission of the buffer 19 is E = "L" and DIR - "L", according to truth table 2, the buffer 34 is ON (connected), and in the direction from the input/output terminal 100 to the input/output terminal B. I understand something.

Next, operation mode 2 will be explained below.

Since there is no power source 14 from the terminal and the pull-down resistor 23 is at the ground level, the detection circuit 21
is inactive and the transistor 20 is in an OFF state. Therefore, the internal power supply 15 is in a state where the battery voltage is supplied via the battery 6, the series resistor 5, and the diode 4. That is, the state in which the data stored in the RAM 2 is held is maintained. On the other hand, the buffer 180E terminal is in a disabled state since the connection/disconnection signal 24a of the detection circuit 21 is at the "L" level. Also, since the σT terminal is blocked by the buffer 18, the trap terminal of the buffer 19 is pulled up by the resistor 17 and becomes H", and is in the disabled state. Therefore, from truth table 1.2, switch 3
O-OFF (1!J1).

It can be seen that the switch 3l is turned ON (connected) and all terminal signals of the RAM 2 are at low impedance.

Therefore, it can be seen that when carrying a memory card, the static electricity and electromagnetic field resistance can be significantly improved compared to the RAM 2 alone.

Next, operation mode 3 will be explained below.

When the memory card is inserted into a terminal in a live state from operation mode 2, the action of the memory card coupling part 25 works effectively.

That is, at the moment when the memory card is inserted into the terminal, the connecting portions other than the short pin contacts 25 are first connected. At this time, since the contacts 25 are not in contact yet, the operation mode 2 continues. Subsequently, the card insertion/removal signal 24 is supplied for the first time when the contact 25 makes contact, and the operation mode 1 is entered. Therefore, even if the memory card 22 is inserted while the terminal is in a live state, it will not be affected by level fluctuations and time differences of terminal signals of the terminal occurring at the coupling portion. .

In other words, all terminal signals of RAM2 are inserted while maintaining a low impedance state, so even if static electricity or noise due to electromagnetic fields enters during insertion, there is no problem at all.The subsequent operation is the same as operation mode 1. Since there is, I will omit it.

Finally, operation mode 4 will be explained below.

When removing the memory card from operation mode 1, the memory card coupling portion 25 works effectively. That is, since the contact 25 of the connection part with the terminal device is separated first, the card insertion/removal signal 24 disappears and the resistor 23 instantaneously goes to the "L" level. Therefore, the detection circuit 21 becomes inoperative, the transistor 20 becomes 0FF (off), and the connection/disconnection signal 24a of the detection circuit 21 also becomes "L" level. Therefore, the E terminal of the buffer 18 becomes "L" and becomes disabled.

Further, since the buffer 18 is disabled, the surface terminal of the buffer 19 is cut off, and is pulled up by the action of the resistor 17 to become "H" level or disabled. This state is the same as operation mode 2. After this, the terminal's other terminal signals are removed. At this time, it is completely unaffected by the temporal difference in level fluctuations occurring at the joint.

Further, since all terminal signals of the RAM 2 are in a low impedance state, they are not affected by static electricity or electromagnetic fields, and it is possible to completely remove the data stored in the RAM 2 without destroying it.

From the above operation, even if the memory card is inserted or removed while the terminal is in a live line state, the data stored in the RAM 2 is guaranteed. Furthermore, it is possible to significantly improve static electricity and electromagnetic field resistance when carrying the device.

In addition, according to the above embodiment, the semiconductor memory is statically R
Although AM is used, the present invention can be applied to other OTP (one-time programmable) ROMs and mask ROMs except for batteries, series resistors, and protection diodes.

The same effects as in the above embodiment can be expected in semiconductor memories such as EEPROMs.

Furthermore, although the unidirectional non-inverter buffer with analog switch and the bidirectional 3-state buffer with analog switch can be configured using well-known ICs, it is also easy to integrate them into one integrated circuit or to form the entire circuit into a gate array. possible. Furthermore, it is possible to form a gate array including a power supply voltage detection circuit using well-known techniques. Therefore, significant cost reduction is possible.

〔Effect of the invention〕

As described above, the memory card circuit according to the present invention has the following effects.

1) All terminal signals of the semiconductor memory are not directly exposed to the outside, but are connected to the terminal via a unidirectional and bidirectional buffer with an analog switch, so even if multiple semiconductor memories are installed, the electrical characteristics of a single product can be maintained. is obtained. Therefore, even if the wiring of the interface bus with the terminal device becomes long, the electrical characteristics do not deteriorate, and a highly reliable large capacity memory card can be realized.

2) The analog switches of the unidirectional and bidirectional buffers are connected in series to the terminal signal of the semiconductor memory and in parallel to the ground, and a series transistor is installed between the power input and the internal power supply to connect the terminal and the memory. A power supply voltage detection circuit is provided that receives the card insertion/removal signal and power supply voltage generated by the shortest contact at the connection part with the card, and its output signal connects/disconnects the series transistor and the unidirectional and bidirectional buffers. This prevents the memory data from being destroyed even if the card is inserted or removed while the terminal is in a live wire state, and all terminal signals of the semiconductor memory are reliably cut off from the terminal at the moment of insertion or removal. It can be made into an impedance, has extremely high resistance to static electricity and electromagnetic fields, and can significantly improve noise resistance.

Furthermore, the noise resistance performance is greatly improved even when carrying the card. Furthermore, it is possible to prevent battery current from flowing to the terminal when there is no power input.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a memory card circuit according to an embodiment of the present invention, FIG. 2(a) is an internal circuit diagram showing a non-inverter buffer with an analog switch, and Part 2) is an explanation diagram of its equivalent circuit operation. FIG. 3(a) is an internal circuit showing a 3-state buffer with an analog switch. FIG. 1 is a static RAM group, 2 is a static RAM, 3 is an address decoder circuit, 4 is a protection diode, 5 is a series resistor, 6 is a battery, 7 is a capacitor, 8 is an address bus signal, 9 is a chip enable signal (τ100) , 10 is a write enable signal (WE), 11 is an output enable signal (OR), 12 is a data bus signal, 18 is a unidirectional non-inverter buffer with an analog switch, 1
9 is a bidirectional 3-state buffer with analog switch, 2
0 is a series transistor, 21 is a power supply voltage detection circuit,
22 is a memory card, 23 is a pull-down resistor, 24 is a card insertion/removal signal, 25 is the shortest short pin contact, 30
is an analog switch for signal control, 31 is an analog switch for protection, 32 is a non-inverter buffer, 33 is an inverter buffer, 34 is 3-state buffer A, 35 is 3-state buffer B 136 is NAND circuit A circuit element is NAND circuit B be. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. 182 Figure E'1J-7 leaked IR

Claims (1)

[Claims] (1) In a memory card circuit having a portable memory card, an analog switch connected in series to the terminal signal of the semiconductor memory and in parallel to the ground for interfacing between the semiconductor memory and the terminal device. a unidirectional non-inverter buffer with an analog switch provided inside the memory card and connected to the input terminal of the semiconductor memory, and a bidirectional 3-state buffer with an analog switch connected to the input/output terminal, and the terminal device A card insertion/removal signal generated by a series transistor provided between the power input from the terminal and the internal power supply of the memory card, and the shortest contact among the contacts at the joint between the terminal and the memory card, and the memory card. Take the card power supply voltage as input,
A memory card circuit characterized in that it is equipped with a power supply voltage detection circuit that outputs a signal for connecting or disconnecting the series transistor, the unidirectional non-inverter buffer with an analog switch, and the bidirectional 3-state buffer with an analog switch. .