JPH01116448U - - Google Patents
Info
- Publication number
- JPH01116448U JPH01116448U JP1988011636U JP1163688U JPH01116448U JP H01116448 U JPH01116448 U JP H01116448U JP 1988011636 U JP1988011636 U JP 1988011636U JP 1163688 U JP1163688 U JP 1163688U JP H01116448 U JPH01116448 U JP H01116448U
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- semiconductor integrated
- periphery
- power supply
- utility
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000000605 extraction Methods 0.000 description 3
- 230000020169 heat generation Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988011636U JPH01116448U (ko) | 1988-01-30 | 1988-01-30 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1988011636U JPH01116448U (ko) | 1988-01-30 | 1988-01-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01116448U true JPH01116448U (ko) | 1989-08-07 |
Family
ID=31220364
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1988011636U Pending JPH01116448U (ko) | 1988-01-30 | 1988-01-30 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01116448U (ko) |
-
1988
- 1988-01-30 JP JP1988011636U patent/JPH01116448U/ja active Pending