JPH01114159A - Intermediate tone picture processing method - Google Patents

Intermediate tone picture processing method

Info

Publication number
JPH01114159A
JPH01114159A JP62270871A JP27087187A JPH01114159A JP H01114159 A JPH01114159 A JP H01114159A JP 62270871 A JP62270871 A JP 62270871A JP 27087187 A JP27087187 A JP 27087187A JP H01114159 A JPH01114159 A JP H01114159A
Authority
JP
Japan
Prior art keywords
row
dither matrix
digital signal
dither
threshold value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62270871A
Other languages
Japanese (ja)
Inventor
Katsumi Sakamoto
阪本 克巳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP62270871A priority Critical patent/JPH01114159A/en
Publication of JPH01114159A publication Critical patent/JPH01114159A/en
Pending legal-status Critical Current

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  • Facsimile Image Signal Circuits (AREA)
  • Image Processing (AREA)

Abstract

PURPOSE:To eliminate flickering of the screen and to obtain a picture with high quality by using dither matrices adjacent in lateral direction in the state of deviation in longitudinal direction in using the dither matrix to generate a binary intermediate picture. CONSTITUTION:A dither matrix memory 5 outputs a threshold value sequentially from the left end of the 1st row of the 1st dither matrix in the right direction and then from the left end of the 1st row of the 2nd dither matrix in the right direction in response to the pattern address generated from an address generating circuit 6. The operation above is repeated to a digital signal by one row and then the processing is advanced to the 2nd row and the 3rd row of the matrix. Then the threshold value outputted sequentially from the memory 5 and the digital signal outputted from a correction circuit 4 are compared by a comparator circuit 8 and only when the level of the digital signal is larger than the threshold value, a black picture element signal is outputted. Since the black picture elements exist scattering, the object is attained.

Description

【発明の詳細な説明】 げ)産業上の利用分野 本発明はディザマトリクスを使用して2値中間調画像を
生成する中間調画像処理方法に関する。
DETAILED DESCRIPTION OF THE INVENTION G) Industrial Application Field The present invention relates to a halftone image processing method for generating a binary halftone image using a dither matrix.

(ロ)従来の技術 情報ファイル装置またはファクシミリ装置等では、光学
的に原稿から読取った画像をドツト状の画素に分解し、
各画素を黒、白の2値信号とする画像処理が行なわれて
いる。
(b) Conventional technical information filing devices or facsimile devices optically read an image from a document and decompose it into dot-shaped pixels.
Image processing is performed in which each pixel is converted into a binary signal of black and white.

また、この種の画像処理において、写真等の濃淡画像に
対しては、ディザマトリクスを用G)るデイザ法により
、2値化処理を行ない、擬似的に2値中間調信号を得る
。斯るデイザ法については、日刊工業新聞社発行のrF
AX 、OAのための画像の信号処理」(昭和57年1
0月20日発行)の第16頁乃至第25頁における「中
間調画像の2値表示装置による擬似中間調表示」なる記
事に詳細に示されているように、第5図の如く、種々の
閾値からなる4に4のマトリクス(本件ではうず巻き型
マトリクス)を1単位分とし、斯るマトリクスを第6図
の如く縦、横に同じように配置して、読取った画像を2
値信号に変換するものである。
Furthermore, in this type of image processing, for grayscale images such as photographs, binarization processing is performed using a dither method using a dither matrix to obtain a pseudo binary halftone signal. Regarding such dither method, please refer to rF published by Nikkan Kogyo Shimbun.
“Image signal processing for AX, OA” (1981)
As shown in detail in the article ``Pseudo-halftone display using a binary display device for halftone images'' on pages 16 to 25 of the issue (published on October 20th), as shown in Figure 5, various A 4 by 4 matrix (in this case, a spiral matrix) consisting of threshold values is taken as one unit, and such a matrix is arranged vertically and horizontally in the same way as shown in Figure 6, and the read image is divided into two.
It converts it into a value signal.

四 発明が解決しようとする問題点 ところで、第6図に示すディザマトリクスを用いて一様
に4の濃度レベル(薄い灰色)の画像を2値信号に変換
した場合、第7図に示すパターンになるユこれを半分の
解像度のCRTデイスプレィに表示すべく、奇数行及び
奇数列を間引くと、そのパターンは第8図に示すように
、−行毎(及び−列毎)に黒画素がチ見われる画像とな
る。
4. Problems to be Solved by the Invention By the way, when an image with a uniform density level of 4 (light gray) is converted into a binary signal using the dither matrix shown in Fig. 6, the pattern shown in Fig. 7 is obtained. In order to display this on a CRT display with half the resolution, if the odd rows and odd columns are thinned out, the pattern will be as shown in Figure 8, with black pixels appearing in every -row (and -column). The image will be displayed.

然るに、CRTデイスプレィによる表示は、−般にイン
ターレース方式により奇数行及び偶数行を交互に用いて
行なうつこのため、第8図のように、−行毎に黒画素が
壜われるような画像は、CRTデイスプレィ上で暗の画
面(奇数行の表示)と明の画面(偶数行の表示)とが交
互に表われる状態に表示されることとなり、画面のちら
つきが発生する。
However, displays on CRT displays are generally performed using an interlaced method, alternately using odd and even lines. Therefore, as shown in FIG. 8, an image with black pixels in each line is On the CRT display, a dark screen (display on odd-numbered lines) and a bright screen (display on even-numbered lines) are alternately displayed, and the screen flickers.

このような画面のちらつき状態は、第6図のデ、イザマ
) IJクスの使用パターンにおいて7の濃度レベル(
灰色)までの各画像を2値信号に変換した場合にも同様
に発生する。
This flickering state of the screen is caused by the density level 7 in the IJ mask usage pattern (Fig. 6).
A similar problem occurs when each image up to (gray) is converted into a binary signal.

また、間引くことのない第6図に示す原パターンにおい
ても、所定の行に黒画素が片寄るため、品質的には良い
と言えない。
Furthermore, even in the original pattern shown in FIG. 6 which is not thinned out, the quality cannot be said to be good because the black pixels are concentrated in a predetermined row.

本発明の目的は、画面のちらつきをなくし、また高品質
画像を得ることにある。
An object of the present invention is to eliminate screen flickering and obtain high quality images.

に)問題点を解決するための手段 本発明はディザマ) IJクスを使用して2値中間調画
像を生成する装置において、横方向に隣り合う上記ディ
ザマトリクスが縦方向にずれて使用されていることを特
徴とする。
In an apparatus for generating a binary halftone image using an IJ matrix, the dither matrices that are adjacent in the horizontal direction are used with a shift in the vertical direction. It is characterized by

(ホ)作用 本発明のように、横方向に隣り合うディザマトリクスが
縦方向にずれて使用されることにより、黒画素が多くの
行に分散されて現われるようになる。
(e) Effect: As in the present invention, by using dither matrices that are adjacent in the horizontal direction and shifted in the vertical direction, black pixels appear distributed over many rows.

(へ)実施例 第1図は本発明方法を用いた画像読取装置の一実施例を
示すブロック図である。(1)は原稿(図示せず)上の
画像を電気信号に変換するC0D(電荷結合素子)等か
らなる読取センサ、(2)は電気信号を所定レベルに増
幅する増幅回路、(3)は増幅された電気信号をデジタ
ル信号に変換するA/D変換回路、(4)はデジタル信
号のシェーディング補正等を行なう補正回路、(5)は
予め定められたディザマトリクスを記憶するディザマト
リクスメモリ、(6)はディザマトリクスメモリ(5)
にパターンアドレスを出力するアドレス発生回路、(7
)はA/D変換回路(3)、補正回路(4)の動作制御
を行なうとともに、その制御に対応したパターンアドレ
スがアドレス発生回路(6)から出力されるようにアド
レス発生回路(6)を制御する制御回路、(8)は補正
回路(4]から与えられるデジタル信号とディザマトリ
クスメモリ(5)から読出された閾値とを比較し、デジ
タル信号のレベルが閾値より大きい場合にのみ黒画素信
号を出力する動作により、黒、白の2値信号を発生する
比較回路、(9)は黒、白の2値信号を出力する出力イ
ンターフェイスであり、この出力インターフェイスの出
力がCRTデイスプレィ(図示していない)に表示され
ることになる。
(f) Embodiment FIG. 1 is a block diagram showing an embodiment of an image reading apparatus using the method of the present invention. (1) is a reading sensor consisting of a C0D (charge-coupled device) or the like that converts an image on a document (not shown) into an electrical signal, (2) is an amplifier circuit that amplifies the electrical signal to a predetermined level, and (3) is (4) is a correction circuit that performs shading correction of the digital signal, etc.; (5) is a dither matrix memory that stores a predetermined dither matrix; 6) is dither matrix memory (5)
An address generation circuit that outputs a pattern address to (7)
) controls the operation of the A/D conversion circuit (3) and the correction circuit (4), and also controls the address generation circuit (6) so that the pattern address corresponding to the control is output from the address generation circuit (6). The control circuit (8) compares the digital signal given from the correction circuit (4) with the threshold value read from the dither matrix memory (5), and outputs the black pixel signal only when the level of the digital signal is higher than the threshold value. (9) is an output interface that outputs black and white binary signals, and the output of this output interface is displayed on a CRT display (not shown). (not available) will be displayed.

本発明は、第2図に示すように、横方向に隣り合う第5
図の如き4に4の大きさの1単位分のディザマトリクス
が、縦方向にずれて(本実施例で2行分ずれて)使用さ
れるようにしたものである。
As shown in FIG.
As shown in the figure, the dither matrix for one unit having a size of 4 by 4 is used shifted in the vertical direction (shifted by two rows in this embodiment).

このために、ディザマトリクスメモリ(5)には、第2
図に破線枠で示すように、正規の状態のパターンの第1
ディザマトリクスとこれを2行分ずらして形成したパタ
ーンの第2ディザマトリクスとが記・戊、されている。
For this purpose, the dither matrix memory (5) contains a second
As shown by the dashed frame in the figure, the first pattern in the normal state
A dither matrix and a second dither matrix formed by shifting the dither matrix by two lines are described.

以下、斯る画像読取装置の動作について説明する。所定
の位置に原稿(図示せず)をセットすると、読取センサ
(1)は原稿上の画像を一行分づつアナログ電気信号に
変換する。このアナログ電気信号は増幅回路(2)によ
り所定のレベルにまで増幅された後、A/D変換回路(
3)に入力され、ここでデジタル信号に変換される、斯
るデジタル信号は補正回路(4)に入力されてシェーデ
ィング補正等の補正処理がなされる。この時、制御回路
(7)はA/D変挽変格回路)及び補正回路(4)の動
作を制御すると共に、この制御に対応してアドレス発生
回路(6)から適宜のパターンアドレスが発生されるよ
うに、アドレス発生回路(6)の動作を制御している。
The operation of such an image reading device will be explained below. When a document (not shown) is set at a predetermined position, a reading sensor (1) converts the image on the document line by line into analog electrical signals. This analog electrical signal is amplified to a predetermined level by the amplifier circuit (2), and then the A/D conversion circuit (
3), where the digital signal is converted into a digital signal.The digital signal is input to a correction circuit (4) and undergoes correction processing such as shading correction. At this time, the control circuit (7) controls the operation of the A/D conversion circuit (A/D conversion circuit) and the correction circuit (4), and in response to this control, an appropriate pattern address is generated from the address generation circuit (6). The operation of the address generation circuit (6) is controlled so that the address generation circuit (6)

斯る制御のFにアドレス発生回路(6)から発生するパ
ターンアドレスに応じて、ディザマトリクスメモリ(5
)は第1デイザマドIJクスの第1行左端から嵩右方向
・\、読いて第2ディザマトリクスの第1行左端から右
方向へ、順次閾値を出力する。この動作は1行分のデジ
タル信号に対して繰り返し行なわれ、その後、マ) I
Jクスの第2行、第3行へと進むつこうして、ディザマ
トリクスメモリ(5)から順次出力される閾値と補正回
路(4)から出力されるデジタル信号とが、比較回路(
8)により比較され、デジタル信号のレベルが閾値より
大きい場合にのみ黒画素信号が出力される。例えば、本
実施例の第2図のディザマ) IJクスを用いて4の濃
度レベルの画像を2値信号に変換すると、第3図に示す
如く、黒画素が所定行に片寄らず、多くの行に現われ、
良品質の中間調画像が得られる。
According to the pattern address generated from the address generation circuit (6) in F of such control, the dither matrix memory (5)
) is read from the left end of the first row of the first dither matrix in the vertical and rightward directions, and sequentially outputs the threshold values from the left end of the first row of the second dither matrix to the right. This operation is repeated for one row of digital signals, and then
In this way, the threshold value sequentially output from the dither matrix memory (5) and the digital signal output from the correction circuit (4) are transferred to the comparison circuit (
8), and a black pixel signal is output only when the level of the digital signal is greater than the threshold value. For example, when an image with a density level of 4 is converted into a binary signal using the dithering device (IJ) shown in FIG. 2 of this embodiment, as shown in FIG. appeared in
Good quality halftone images can be obtained.

更に、この画像の奇数行及び奇数列を間引くと、そのパ
ターンは第4図に示すように奇数行及び偶数行共に黒画
素が現われるので、これをインターレース方式のCRT
デイスプレィに表示してもちらつきは生じない。
Furthermore, if the odd rows and odd columns of this image are thinned out, black pixels will appear in both the odd and even rows, as shown in Figure 4.
No flickering occurs when displayed on a display.

なお、ディザマトリクスの大きさ及びずらし虚は本実施
例に限らず、適宜に設定すればよい。
Note that the size of the dither matrix and the shift imaginary are not limited to those in this embodiment, and may be set as appropriate.

(ト)発明の効果 本発明によれば、横方向に隣り合うディザマトリクスが
縦方向にずれた状態で使用されているので、黒画素が所
定の行に片寄らず、分散されて存在するようになる。従
って、ちらつきのない画面表示、高品質の画像を得るこ
とができる、
(G) Effects of the Invention According to the present invention, dither matrices that are adjacent in the horizontal direction are used in a state that they are shifted in the vertical direction, so that the black pixels are not concentrated in a predetermined row but are dispersed. Become. Therefore, flicker-free screen display and high-quality images can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係わる画像読取装置を示すブロック図
、第2図は本発明方法におけるディザマトリクスの使用
状態を示す模式図、第3図は本発明方法により得られる
中間調画像の一例を示す模式図、第4図はこの中間調画
像の間引き処理を行なった状態の画像を示す模式図、第
5図はディザマトリクスの典型例を示す模式図、第6図
は従来のディザマ) IJクス使用パターンを示す模式
図、第7図は従来例にて得られる中間調画像の一例を示
す模式図、第8図はこの中間調画像の間引き処理を行な
った状態の画像を示す模式図であるつ(Li・・・読取
センサ、(5)・・・ディザマトリクスメモリ、(8)
・・・比較回路、
FIG. 1 is a block diagram showing an image reading device according to the present invention, FIG. 2 is a schematic diagram showing how a dither matrix is used in the method of the present invention, and FIG. 3 is an example of a halftone image obtained by the method of the present invention. 4 is a schematic diagram showing an image after the halftone image has been thinned out, FIG. 5 is a schematic diagram showing a typical example of a dither matrix, and FIG. 6 is a conventional dither matrix.) FIG. 7 is a schematic diagram showing an example of a halftone image obtained in the conventional example, and FIG. 8 is a schematic diagram showing an image after thinning processing of this halftone image. (Li...reading sensor, (5)...dither matrix memory, (8)
...comparison circuit,

Claims (1)

【特許請求の範囲】[Claims] (1)ディザマトリクスを使用して2値中間調画像を生
成する装置において、横方向に隣り合う上記ディザマト
リクスが縦方向にずれた状態で使用されていることを特
徴とした中間調画像処理方法。
(1) A halftone image processing method, characterized in that in a device that generates a binary halftone image using dither matrices, the dither matrices that are adjacent in the horizontal direction are used in a state that they are shifted in the vertical direction. .
JP62270871A 1987-10-27 1987-10-27 Intermediate tone picture processing method Pending JPH01114159A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62270871A JPH01114159A (en) 1987-10-27 1987-10-27 Intermediate tone picture processing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62270871A JPH01114159A (en) 1987-10-27 1987-10-27 Intermediate tone picture processing method

Publications (1)

Publication Number Publication Date
JPH01114159A true JPH01114159A (en) 1989-05-02

Family

ID=17492126

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62270871A Pending JPH01114159A (en) 1987-10-27 1987-10-27 Intermediate tone picture processing method

Country Status (1)

Country Link
JP (1) JPH01114159A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6687023B1 (en) * 2000-04-17 2004-02-03 International Business Machines Corporation Data processing system and method for producing shifted-element halftone screens
US7636111B2 (en) 2004-10-28 2009-12-22 Canon Kabushiki Kaisha Image capturing device having a distortion-reduction unit configured to reduce geometrical distortion caused by an imaging lens in an image progressive signal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6687023B1 (en) * 2000-04-17 2004-02-03 International Business Machines Corporation Data processing system and method for producing shifted-element halftone screens
US7636111B2 (en) 2004-10-28 2009-12-22 Canon Kabushiki Kaisha Image capturing device having a distortion-reduction unit configured to reduce geometrical distortion caused by an imaging lens in an image progressive signal

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