JPH01114073A - Solid-state image sensor - Google Patents

Abstract

PURPOSE:To suppress a dark current generated in an element separation region by making film thickness of a gate insulating film on a separation region between the photoelectric conversion elements, and between the photoelectric conversion element and a charge transfer means to be different according to the regions. CONSTITUTION:A gate oxide film 17 under a gate electrode 15 on an element separation region 10 between the photoelectric conversion element parts 7, and between the photoelectric conversion element part 7 and a vertical CCD shift resistor part 9 is formed so as to have thicker film thickness than a gate oxide 16 under a signal read gate part 8. Thereby, even when high voltage is impressed on the gate electrode 15 for the purpose of read of a signal, holding and transfer of charge of vertical CCD, depletion of the surface of a high density diffusion layer 14 for channel stop due to rising threshold value voltage is suppressed so as to suppress generation of a dark current in the element separation region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device, and particularly to a solid-state imaging device having a structure suitable for reducing dark current.

[Conventional technology]

Conventionally, in solid-state image sensors, 4! Gansho 59-146822
As described in the above issue, each photoelectric conversion element group or the element isolation region between the photoelectric conversion elements and the charge transfer means is covered with a thick oxide film by the usual LOCO8 method.

However, in the LOCO8 method, miniaturization is hindered by the lateral growth of the oxide film (bird's beak) and the reduction in channel width due to lateral diffusion of the high concentration impurity layer provided under the thick oxide film.

For this reason, etc., a gate insulating film (thin oxide film) and a gate electrode are provided in the element isolation region, and active
The field plate method, which performs element isolation using MOS (e') transistors, has been reconsidered.

As an example of this field plate type element,
Some are described in the Technical Report of the Television Society of Japan, ED87-9 (February 1987), pages 19-24.

[Problem that the invention seeks to solve]

A conventional field plate type solid-state imaging device is shown in FIG.

Figure 2 is from the Television Society Technical Report, ED87-9 (
This figure shows a pixel cross section of the field plate type solid-state image sensor shown in pp. 19-24 (Feb., 1987). 31 is a photoelectric conversion element section consisting of a photodiode, 32 is a readout gate section, and 33 is a vertical charge transfer means (CCD).

34 is an element isolation region. 35 is a high concentration layer p" (same conductivity type as the p-well) for element isolation; 36 is an impurity layer N forming a photodiode (same conductivity type as the N substrate); 3
7 is a high concentration P+ layer (same conductivity type as the P- well) provided above the impurity layer 36 forming the photodiode; 38;
is a gate electrode (shared with readout gate and vertical CCD transfer gate).

39 is a gate oxide film. In this way, the element isolation region 3
4 is controlled by a gate electrode 38. In this unconventional element, when a high-level voltage is applied to the gate electrode, the surface of the heavily doped layer 35 is also depleted, and unnecessary noise charges are generated due to dark current. On the other hand, by providing the highly-concentrated P'' layer 35, the threshold voltage is increased to make it difficult to deplete the element isolation region, thereby reducing the generated dark current charges.

However, since the gate oxide film is thin, even if the surface concentration of the P'' layer is high, for example, about 10"cm-", the threshold voltage is at most about 2 V (for example, if the gate oxide film thickness is 350 cm-"
During operation, a depletion layer is generated and a dark current charge is generated.

The above-mentioned conventional elements do not take this point into consideration, resulting in problems such as an increase in random noise due to dark current, uneven white spots due to variations in dark current, and fixed pattern noise.

An object of the present invention is to suppress dark current in this element isolation region.

[Means for solving problems]

The above purpose is to protect a part of the gate insulating film on the isolation region between the photoelectric conversion elements (photodiodes) and between the photoelectric conversion element and the charge transfer means (for example, CCD), especially the gate on the area other than the part that becomes the charge transfer path. This is achieved by increasing the thickness of the insulating film.

[Effect]

The threshold voltage Vte of a MOS transistor is the charge per rough unit area *Cox: unit area of oxide film εox relative dielectric constant of dioxide film, e, 6: dielectric constant of vacuum.

(Tox: gate oxide film thickness), if the VTOC film thickness To is made about twice as high, the threshold voltage V becomes about 6 times as high, and even during operation when a high voltage is applied to the gate electrode, separation is possible. Accumulate the area / Yo7 (Ac
(cumulation) state.

Dark current can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG.

FIG. 1(a) is a plan view of the light receiving section of the solid-state image sensor,
1 is a photoelectric conversion element, 2 is a vertical COD shift register with two-phase drive, and 3. ．． g of 4d vertical CCD shift register
l! 1. The second transfer electrode 3 also serves as a signal readout electrode for sending the optical signal charges accumulated in the photoelectric conversion element 1 to the vertical COD shift register. Reference numeral 5 indicates a channel region (channel means a path of charge) of the signal readout electrode.

8g1 (b) is an example of a sectional view taken along the line AA' in FIG. 1 (a), where 7 is a photoelectric conversion element section, 8 is a signal readout gate section, and 9 is a vertical CCD shift register section.

10 is an element isolation region. 1.1 is a silicon substrate (for example, P type); 12 is a diffusion layer (for example, N type) forming a photoelectric conversion element; 13 is a diffusion layer (for example, N type) forming a buried channel of the vertical CCD shift register;
is a high concentration diffusion layer for channel stop (e.g. shrimp P type), 1
5 is a gate electrode (shared as a vertical COD transfer electrode and a signal readout electrode). Reference numerals 16 and 17 are gate oxide films having different thicknesses according to the present invention. Further, 18 indicates a light-shielding metal film. Here, signal readout and vertical COD
Even if a high voltage is applied to the gate electrode 15 to retain and transfer charges, the gate oxide film 17 (for example, 200 OA thick) under the gate electrode 15 in the element isolation region 10
) is the gate oxide film 16 under the signal readout gate section 8.
(for example, a film thickness of 350 mm), the threshold voltage increases and depletion of the surface of the channel stop high concentration diffusion layer 14 (for example, a surface concentration of 10"cm-") can be suppressed. This makes it possible to suppress the generation of dark current in the element isolation □ region.

FIG. 3 shows another embodiment, which corresponds to FIG. 1(b). Here, 15' is a gate electrode (shared with vertical CCD transfer electrode and signal readout electrode).

16' and 17' are gate oxide films, respectively.

A part of the gate oxide film under the gate electrode 15' in the element isolation region 10 is formed with a thick gate oxide film 17'. As a result, the gate oxide film 17'
It is possible to suppress depletion of the surface of the lower heavily doped channel stop layer 14, and also depletion under the gate electrode of the thin gate oxide film 16' of the element isolation region 10, generating dark current. Even if the gate oxide film 17' is thick, there will be some damage.

Since a mechanical barrier is formed, it is possible to prevent dark current charges from entering the photoelectric conversion element section 7.

FIG. 4 shows another embodiment, which corresponds to FIG. 1(b). Diffusion 14i forming a photoelectric conversion element
It is clear that even if a heavily doped diffusion layer 20 (for example, P type) is provided on the silicon surface of 12' (for example, N type), the dark current from the isolation region can be reduced in the same way as in FIG. Here, by the lateral diffusion of the high concentration diffusion layer 20, the threshold voltage of the isolation region can be further increased, and the effects of the present invention can be further enhanced. Further, due to the lateral diffusion of the high concentration diffusion layer 20, the surface concentration of the channel stop high concentration layer 14 becomes higher, and the electric field under the gate becomes stronger when a high voltage is applied to the gate electrode 15. Dark current newly generated due to this high electric field can also be reduced by the effect of the thick gate oxide film 17, as the electric field is relaxed.
゛FIG. 5 shows yet another embodiment. Figure 5(a) is the first
The gate electrodes 3 and 4 in FIG.
Transfer electrodes 3/ and 4/ (for example, second and third layers of polysilicon) are made independent.

FIG. 5(b) is an example of a cross-sectional view taken along line BB' in FIG. The gate oxide films 25 and 26 under the gate oxide films 23 and 22' are made thicker as are the gate oxide films 24 in other regions. Here, the gate oxide films 25 and 26 may have substantially the same thickness or different thicknesses. As a result, accumulation (A
(ccumulation) state. "-! Figure 85 (C) is an example of a cross-sectional view taken along the line c-c' in Figure 5 (a). 41 is a gate electrode for signal readout; 2
3' is a vertical COD transfer electrode. or.

24', 25', and 26' are gate oxide films having different thicknesses according to the present invention. Here, the gate oxide films 25' and 26', which are thicker than the gate oxide film 24', may have substantially the same thickness or different thicknesses. The gate oxide film under the signal readout polarization 41 is replaced with a thick gate oxide film 26' (
By making the gate oxide film 24' thinner (for example, 500 mm thick) and thinner (for example, 350 mm thick), the potential inside the substrate during signal readout can be controlled.

FIG. 6 shows still another embodiment, in which a wiring 27 (for example, a first layer of polysilicon) is provided in the separation region between the photoelectric conversion element 1 and the vertical CCD shift register 2 in the plan view of FIG. 5(a).
, and a part of the wiring 27 is connected to an over 70-M2S transistor for suppressing blooming (pluming is a phenomenon in which excess charge overflows to the adjacent vertical COD and generates a vertical white @ on the monitor). is added.

Here, 28 is the channel of the overflow MOS transistor, 2911 through hole, 30u, through hole 2
9 is an overflow drain connected to the wiring 27. Even with the addition of this overflow MOS transistor, the effects of the present invention do not change at all.1 For example, by thinning the gate oxide films of channels 5 and 28,
Dark current generated from one isolation region can be suppressed by thickening the gate oxide film in the other isolation regions. Further, the overflow MO8) transistor may have a drain shared by two photoelectric conversion elements (upper and lower), or may have a different shape.

In the above embodiments, it is also effective to change the combination of these. For example, the high concentration diffusion layer 20 provided in FIG. 4 is applied to the embodiments in FIGS. 3, 5, and 6. The present invention can also be carried out in the same manner.

Also, the vertical CCD was explained as being driven by two phases.

It is clear that the present invention is applicable regardless of vertical COD driving. Furthermore, a structure in which a vertical COD buried channel is formed in the well can also be used as a photodiode tMO.
Also as an s diode structure.

The present invention is applicable. Further, even in a solid-state imaging device in which a P-type well is formed on an N-type substrate, the effect of the present invention of reducing the dark current in one isolated region remains the same.

〔Effect of the invention〕

According to the present invention, in a field plate type solid-state imaging device in which separation between photoelectric conversion elements and between a photoelectric conversion element and a charge transfer means is performed by a gate electrode via a gate insulating film, a portion under the gate electrode is provided. This has the effect of suppressing the generation of dark current in the one-separation region because it is always in the achievable state.

[Brief explanation of the drawing]

FIG. 1(a) is a plan view of one embodiment of the present invention, and FIG.
) is a cross-sectional view taken along the line A-A' in FIG. 1(a), FIG. 2 is a cross-sectional view of the conventional example, and FIGS.
5(a) is a plan view of another embodiment of the present invention, and FIG. 5(b) and (C) are respectively BB in FIG. 5(a). A sectional view taken along the line C-C" and a plan view of still another embodiment of the present invention are shown in FIG. ', 24, 25, 26.24', 25'. Figure 21 2'/

Claims (1)

[Scope of Claims] 1. A plurality of photoelectric conversion elements and a charge transfer means for transferring signal charges accumulated in the group of photoelectric conversion elements are integrated on the same semiconductor substrate, and a plurality of photoelectric conversion elements are integrated between the photoelectric conversion elements and between the photoelectric conversion elements. A solid-state imaging device in which a gate electrode is provided on a semiconductor substrate in a separation region between the charge transfer means and the charge transfer means via a gate insulating film, wherein the thickness of the gate insulating film differs depending on the region. element. 2. The solid-state imaging device according to claim 1, wherein the thickness of the gate insulating film under the gate electrode in the isolation region is increased except for the charge transfer path. 3. In claim 1, furthermore, an overflow MOS transistor is provided in the isolation region between the photoelectric conversion element and the charge transfer means for sweeping out excess signal charge to the outside, and at least the gate electrode of the overflow MOS transistor is provided. A solid-state imaging device characterized in that a part of the gate electrode also serves as a part of the gate electrode. 4. The solid-state imaging device according to claim 3, wherein the thickness of the gate insulating film under the gate electrode in the isolation region is increased except for the charge transfer path.