JPH01113996A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To read the data of a data width exceeding an output data width at high speed by fetching the data times as many as the number of the blocks of one output data width from a memory cell array address designated by a call means and outputting this data to an output part at high speed sequentially for every block by a data output means. CONSTITUTION:The data of 24 bits according to one address designation is realized by the data outputs of the three times D0-D7 based on the control signals S1-S3 of a counter 9. Therefore, after the output of the data of a sense amplifier 6x1, the data of a sense amplifier 6x3 is outputted at after 2T in time and since the time 2T is the two cycles of a clock phi, which is extremely short, the data of 24 bits can be outputted at high speed in the mask ROM of the data output of 8 bits. Thereby, according to the one address designation, the data of the data width obtained by integrating the output data width of an output part with the number of the blocks can be read at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to improving the read speed thereof.

(Prior Art) FIG. 6 is an explanatory diagram of the configuration of a conventional mask ROM used as, for example, a kanji ROM. In the figure, 1 is an address buffer, 2 is a row decoder, 3 is a column decoder, and 4
is a memory cell array; 5 is a bit line selection circuit that selects a predetermined bit line according to the output signal of the column decoder 3;
Is 6 a sense amplifier and 7 an output buffer? It is. The output buffer 77 is usually composed of 8 or 16 pieces, and in the figure, the output buffer 77 is 7° to 7.0°. Eight examples are shown. In accordance with the number of output buffers 7, eight sense amplifiers 6 and eight bit line selection circuits 5 are provided each from 6 to 6.5 o to 5□, and the memory area of the memory cell array 4 is divided into eight from 4 degrees to 4□. Ru. Also, address bar.

There are n buffers 1 from 10 to 1 (.-1), and n
+3 has a memory configuration of 2×8=2 bits. Note that D0 to D7 are data outputs.

FIG. 7 is a circuit configuration diagram showing a sense amplifier 6x and a bit line selection circuit 5X connected to one data buffer 77x (X=O to 7). As shown in the figure, a transistor Q has one electrode connected to each bit line of the memory cell array 4x and the other electrode commonly connected to the sense amplifier 6x.
. -Ql-1 are provided, each transistor Q -Q,
, each output signal line 3° to 31 of the column decoder 3 is connected to the gate of the column decoder 3.
1-1 is connected.

In such a configuration, when reading, a CPU (not shown)
When an address signal is generated by, for example, the address buffer 1, the address signal is inputted to the row decoder 21 as a row address RA and to the column decoder 3 as a column address CA. Then, one row (word line) of the memory cell array 4 is selected by the row decoder 2 based on the row address RA.

Thereafter, all the data in the memory cells of the selected row are transferred to the transistors of each bit line selection circuit 5x via all bit lines.
, is transmitted to the drain of QO-Qm-1.

On the other hand, the column decoder 3 activates one of the output signal lines 3 to 311-1 based on the column address CA, and the transistor Q is activated in each bit line selection circuit 5x. -Qa
-1 is conductive. As a result, each sense amplifier 6X receives addresses RA and C from each memory cell array 4X.
A The data of the designated memory cell array 4 is input,
The sense amplifier 6X detects and amplifies the data, and the data can be outputted via the output buffer 7X.

In other words, 8 bits of data D can be generated by one address specification.
. -07 can be obtained in parallel.

Let us consider a case where the above mask ROM is used as a Kanji ROM storing Kanji font data. The mainstream of recent Kanji fonts is the 24x24 dot structure. Therefore, 24 bits of data for one row are divided into 24 bits per row.
The most appropriate method is to generate a single kanji character by outputting it twice.

Therefore, when using a mask ROM with 8-bit data output, this mask ROM is
For example, as shown in Figure 8, for the character "kan", the kanji ROMI contains kanji data D1, kanji R
Kanji data D2 is stored in OM2, Kanji data D3 is stored in Kanji ROM3, and font data on the same line is stored at the same address (A
o~A4. (upper address omitted). With this configuration, kanji font data of 24 bits per line can be output from a kanji ROM with 8-bit data output.
This is done by using three and outputting 24-bit data in parallel with one address specification. In addition, this kanji ROM
For each of the Kanji ROMs 3, conventionally, 6 IM (mega) bit configurations were mainly used.

[Problem that the invention seeks to solve]

By the way, the number of characters that should be stored in the kanji ROM is: JIS No. 1 kanji characters: 524 characters JIS 1st level characters: 2,965 characters JIS 2nd level characters:
3,388 characters, including the number of characters in the second chapter, 0.
There are 877 characters, and the required memory capacity is: Kanji font 16 x 16 dots 176 Mbits 24
x24 n 3.96 Mbit 36x 36,
n8. ．． 91 Mbits are required, and in order to construct a Kanji ROM including JIS level 2 with the recently mainstream 24x24 dot structure Kanji font, a memory capacity of 4Mbits or more is required.

Therefore, it is necessary to use three Kanji ROMs having a capacity of 2M bits (4M pits), which is larger than 1M pits, in parallel as shown in FIG. 8 using the same method as in the conventional method. However, when using Kanji ROM in this way, the required memory capacity is 3.9 for 24x24 font Kanji data.
Kanji ROM with sufficient capacity of 6M bits and 4M bits,
This resulted in a configuration of 6 (2 x 3) M pits and 12 (4 x 3) M bits, which resulted in a large capacity and a problem of poor memory efficiency.

In order to solve this problem, 4M of 8-bit data output
Memory efficiency can be improved by using one bit-configured mask ROM as the Kanji ROM and storing all seven Kanji character data in one Kanji ROM.

However, a Kanji ROM with one 8-bit data output
In this case, three memory accesses are required to output data for one line of kanji. For this reason, 1 of the mask ROM
Since the access time for each kanji ROM is about 200 to 250 ns, it takes 600 to 750 ns to access it three times, which is about three times the conventional rate. Especially when accessing such a kanji ROM with a high-speed microprocessor, However, there was a problem in that the processing time required to output kanji characters was longer than necessary.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor memory device that can be accessed at high speed when data is read out in multiple steps.

[Means for solving problems]

The semiconductor memory device according to the present invention includes a data calling means for taking in a plurality of bits of data addressed from a memory cell array in block units, and a data calling means for taking in the plurality of bits of data addressed by the data calling means at predetermined time intervals for each block. and data output means for outputting data to the same output section.

[Effect]

The data output means in this invention outputs multiple bits of data fetched from the memory cell array addressed by the data calling means to the same output section at predetermined time intervals for each block, so that one address designation is enough. It is possible to read data with a data width equal to the output data width of the output section plus the number of blocks by l1iW.

(Embodiment) FIG. 1 is an explanatory diagram of the configuration of a mask ROM which is an embodiment of the present invention. In the same figure, since 1 to 4 are the same as the conventional one, their explanation will be omitted. Unlike conventional bit line selection circuits 5, three bit line selection circuits 5x are provided for each memory cell array 4x (x=O to 1) according to the output of the column decoder 3.
Three bits are selected by providing 1 to 5x3. Correspondingly, the sense amplifier 6 is also configured to hold 6x1 to 3 data for each memory cell array 4x.
There are three, 6x3. In this way, the bit line selection circuit 5 and the sense amplifier 6 have a three-block configuration.

Also, is there a transmission buffer between the sense amplifier 6 and the output buffer 77? 8 are provided, each sense amplifier 6x
One each of 8x1 to 8x3 is provided corresponding to 1 to 6x3. This transmission buffer 8 is also 8x1,8
It has a three-block configuration of x2 and 8x3, and is controlled by applying control signals 81 to S3 inputted from the counter 9 to each of the three blocks, so that only one transmission buffer 8x of the three blocks becomes conductive.

Is counter 9 a human power buff? 10 according to the clock φ, and three t11 control signals S are activated at cycle intervals of the clock φ.
A trigger is generated for each of steps 1 to S3. The input buffer 10 receives an external signal and sends 0 to the counter 9.

FIG. 2 is a detailed circuit diagram showing the sense amplifier 6, transmission buffer 8, and bit line selection circuit 5x connected to one output buffer 7x. As shown in the figure, the bit line selection circuit 5 is
One column decoder output line3. For (V=0 to (I-1)), a three-block configuration 5x1 to 5x3 is connected to the gates of three transistors Q, 1 to Q, and 3.

Correspondingly, as shown in FIG.
6x1 corresponding to each bit line selection circuit 5x1 to 5x3
It is provided in ~6x3 and 3 block configuration.

In addition, three transmission buffers 8x1 to 83x are provided between the sense amplifiers 6x1 to 683 and the output buffer 7x, respectively.
It is set up in a block configuration. That is, a set of bit line selection circuit 5, sense amplifier 6X, and transmission buffer 8 (56XXi'Xl).

8), (5x2, 6x2, 8x2), (5x3.6x3
Blocks 81 to B3 having a size of 8.times.8.times.3) are provided for one output buffer 7.

FIG. 3 is a circuit diagram showing details of the counter 9.

As shown in the figure, flip 70 knobs FF1. FF2 is connected in series. These 7-lip 70-tube FFI and FF2 both have a J input and a power supply ■. It is pulled up to C. flip 7
The toggle input of the 0-tube FF1 receives an inverted clock signal φ via the inverter G1 of the clock φ input from the input buffer 10, and the Q output of the flip 70-tube FFI serves as the toggle input of the 7-lip 70-tube FF2. .

The control signals 81 to S3 are the output signals of the Nant gates NGI to NG3. Gate NG2 is an inverted signal cup.

The inverted Q output of the flip-flop FF1 via the inverter G2 and the Q output of the flip-flop FF2 are powered by three people, and the Nant gate NG3 outputs the inverted 0 clock signal φ,
It is powered by three people: the Q output a of the flip 70-tube FF1 and the inverted Q output δ of the flip 70-tube FF2 via the inverter G3.

In addition, an OR gate OG is provided with the inverted clock cup 1 inverted Q output a and Q output as human signals, and its output signal r
is flip 70 tube FF1. It is applied to the reset human power R of FF2.

FIG. 4 is a waveform diagram showing the operation of the counter 9. The operation will be explained below with reference to the same figure.

Note that time t. Former 7 lip flop FF1゜FF2
are both reset, and their Q output is at “L” level,
When clock φ is not activated, clock φ is “H”
Since the inverted clock signal is at the "high" level, the output signals 81 to s3 of the Nantes gates NG1 to NG3, which receive the inverted clock signal as input, are all at the "H" level.

Time t. The inverted clock cup, which was at “L” level, becomes “H”.
The level rises, and using this as a trigger, the Q output a of the Noritub 70 output F1 is inverted and becomes the "HII level," and at the same time, using this Q output a as a trigger, the Q output a of the flip-flop FF2 is inverted.
The Q output of is inverted and becomes H" level. As a result, the inverted clock φ, Q output a, and Q output b (all at "H" level)
Only the output signal S1 of the Nandt gate NGI which receives the input signal falls to the "yes" level. (82 and 83 are at H level).Then, at time t1, the inverted clock low falls to an L level, and the signal S1 returns to an H level.

At time t2, when the inverted clock falls again, the Q output a of the flip 70-tube FFI becomes °゛L'.

The level falls (the Q output of flip 70 knob FF2 maintains the "H" level). As a result, only the output signal S2 of the Nant gate NG2 whose input signals are inverted 0, small 9 inverted Q output, and Q output b (all at "HII level") is "L".
fall to the level ($1゜83 is 1]” level) and,
At time t3, the inverted clock falls and the signal S2 becomes HII.
Return to level.

At time t4, when the inverted clock φ rises again, the Q output a of the flip 70 block FFI rises to the "HII" level. At the same time, using this Q output a as a trigger, the flip 70
The Q output of Tsubu FF2 falls to the L11 level. As a result, a Nantes gate NG3 whose input signals are the inverted clock small and the Q output a1 and the inverted Q output 5 (all at "T1" level)
Only the output signal S3 falls to “L” level (82.33
is H'.

level).

Then, at time t5, the inverted clock low rises to the ``V'' level, and the signal S3 returns to the ``H'' level.

At this time, the output signal r of the OR gate OG, which uses the inverted clock signal 1 inverted Q output a and Q output b (all at "L'° level") as input signals, falls to the LIT level, and as a result, the output signal r of the OR gate OG falls to the LIT level. A reset is applied, and both the Q output a and the Q output are initialized to the "off" level.

In this way, when the clock φ starts, the signal S1 generates a falling trigger, and 82 .
83 sequentially generates falling triggers.

FIG. 5 is a circuit diagram showing details of the transmission buffer 8x. In the figure, the transmission buffer 8x1 includes an inverter G4 composed of a pMO8 transistor 11 and an nMO8 transistor 12, and a pMOS
Transistors 13, 14, nMOS transistor 15.
It is configured with a buffer BF composed of 16 buffers. The buffer 7BF is connected so that the output of the sense amplifier 6x is applied to the gate of the transistor 14, 15, the control signal $1 is applied to the gate of the transistor 13, and the inverted control signal S1 via the inverter G4 is applied to the gate of the transistor 16. When the control signal S1 reaches the 111'' level, the data held in the sense amplifier 6x1 is output.

In addition, ]・Transmission buffer 8 8 is also a transmission×2・×3 buffer? It has the same configuration as 8x1.

In such a configuration, an output signal from the address buffer 1 is received by a CPU (not shown), etc., and a row of the memory cell array 4 is selected by the row decoder 2, so that the data of all memory cells in the selected row cover all pit lines. Transistors Q of each bit line selection circuit 5x1 to 5x, . . .
・Q-, Qx3 01 (nl
)1 02°...Q-, Q,... transmitted to the drain of Q- (n 1)2 03 (n 1)3.

On the other hand, the column decoder 3 sets the column address CAk: 1 with M.
Any one of the output signal lines 3 to 31-1 is activated, and in each bit line selection circuit 5x1 to 5x3, one of the transistors Q
)1 Either transistor Q -Q, transistor 0
2 (n-1)2 A total of three transistors in any one of the stars Q03 to Q(n-1)3 become conductive. As a result, each sense amplifier 6x1
~6x3 has address RA from memory cell array 4x,
Data of a memory cell designated by CA is input, sensed, amplified and held by the sense amplifiers 6x1 to 6x3. Then, the counter 9 is activated by sending a clock φ from the input buffer 10.

Then, the counter 9 generates control signals 81 to S3 as shown in FIG.
The data of the sense amplifiers 66x11x2 and 6x3 are sent sequentially at intervals, and the data output Dx can be obtained three times.

That is, one address designation causes 24-bit data to be output three times based on the control signals 81 to $3 of the counter 9. This is realized by ~D7. Therefore, after the data output from the sense amplifier 6x1, the data output from the sense amplifier 6x3 can be obtained after 2 hours, and since the time 2 times is extremely short as 2 periods of the clock φ, in a mask ROM with 8-bit data output, High-speed data output of bit data has been realized.

Therefore, this mask ROM can be applied to a kanji ROM of a 24×24 dot kanji font as follows. For example, the kanji data D1 stored in the kanji ROMI in the kanji data "kan" shown in FIG.
1 stores the kanji data in the memory array 4 so that the block B2 takes in the kanji data D2 stored in the kanji ROM 2, and the block B3 takes in the kanji data D3 stored in the kanji ROM 3. When stored in this way, one 4M pit mask ROM with 8-bit data output is used as a Kanji ROM, thereby achieving high memory efficiency and high-speed reading of Kanji data. As a result, high-speed CP
It can also be fully compatible with U.

In addition, in this embodiment, an example of a mask ROM is shown that can obtain 24-bit data output by outputting 8-bit data three times at high speed with one address specification, but one data output The number of pits and the number of pits can be increased or decreased as appropriate. In this case, the bit line selection circuit 5. Sense amplifier 6, output buffer 7. Transmission buffer8. It is necessary to change the configuration of the counter 9 appropriately.

For example, if the number of data output bits remains 8 and the number of data outputs is set to p, the bit line selection circuit 5 conducts 0 transistors on the signal output line of one column decoder 3.
m, the number of blocks of the bit line selection circuit 5, sense amplifier 6, and transmission buffer 8 is p,
This can be realized by appropriately increasing or decreasing the number of flip 70-tube FFs in J- in the counter 9 as needed, and providing control signals of 81 to Sp and p types.

Further, in the counter 9, another external signal SO is flipped to J- as shown in FIG.

By using it as the reset input of FF2, this external signal SO
It is also possible to reset the counter 9 by.

In addition, the input external signal of the input buffer 10 that outputs the clock φ is input to the mask ROM's output enable terminal.
E, and by controlling the data output from the OF large input,
It is necessary to prepare a separate external human input signal pin for the generation of L1 tsukuφ! G is gone. Furthermore, by making the external signal SO a signal that generates an "L" signal for a predetermined time in response to the falling edge of the chip enable input GE, the mask ROM C
It is possible to set the counter 9 to be reset upon activation by a large E input.

In addition, although the mask ROM was described in this embodiment,
Dynamic RAM, static RAM, EPROM
By applying the present invention to other semiconductor memory devices such as 6., high-speed reading can be realized.

Furthermore, it can of course be used in other application fields other than Kanji font data processing.

〔Effect of the invention〕

As explained above, according to the present invention, the memory address specified by the data calling means [from the recell array
Data with a data width that exceeds the output data width can be read out at high speed because the data is taken in as many blocks as the output data width, and the data output means sequentially outputs this data block by block to the output section at high speed. can.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram of a mask ROM which is an embodiment of the present invention, FIG. 2 is a circuit configuration diagram showing partial details thereof, and FIG.
The figure is a circuit diagram showing the details of the counter shown in Figure 1, and the circuit diagram shown in Figure 4.
FIG. 5 is a waveform diagram showing the operation of the counter, FIG. 5 is a circuit configuration diagram showing gT details of the transmission buffer in FIG. 1, FIG. 6 is a configuration explanatory diagram showing the conventional mask 1 < OM,
FIG. 7 is a circuit configuration diagram showing partial details thereof, and FIG. 8 is an explanatory diagram showing an example of storing Kanji font data. In the figure, 3 is a column decoder, 4 is a 7-ray memory cell,
5 is a bit line selection circuit, 6 is a sense amplifier, 7 is an output buffer 7. 8 is a transmission buffer 1. 9 is a counter. In addition, the number -m in each figure indicates the same or corresponding part. Agent Person Right Masu 1st Figure Do Dt 5-1--Loin) Mika AL Oz Times Kito 6-----Ku Suanfu 0 Q-----) Laso Entering Mion 1 Tsunogutsufu Y No. Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 01

Claims (5)

[Claims] (1) A semiconductor memory device that reads data from a memory cell array through an output section, the device comprising: data calling means for taking in a plurality of bits of data addressed from the memory cell array in block units; and data output means for outputting a plurality of bits of data to the same output section at predetermined time intervals for each block. (2) The data calling means includes bit line selection means for simultaneously selecting a plurality of bit lines based on the output of the decoder, and a plurality of bit line selection means for holding data on each bit line selected by the bit line selection means in units of blocks. The data output means includes a counter that sequentially generates a trigger for each block at the predetermined time interval, and a counter that is provided between each sense amplifier and each output section for each block and is electrically connected when the trigger of the counter is generated. A semiconductor memory device according to claim 1, comprising a transmission buffer. (3) A plurality of the output sections each have a 1-bit output, and the data calling means and the data output means are provided corresponding to each of the output sections.
The semiconductor storage device described in 1. (4) The semiconductor memory device according to claim 2 or 3, wherein the reference clock for determining the predetermined time interval in the counter is based on an output enable signal. (5) The semiconductor memory device according to any one of claims 2 to 4, wherein the counter is reset based on a chip enable signal.