JPH01113834A - Data processor - Google Patents

Abstract

PURPOSE:To optionally set the priority order of external interruptions and also to freely set the number of pieces of external interruptions to some extent by providing a mask circuit independently of an interruption control module to prevent the input of the external interruption signal to an interruption control circuit. CONSTITUTION:A mask circuit MSK is set outside an interruption controller module ICM. Then the priority order can be set for each interruption signal as desired by a user by connecting optionally a signal line led from a peripheral module MDL for the internal interruption request signal iNT and a signal line led from the circuit MSK for the external interruption request signal EXI to interruption request terminals IRQ0-IRQ15 of the module ICM. Thus it is possible to avoid such a conventional case where the external interruption signal always have a higher priority order than the internal interruption signal. Furthermore the number of circuits MSK can be set freely within a range of bit number (4 bits) of a mask register M-REG.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to data processing technology and technology that is particularly effective when applied to interrupt control circuits of microcomputers, such as ASIC (Application 5PE).
cific integrated circuit
t) It relates to a technique effective for use in configuring an interrupt control circuit of a compatible microcomputer.

[Prior art] In recent years, in the field of microcomputers, ASIC
Application-specific LSIs called "LSIs" are becoming available. ASIC-compatible microcomputers are
Peripheral devices such as CPU (central processing unit), timer, A/D converter, DMA controller, and ROM,
A device that allows a user to configure a microcomputer by preparing a number of memory modules, such as RAM, with different functions, and selecting from among these modules the module with the function that meets his or her needs. It is. This makes it possible to shorten the development period for microcomputers.

In conventional standard cell type microcomputers, - For boat fishing, the interrupt controller is handled as an integral part of the CPU module. When integrating the interrupt controller with the CPU module in this way, it is not reasonable to prepare multiple CPU modules that differ only in the interrupt controller part, so it is necessary to assume the maximum number of interrupt request signals and A matching interrupt controller will be built in. However, for users who desire a simple system with a small number of peripheral modules, this would result in a large number of unnecessary interrupt request terminals and functions, making it impossible to reduce the chip size sufficiently.

Therefore, a method can be considered in which the interrupt controller is separated from the CPU and made into a separate module. For example, regarding ASIC, published in July 1986, Industrial Research Institute Vol. 1.2
5r Electronic Materials jp, 22-p, 128.

[Problems to be Solved by the Invention] However, even when only the interrupt controller is made into a module, the conventional general interrupt controller method in which external interrupts are masked within the interrupt controller does not limit the number of external interrupts. and priorities are fixed. Therefore, in order to set the number and priority of external interrupts as desired by the user, it is necessary to modify each module.

On the other hand, as a method that allows the user to arbitrarily set the number and priority of external interrupts, there is a mask register with the same number of bits as the number of interrupt request pins of the interrupt controller, and input of external interrupts is blocked according to the contents of this register. It is also conceivable to provide a mask circuit to do this. However, in this case, the area occupied by the mask register and the mask circuit increases, making it difficult to reduce the chip size.

This invention was made against the above background, and its purpose is to arbitrarily set the priority of external interrupts and to control external interrupts without changing the design of the module or increasing the area occupied by the module. It is an object of the present invention to provide an interrupt controller module suitable for ASIC LSI in which the number of interrupt controllers can be set freely to some extent.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] Representative inventions disclosed in Suito are summarized as follows.

In other words, the external interrupt mask circuit is placed outside the interrupt controller module, and the mask circuit is incorporated into the input buffer of the external interrupt input terminal to form a standard cell, and the interrupt mask circuit is controlled by a register within the interrupt controller module. It is something that you should do.

[Operation] According to the above means, since the mask circuit is located outside the interrupt controller, the internal interrupt signal line from the internal module and the external interrupt signal line via the mask circuit are arranged in priority order of the interrupt controller module. By arbitrarily connecting to the interrupt request terminal, the priority order of external interrupt signals can be freely set, and the number of external interrupt signals can also be freely set within the range of the number of bits of the masking register.

[Embodiment] FIG. 1 shows the -actual flow side of an interrupt control circuit according to the present invention.

In the figure, the reference numeral ICM indicates an interrupt controller module, and this interrupt controller module ICM, although not particularly limited, handles interrupt reception through a section IRC and 16 interrupt request terminals IR arranged in priority order.
It has Q, -IRQ. In this example, terminal I
RQo has the highest priority, and terminal IRQ has the lowest priority. Also, interrupt controller module I
For example, a 4-bit mask register M is included in the CM.
-REG is provided. This mask register M-R
In the EG, data can be arbitrarily set for each bit by a command from the CPU via the internal bus BUS.

And this interrupt controller module ECM is 1
Peripheral module MDL that notifies the CPU of the occurrence of an interrupt when interrupt signals are simultaneously input to the interrupt request terminals IRQ, ~IRQ, etc., but also determines the priority order and issues one interrupt request, although this is not particularly limited. A permission signal ACK is sent to each device according to the priority order.

In this embodiment, an external interrupt signal masking circuit MSK is provided outside one interrupt controller module ICM. Four mask circuits MSK are provided corresponding to the number of bits of the mask register M-REG,
Each mask circuit MSK has a synchronization circuit SYN connected to an external interrupt terminal (ponding pad) INT of the chip, as shown representatively for one of them MSKo.
and control signal EXIE from mask register M-REG.
NAND gate GL which is opened and closed by.

NAND control signal EXIE in synchronization with clock CKI
A clocked inverter INV supplies the gate G1.

This causes the mask circuit MSK to control the mask register M
When a low level interrupt signal is input to the external interrupt terminal INT while the corresponding bit of -REG is set to "1", an interrupt request signal EXI is supplied to the 1 interrupt controller module ICM. On the other hand, if the corresponding bit of the mask register M-REG is "0", no interrupt request signal EXI is sent to the interrupt controller module ICM even if the external interrupt terminal INT is set to low level. by this,
For example, even if an external interrupt request signal with a higher priority comes in during a certain interrupt process, by setting II O71 in the corresponding micro register bit in advance, it is possible to prevent the interrupt from occurring. .

In this way, in the above embodiment, since the mask circuit MSK is provided outside the interrupt controller module ICM, the signal line for the internal interrupt request signal iNT from the peripheral module MDL and the external interrupt request from the mask circuit MSK are Connect the signal line of signal EX■ to interrupt request terminals IRQo to IRQ1 of interrupt controller module 1CM.
5, by arbitrarily connecting them, it is possible to give priority to each side-in signal as desired by the user. Therefore, the external interrupt signal does not always have a higher priority than the internal interrupt signal, unlike in the conventional case.

In addition, in the above embodiment, since the mask circuit MSK is located outside the module, the number of bits of the mask register M-REG (
The number of mask circuits MSK can be freely set within the range of 4 bits). Therefore, for example, if the external interrupt terminal is 2
If you want to design a microcomputer that requires only two mask circuits, you only need to prepare two mask circuits MSK. Thereby, the number of mask circuits can be minimized and the chip size can be reduced accordingly.

In addition, in this case, the mask register M − in the module
Regarding RE'G, 2 bits are wasted, but 16 bits are wasted.
Compared to the case where a bit mask register is prepared, there is much less waste, and the area occupied by the interrupt controller module can be significantly reduced compared to the conventional method.

Moreover, the mask circuit MSN of the embodiment has a synchronization circuit SYN similar to the input/output buffer connected to other external terminals.
By registering them as standard cells along with the control gate G□ and inverter INV, and selecting the number of cells as needed and placing them near the chip terminals, it can be done easily and in a short period of time without major changes. An ASIC microcomputer with desired functionality can be designed.

Experience has shown that it is often sufficient to have four external interrupt request terminals. However, if it is anticipated that there will be users who request five or more external interrupt request terminals, an interrupt controller module having, for example, an 8-bit mask register may be prepared. Even if you do that,
The number of interrupt controller modules that need to be prepared is only a few, which is more reasonable than changing the module only according to the number of external interrupt signals or preparing all interrupt controllers with different external interrupt signals as modules in advance. It is true.

FIG. 2 shows an example of the configuration of a standard cell type microcomputer using the interrupt controller module of the above embodiment.

In the same figure, the symbol CPU is a microprocessor as a centralized control means, the symbol TMR is a timer, SCI is a serial communication interface, BSC is a bus controller, M
ACP is a selection circuit that decodes an internal address signal and generates a selection signal generation signal C8 for a peripheral circuit;
What is indicated by CM is the interrupt controller of the above embodiment.

These circuits are modularized into multiple circuits with different functions and registered as standard cells, and a desired microcomputer can be configured by selecting and combining those with the desired functions from among them. be done.

The selected modules are arranged on the chip in the most space-efficient manner and are connected to each other by a standard bus SEP, called the silicon backplate.

It should be noted that IOB 7 indicates input/output buffer circuits for data input/output signals and various external control signals provided corresponding to each of the modules. These buffer circuit works ○B1 to ○B.

Among them, the input buffer IOB provided corresponding to the interrupt controller module ICM has the mask circuit MSK (synchronization circuit SYN, control gate G1, and inverter INV) shown in FIG. 1 registered in advance as one cell. It is constructed by arranging the necessary number of things.

Similarly, the other input/output buffer 7 circuits are constructed by arranging a desired number of buffer cells from pre-registered buffer cells.

Note that the modules shown in FIG. 2 are just examples, and in addition to the above, there are also memories (ROM, RAM, etc.).

All peripheral circuits of a microcomputer, such as EPROM, DMA controller, memory management unit, and A/D converter, can be modularized.

As explained above, in the above embodiment, the external interrupt mask circuit is placed outside the interrupt controller module, and the mask circuit is incorporated into the input buffer of the external interrupt input terminal to form a standard cell, and the control of the interrupt mask circuit is Since this is done by a register in the interrupt controller module, the mask circuit is outside the interrupt controller, so the internal interrupt signal line from the internal module and the external interrupt signal line via the mask circuit are prioritized by the interrupt controller module. By arbitrarily connecting to the interrupt request terminals lined up in order, you can freely set the priority of external interrupt signals and also freely set the number of external interrupt signals within the range of the number of bits of the mask register. There is an effect that it can be done.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it is possible to make various changes without departing from the gist of the invention. Not even. For example, in the above embodiment, the interrupt reception unit IRC of the interrupt controller module
Although it has been explained that 16 interrupt request terminals are provided, the number of interrupt request terminals is not limited to 16, and may be any number such as 24 or 32. Also, in the embodiment, it is explained that the interrupt request terminals are arranged in priority order, but it is only necessary that the priority order is clear.
They do not necessarily have to be physically arranged in priority order.

In the above description, the invention made by the present inventor was mainly applied to a microcomputer compatible with AS engineering, which is the background field of application, but the present invention is not limited thereto. and various controller LIS and other control processing functions,
It can be used for data processing LSIs that are desired to be modularized.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, in ASIC-compatible microcomputers, etc., the priority order of external interrupts can be arbitrarily set and the number of external interrupts can be freely set to a certain extent without changing the design of the module or increasing the area occupied by the module.
Furthermore, the chip size of the microcomputer can be minimized.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of an interrupt control circuit according to the present invention, and FIG. 2 is an example of a standard cell type microcomputer using the interrupt controller module of the embodiment. ICM・・・Interrupt controller module, M-R
EG...Mask register, MSK...Mask circuit, MDL...Peripheral module, SYN...Synchronization circuit, CPU...Microprocessor, TMR
...Timer, SCI...Serial communication interface, BSC...Bus controller, MACP...Selection signal circuit, l0B1-I
OB, ... input/output buffer.

Claims (1)

[Claims] 1. A plurality of centralized control means having mutually different functions, a plurality of peripheral circuits having mutually different functions, and an interrupt control circuit for processing interrupt requests from the peripheral circuits or the outside to the microprocessor, respectively. In a microcomputer that is configured by selecting a desired module from among a plurality of modules prepared as modules, a mask circuit that prevents input of an external interrupt signal to the interrupt control circuit performs interrupt control. A data processing device characterized by being provided separately from a module. 2. Claim 1, characterized in that a mask register for forming a control signal for permitting or blocking input of an external interrupt signal to the mask circuit is provided in the interrupt control module. The data processing device described in Section 1. 3. The data processing device according to claim 1 or 2, wherein the number of bits of the mask register is less than half the number of interrupt request receiving terminals provided in the interrupt control module. 4. The above-mentioned mask circuit is registered as an input buffer cell equivalent to an input/output buffer connected to an external terminal other than an interrupt input terminal together with a synchronization circuit and a control gate. The data processing device according to item 1, item 2, or item 3.