JPH01112833A - Error rate measuring instrument - Google Patents
Error rate measuring instrumentInfo
- Publication number
- JPH01112833A JPH01112833A JP26983687A JP26983687A JPH01112833A JP H01112833 A JPH01112833 A JP H01112833A JP 26983687 A JP26983687 A JP 26983687A JP 26983687 A JP26983687 A JP 26983687A JP H01112833 A JPH01112833 A JP H01112833A
- Authority
- JP
- Japan
- Prior art keywords
- error
- circuit
- counting
- errors
- error rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 4
- 238000005259 measurement Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
- 238000001514 detection method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はディジタル伝送装置の誤り率計測器に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an error rate measuring device for a digital transmission device.
従来の誤り率計測器の一例を第2図に示し説明する。 An example of a conventional error rate measuring device is shown in FIG. 2 and will be described.
図において、11は誤り信号001を計数する誤り計数
回路、12はこの誤り計数回路11に初期設定信号00
2を供給する計数時間設定回路、13は誤り計数回路1
1の出力を入力とする誤り率判定回路である。In the figure, 11 is an error counting circuit that counts error signals 001, and 12 is an initial setting signal 00 to this error counting circuit 11.
2 is a counting time setting circuit that supplies 1, and 13 is an error counting circuit 1.
This is an error rate determination circuit that receives an output of 1 as an input.
そして、計数時間設定回路12によって区切られる各計
数時間内に発生した誤りを誤り計数回路11で計数し、
その個々の誤り数003から誤り率判定回路13で直接
誤り率判定結果004を得ていた0
〔発明が解決しようとする問題点〕
上述した従来の誤り率計測器は、計測しようとする誤り
率が低い場合、すなわち、設定された計数時間が長い場
合には、計数した誤り数から誤り率を判定した後は次の
誤多事判定まで途中の誤)率を判定することが不可能で
あるため、実際の誤多事が短時間で変化すると変化した
誤多事判定の遅れが大きいという問題点があった。Then, the error counting circuit 11 counts errors occurring within each counting time divided by the counting time setting circuit 12,
The error rate determination circuit 13 directly obtains the error rate determination result 004 from the number of individual errors 003. [Problems to be solved by the invention] is low, that is, when the set counting time is long, it is impossible to determine the error rate after determining the error rate from the number of counted errors until the next error/event determination. Therefore, there is a problem in that when an actual error event changes in a short time, there is a large delay in determining the changed error event.
本発明の誤多事計測器は、ディジタル伝送システムの誤
多事計測において、誤り信号を計数する誤り計数回路と
、この誤り計数回路に初期設定信号を供給する計数時間
設定回路と、この計数時間設定回路から記憶命令を受け
上記誤り計数回路からの誤り数を記憶する誤り記憶回路
と、この誤〕記憶回路の出力を加算する加算回路と、こ
の加算回路によって得られた加算結果に基いて判定結果
を得る誤多事判定回路とを備え、一定間隔に区切られ九
各計数時間内に発生した誤)を計数してそれらを順番に
記憶しておき、誤りの計数終了毎に新しいものから順に
一定個数の誤多数を加算した結果から誤多事を判定する
ことで、誤多事が短時間に変化してもその変化した誤多
事をよシ早く判定できるようにしたものである。The error measuring device of the present invention is used to measure errors in a digital transmission system, and includes an error counting circuit that counts error signals, a counting time setting circuit that supplies an initial setting signal to this error counting circuit, and a counting time setting circuit that supplies an initial setting signal to this error counting circuit. An error storage circuit that receives a storage command from the setting circuit and stores the number of errors from the error counting circuit; an addition circuit that adds the outputs of the error storage circuit; and a judgment based on the addition result obtained by this addition circuit. It is equipped with an error/occurrence judgment circuit that obtains results, counts errors that occur within nine counting times divided at regular intervals, stores them in order, and stores them in order from the newest one every time counting of errors is completed. By determining an erroneous event based on the result of adding up a fixed number of erroneous errors, even if the erroneous event changes in a short period of time, the changed erroneous event can be determined more quickly.
〔作用〕
本発明においては、計測しようとする誤多事が低い場合
、従来乙の計数時間毎の誤多数を新しいものから順にn
個記憶しておき、誤り計数終了毎にそれらを加算した結
果から誤多事を判定する。[Operation] In the present invention, when the number of errors to be measured is low, the number of errors per counting time of conventional B is calculated in order from the newest one to n.
Errors are determined from the result of adding them each time the error count is completed.
以下、図面に基づき本発明の実施例を詳細に説明する。 Hereinafter, embodiments of the present invention will be described in detail based on the drawings.
第1図は本発明による誤り本計測器の一実施例を示すブ
ロック図である。FIG. 1 is a block diagram showing an embodiment of an error measuring device according to the present invention.
図において、1は誤り信号01を計数する誤り計数回路
、2はこの誤り計数回路1に初期設定信号02を供給す
る計数時間設定回路、3はこの計数時間設定回路2から
記憶命令03を受け誤り計数回路1からの誤多数04を
記憶する誤り記憶回路、4はこの誤り記憶回路3の出力
を加算する加算回路、5はこの加算回路4によって得ら
れた加算結果に基いて判定結果を得る誤多事判定回路で
ある。なお、05は新しいものから順にn個の誤多数を
示し、06はn個の誤多数の和、07は誤多事判定結果
を示す。In the figure, 1 is an error counting circuit that counts error signals 01, 2 is a counting time setting circuit that supplies an initial setting signal 02 to this error counting circuit 1, and 3 is an error counter that receives a storage command 03 from this counting time setting circuit 2. An error storage circuit that stores the error number 04 from the counting circuit 1; 4 an adder circuit that adds the output of the error storage circuit 3; 5 an error storage circuit that obtains a judgment result based on the addition result obtained by the adder circuit 4; This is an event judgment circuit. Note that 05 indicates n false counts in descending order, 06 indicates the sum of n false counts, and 07 indicates the false event determination result.
そして、一定間隔に区切られた各計数時間内に発生した
誤りを計数してそれらを順番に記憶しておき、誤りの計
数終了毎に新しいものから順に一定個数の誤多数を加算
した結果から誤多事を判定することで、誤多事が短時間
に変化してもその変化した誤9率をよシ早く判定できる
ように構成されている。Then, the errors that occur within each counting time divided at regular intervals are counted and stored in order, and each time the counting of errors is completed, a fixed number of errors are added in order from the newest one. By determining an error, even if the error occurs in a short period of time, the changed error rate can be determined quickly.
つぎにこの第1図に示す実施例の動作を説明する。Next, the operation of the embodiment shown in FIG. 1 will be explained.
まず、誤り計数開始時に計数時間設定回路2からの初期
設定信号02でゼロ(零)に設定された誤り計数回路1
は、誤り信号01によシ従来の1/、の各計数時間内に
発生した誤りを計数し、計数終了後記憶命令03によシ
誤多数04は誤り記憶回路3に記憶される。さらに、各
計数時間毎にこの操作を繰シ返し誤り記憶回路3は常に
新しいものから順にn個の誤多数05を記憶しておき、
各計数時間終了時に記憶されている誤多数05が変更さ
れる毎にこれらを加算回路4で加算する。First, the error counting circuit 1 is set to zero by the initial setting signal 02 from the counting time setting circuit 2 when error counting starts.
The error signal 01 counts the errors that occur within each counting period of 1/, and after the counting is completed, the error count 04 is stored in the error storage circuit 3 according to the storage command 03. Furthermore, this operation is repeated for each counting time, and the error storage circuit 3 always stores the n number of errors 05 in order from the newest one.
Every time the erroneous number 05 stored at the end of each counting time is changed, these are added by an adding circuit 4.
つぎに、その加算計果06 (n個の誤多数の和)から
誤多事判定回路5にょシ誤多率判定結果07を得る。Next, from the addition result 06 (sum of n false counts), the error rate determination circuit 5 obtains the error rate determination result 07.
以上説明したように1本発明は、ディジタル伝送システ
ムの誤)本計測器において、計測しようとする誤多事が
低い場合、従来の4の計測時間毎の誤)数を新しいもの
から順Kn個記憶しておき、誤り計数終了毎にそれらを
加算した結果から誤多事を判定することにょ)、誤り5
4が短時間で変化してもその変化した誤多事をよ)早く
(従来の4の時間毎に)判定することができる効果があ
る。As explained above, (1) the present invention is capable of detecting errors in a digital transmission system when the number of errors to be measured is low in this measuring instrument, the number of errors per measurement time (4) in order from the newest to Kn. Error 5 is determined by memorizing the error count and adding it up each time the error count is completed.
Even if 4 changes in a short period of time, the resulting error can be determined quickly (compared to the conventional 4 time interval).
第1図は本発明による誤多事計測器の一実施例を示ナブ
ロック図、第2図は従来の誤多事計測器の一例を示すブ
ロック図である。
1・・・嗜誤り計数回路、2目・・計数時間設定回路、
3・・・・誤)記憶回路、4・・・・加算回路、5・・
・・誤多事判定回路。FIG. 1 is a block diagram showing an embodiment of an error measuring device according to the present invention, and FIG. 2 is a block diagram showing an example of a conventional error measuring device. 1: Miscellaneous error counting circuit, 2nd eye: counting time setting circuit,
3... Incorrect) Memory circuit, 4... Addition circuit, 5...
...Error detection circuit.
Claims (1)
号を計数する誤り計数回路と、この誤り計数回路に初期
設定信号を供給する計数時間設定回路と、この計数時間
設定回路から記憶命令を受け前記誤り計数回路からの誤
り数を記憶する誤り記憶回路と、この誤り記憶回路の出
力を加算する加算回路と、この加算回路によつて得られ
た加算結果に基いて判定結果を得る誤り率判定回路とを
備え、一定間隔に区切られた各計数時間内に発生した誤
りを計数してそれらを順番に記憶しておき、誤りの計数
終了毎に新しいものから順に一定個数の誤り数を加算し
た結果から誤り率を判定することで、誤り率が短時間に
変化してもその変化した誤り率をより早く判定し得るよ
うにしたことを特徴とする誤り率計測器。In error rate measurement of a digital transmission system, there is an error counting circuit that counts error signals, a counting time setting circuit that supplies an initial setting signal to this error counting circuit, and an error counting circuit that receives a storage command from this counting time setting circuit. an error storage circuit that stores the number of errors from the error storage circuit; an addition circuit that adds the outputs of the error storage circuit; and an error rate determination circuit that obtains a determination result based on the addition result obtained by the addition circuit. , the errors that occur within each counting time divided at regular intervals are counted and stored in order, and each time the counting of errors is completed, the error rate is calculated from the result of adding a certain number of errors in order from the newest one. An error rate measuring device characterized in that by determining the error rate, even if the error rate changes in a short time, the changed error rate can be determined more quickly.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26983687A JPH01112833A (en) | 1987-10-26 | 1987-10-26 | Error rate measuring instrument |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP26983687A JPH01112833A (en) | 1987-10-26 | 1987-10-26 | Error rate measuring instrument |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01112833A true JPH01112833A (en) | 1989-05-01 |
Family
ID=17477859
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP26983687A Pending JPH01112833A (en) | 1987-10-26 | 1987-10-26 | Error rate measuring instrument |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01112833A (en) |
-
1987
- 1987-10-26 JP JP26983687A patent/JPH01112833A/en active Pending
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