JPH01112747A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To assure the dielectric isolation of an insulating film into a flat one without unevenness whatever the distances are between mutual elements, between mutual diffusion layers, and between any element and any diffusion layer by providing a selective oxidation/separation region between mutual trench separation regions. CONSTITUTION:When only trench isolation is insufficient to separate one element from another, one diffusion layer from another, and any element from any diffusion layer, an optimum trench isolation region 2 adjacent to the elements 4, 5, 6 or the diffusion layer 8 is provided, and a selective oxidation and isolation region 3 is provided in a region where no trench region is existent, for formation of an isolation region. There is assured no bad surface having any unevenness and any stepped part whatever such a distance is, for example the distance is insufficiently buried permitting the occurrence of any recess part or it is buried in excess permitting the occurrence of any projecting part. Furthermore, there is no fear of any broken line being produced or of any cavity from being formed in a metal layer or an insulating film.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device having a trench portion Wl region and a selective oxidation portion region in the same half-quad substrate.
This invention relates to a structure in which a selective oxidation limited region is provided between two fltfIIT regions.

[Summary of the invention]

In a semiconductor integrated circuit device having both trench isolation and selective oxidation isolation in the same semiconductor substrate, the present invention provides a trench isolation area adjacent to the element when there is too much distance between elements for trench isolation alone. It is characterized in that a selective isolation region is provided between the trench isolation regions 1jt and tv.

[Conventional technology]

The integration and miniaturization of semiconductor integrated circuits are progressing year by year, and the currently produced products are IM-DRAs with a 1.2 μm rule.
M or 256K-S RAM.

The one that is currently being developed and is starting to consider commercialization is 0.
．． 8μm rule 4M-D RAM and lM-
It is 3RAM. Currently, development is being considered for 0
．． 18 M-D RAM and 41-1- with 5μm rule
It is SRAM.

The trench isolation method has started to be used in some cases starting from the 0.8 μm rule, but it is actually used for the 0.5 μm rule.
This is probably due to the rules. This is because, as miniaturization progresses, the bird's beak of LOGO3 and the narrow channel effect caused by it become a problem, and trench isolation is indispensable for isolation with a fine width.

However, although the trench method is useful for device isolation, LOCO
8 methods are used, both methods are mitsu and kusu.

FIGS. 2 and 3 show schematic cross-sectional views of the conventional method, and the conventional method will be described below.

As shown in FIG. 2, 21 is a P-type Si single crystal substrate, 22 is an insulating film, 23 is a gate oxide film, 24 is a polycrystalline silicon layer, 25 is a silicide layer, 2G is an oxide film, 2
7 is an N+ diffusion layer.

As shown in the figure, if the spacing between elements or between diffusion layers is sufficiently narrow, trench isolane-1
7 Even when separated alone, when filling a trench with an insulating chain, it can be filled without becoming too convex or concave.

As shown in FIG. 3, 31 is a ■) type Si single crystal silicon substrate, 32 is an insulating film, 33 is a gate oxide film, and 34 is a
35 is a silicide layer, 36 is an oxide film, and 37 is an N+ diffusion layer.

As shown in the figure, if the spacing between elements or between diffusion layers is too wide, especially if the trenches are filled with an insulating film that matches the trench with the minimum spacing, This creates a concave portion, resulting in a poor step shape, which can cause wire breakage and the creation of cavities. Furthermore, if an attempt is made to fill in the insulating film in accordance with the wide spacing, the trench portions with the narrow spacing will become protrusions, and the shape of the step will also become poor.

[Problem that the invention seeks to solve]

The object of the present invention is to provide a technique for separating insulating films that are flat and free from irregularities, regardless of the spacing between elements, between diffusion layers, and between elements and diffusion layers.

[Means for solving problems]

The means of the present invention provides trench isolation regions that are most suitable adjacent to the elements or diffusion layers when the distances between elements, diffusion layers, and diffusion layers are too great for trench isolation alone. In this method, an isolation region is formed by creating a selective oxidation isolation region in the remaining region in between.

〔Example〕

FIG. 1 shows a schematic diagram of a cross-sectional structure obtained by the method of the present invention, and the present invention will be explained below.

As shown in FIG. 1, 1 is a P-type Si single crystal substrate,
2 is an insulating film, 3 is an oxide film, 4 is a gate oxide film, 5 is a polycrystalline silicon layer, 6 is a silicide layer, 7 is an oxide film, and 8 is an N+ diffusion layer.

〔Effect of the invention〕

As described above, when the method of the present invention is used, an element and an element,
The spacing between the diffusion layers and the element and the diffusion layer is not the minimum spacing, and regardless of the spacing, it may not be able to fill in completely and create a concave portion, or it may be too deep to cause a convex portion, resulting in unevenness and worsening the step shape. There isn't. Since the surface is flattened by this, it is possible to provide a highly reliable integrated circuit device without the risk of wire breakage or cavities in the gold l1iI layer or insulating film.

[Brief explanation of the drawing]

FIG. 1 is a schematic cross-sectional view of a semiconductor integrated circuit device manufactured by the method of the present invention. FIGS. 2 and 3 are schematic cross-sectional views of a semiconductor integrated circuit device manufactured by a conventional method. Applicant: Seiko Epun Co., Ltd.

Claims (1)

[Scope of Claims] 1) In a semiconductor integrated circuit device having a trench isolation region and a selective oxidation isolation region in the same semiconductor substrate, the selective oxidation isolation region is provided between the trench isolation region and the adjacent trench isolation region. A semiconductor integrated circuit device characterized by being installed. 2) The semiconductor integrated circuit device according to claim 1, wherein the selective oxidation isolation regions have side surfaces in contact with at least one of the trench isolation regions adjacent to each other.