JPH01112597A - Electronic equipment with recording function - Google Patents

Abstract

PURPOSE:To annunciate the recording start time of voice data by starting the storage operation of the voice data in a semiconductor memory by information sent from an address section after the production of a confirming tone by a confirming tone generation signal output means through the operation of a recording switch. CONSTITUTION:The time information of an electronic clock is displayed on a liquid crystal display section 5. In operating a display changeover switch, an alarm time is displayed on the display section 5 by the signal of a one-shot multivibrator circuit 8. In the alarm mode, in operating the recording switch, a one-shot multivibrator circuit 9 is operated and a buzzer tone signal generating circuit 29 is operated by a switch control section 12 and a speaker 25 is sounded. Moreover, the address information is outputted from the address section 16 and an I/O changeover circuit 22 is operated as an input circuit and a voice from a microphone 25 is coded by an encoding circuit 18 and stored in a semi conductor memory. Thus, the external voice is recorded and the recording start time is annunciated.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an electronic device with a recording function that can record audio.

2. Description of the Related Art Recently, electronic devices have become more and more multi-functional, and for example, some electronic watches are equipped with an alarm function, a timer function, and the like. For example, the alarm function is used to notify the time by sounding a single tone of a predetermined frequency or a melody sound of a predetermined song title when the alarm time arrives. However, alarm sounds can only produce melodic sounds, which are determined by the manufacturer, and not only do they have the disadvantage of not meeting the user's tastes or getting tired of them quickly, but also To intuitively understand what the sound means, in other words, what the alarm time was set for.
＜The user memorizes the meaning of the alarm time in advance,
This caused the inconvenience of having to make a distinction.

This invention was made in view of the above circumstances, and its purpose is to be able to easily record a desired sound from the outside, and also to be able to listen to the recorded content as a notification sound for an alarm time, for example. An object of the present invention is to provide an electronic device with a recording function, which can also clearly know the time point at which recording starts by notifying the start of recording at the time of starting recording. This will be explained in detail based on the following. FIG. 1 is a circuit diagram of an electronic clock that notifies alarm time by sound. In the figure, reference numeral 1 denotes an oscillator circuit that generates a reference frequency signal, and the reference frequency signal is sent to a frequency divider circuit 2 where it is frequency-divided into a signal with a period of 1 second and is then applied to a counter circuit 3. This counting circuit 3 calculates 1 minute and 1 minute as time information based on the 1 second cycle signal.
time, PM (afternoon) information that distinguishes between morning and afternoon, and day of the week information.The time information counted by the clock counting circuit 3 is sent to the liquid crystal display via the display control circuit 4. The clock information sent from the counting circuit 3 is sent to the coincidence circuit 7 to which the alarm time information is supplied from the alarm time setting circuit 6.
It is also output for . This alarm time setting circuit 6ζ
This set and stored alarm time information is given to the liquid crystal display section 5 via the display control circuit 4. When the above-mentioned -number circuit 7 detects a match between the clock information from the counting circuit 3 and the alarm time information from the alarm time setting circuit 6, it sends out an alarm signal AL to control display switching to the display control circuit 4. Give as a signal.

On the other hand, in the figure, reference numeral S1 is a display switching switch, and the operation signal of this switch S1 (is given to the one-shot circuit 8, causing the one-shot circuit 8 to output one pulse signal. In addition, the reference numeral S2 is This is a recording switch, and the operation signal of this switch S2 is sent to a one-shot circuit 9.
, causing the one-shot circuit 9 to output one (1) signal. The noggle signal from the one-shot circuit 8 is applied to the T input terminal of the binary 7-rip 70-tube 10, and inverts its output state.

The Q and Q surveying force signals of the 7-puff field 10 are respectively given to the display control circuit 4 as display switching control signals. These 7 tabs 70 tabs 10 are used in a normal time display mode in which the time information of the clock counting circuit 3 is displayed on the liquid crystal display section 5 when the Q survey force signal is being sent out, and in the
When the survey force signal is being sent out, an alarm time display mode is selectively set in which the alarm time of the alarm time setting circuit 6 is displayed on the liquid crystal display device 5I. When the flip 70 knob 10 is in the alarm time display mode, one pulse signal from the one shot circuit 9 is sent to the switch via the AND circuit 11 to which the Q survey force signal of the 71J knob 70 knob 10 is applied. It is sent to the control unit 12.

This switch control unit 12, which will be described in detail later, controls the control signal f1 that is output when one pulse signal from the AND circuit 11 is given, and this control (approximately 4 seconds after outputting No. 1 f1). The switch controller 12 is configured to send out the control signal f2 that is output after seconds have elapsed, and the elapsed time information from when the control signal f1 is output until the control signal f2 is output. The elapsed time information is supplied to the liquid crystal display unit 5 via the display control circuit 4. On the other hand, the nosal signal output from the AND circuit 11 is also supplied to the down counter 13, which receives this pulse signal. At this time, the down counter 13 is preset to 18" in decimal. The @8" preset to the down counter 13 is subtracted by 1 each time the lHz signal output from the AND circuit 14 is given. One input terminal of the AND circuit 14 receives a 1Hz signal, and the other input terminal i receives a control signal f2 output from the switch control section 12. The down counter 13 is given as a gate control signal.
When seconds have elapsed, Boroi No. a is sent out and given to the switch control section 12. The control signal f2 output from the switch control unit 12 is no longer output when the pollo signal is applied. The contents of the down counter 13 are as follows:
As will be described later, it indicates the remaining recording capacity that can be recorded, and the output number output from the down counter 13 is as follows.
The signal is supplied to the liquid crystal display section 5 via the display control circuit 4.

In addition, a control signal f2 output from the switch control unit 12
is sent to address IM16 via OR circuit 15,
While outputting address information from the address section 16,
It is sent as an operation command signal to the A/D (digital/analog) conversion circuit 17 and the encoding circuit 18, and furthermore, a read command /1! is sent to the semiconductor memory 19. f is sent as a loading command signal. The A/D conversion circuit 17 converts an analog audio signal into a digital audio signal,
The digital audio signal obtained here is provided to an encoding circuit 18ζ. This encoding circuit 18 encodes a digital audio signal into pitch, volume, etc.
The encoded signal here is applied to the input side terminal IN of the semiconductor memory 190. This semiconductor memory 19 is used as a solid-state recording means using semiconductor memory,
For example, it is composed of a shift register, )l, AM (random access memory), etc., and is addressed by an address counter (not shown) included in the address section 16. That is, by receiving the control signal f2, the write operation is performed in synchronization with the predetermined frequency signal j output from the frequency dividing circuit 2 upon receiving the write designation.

The semiconductor memory 19 used is one that operates with the signal f and has a recording capacity of approximately 8 seconds.

On the other hand, the alarm signal AL output from the matching circuit 7 is
The signal is sent to the address section 16 via the OR circuit 15, causing the address section 16 to output address information, and is also sent to the encoding circuit 20 and the audio signal synthesis circuit 21 as an operation command signal. Therefore, the semiconductor memory 19 has the address section 1
6, and the voices stored at the specified address are read out from the output terminal 0υT in the order in which they were input. This semiconductor memory 1
The information read from the encoder 9 is provided to an audio signal synthesis circuit 21 via an encoding circuit 20 which performs encoding in the opposite manner to that of the encoding circuit 18 described above. This audio signal synthesis circuit 21 synthesizes and converts the signal encoded by the encoding circuit 20 and the predetermined frequency signal f from the frequency dividing circuit 2 into an audio signal, and the audio signal obtained here is is l10(
input/output) switching circuit 22. A control signal f2 is given to this I10 switching circuit 22 as an audio input command signal, and when this control signal f2 is output, the I10 switching circuit 22 operates as an input circuit, and the control signal f2 is It is configured to operate as an output circuit when no output is being generated.

This I10 switching circuit 22 is connected to a microphone-required speaker 25 by sequentially controlling an amplifier 23 and a gate circuit 24. A control signal f1 is applied to this gate circuit 24 via an inverter 26 as a gate release signal. Thus, the sound input from the microphone 25 passes through the gate circuit 24 and the amplifier 23 in sequence, is sent out from the I10 switching circuit 22, and is applied to the A/D conversion circuit 17.

Furthermore, the audio signal amplified by the amplifier 23 is
After the analog quantity given to the D conversion circuit 27 is converted into a digital quantity, it is displayed on the liquid crystal display section 5 via the display control circuit 4.
is supplied to An alarm signal AL is given to this A/D conversion circuit 27 as an operation command signal.

On the other hand, the control signals f1 and f2 are given to the display control circuit 4 as display switching signals. Further, the control signal f1 is given to the buzzer sound signal generation circuit 29 as an operation command (No. 8), and is also given to the gate circuit 30 as a gate answer code. This circuit outputs a buzzer sound signal, and the buzzer sound signal generated from this circuit is given to the speaker 25 via the gate circuit 30.

FIG. 2 shows a circuit configuration diagram of the switch control section 120. One pulse signal outputted from the AND circuit 11 is applied to the set side input terminal S of the R8 type 7 lip 70 tube to set it. By setting this 7-lip 70-tube 31, the Q height measurement force signal is sent out from the switch control section 12 as the control signal f1, and this Q
The height measurement force signal is sent as a gate control signal to an AND circuit 32 to which a 2 Hz signal is applied. The 2Hz signal output from this AND circuit 32 is sent to the octal counter 3.
3 and counted. The output contents of this counter 33 are sent to the display control circuit 4. Also, when the octal counter 33 reaches the count value "'8", that is, when 4 seconds have passed since the start of the timekeeping operation, a carry signal is output and applied to the reset side input terminal R of the ARITUB 70 and TUB 31. , let this reset. Further, the control signal f1 and the carry signal from the down counter 13 are applied to the T input terminal of the binary flip-flop 35 via the OR circuit 34, and the output state thereof is inverted.

The Q height measurement force signal of the 7 lip-flop 35 is sent to an AND circuit 36 to which the Q height measurement force signal of the 7 lip-flop 31 is applied, and the AND circuit 36 sends out a control signal r2.

FIG. 3 is a circuit diagram of the display control circuit 40 and a configuration diagram of the liquid crystal display section 5. In the display control circuit 4, the PM information obtained by the counting circuit 3 is sent to an AND circuit 37, and the day of the week information is sent to an AND circuit 38, respectively. Each of these AND circuits 37° and 38 has a Q of 7, 70, and 10.
A height measurement force signal is provided as a gate control signal. In addition, the output content A of the down counter 13 is determined by the AND circuit 39.
Additionally, the output contents of the counter 33 of the switch control section 12 are sent to an AND circuit 40, and the output contents of the A/D conversion circuit 27 are sent to an AND circuit 41, respectively. The AND circuit 39 receives the Q height measurement force signal of the flip 70 knob 10 and the control (d-j) f2 as gate control signals, and the AND circuit 40 receives the Q height measurement force signal of the 7 flip 70 knob 10. and control signal f1 are respectively given as gate control signals, and furthermore, the AND circuit 41 receives an alarm signal AL.
is given as a gate control signal. The output information of these AND circuits 39 to 41 is sent out from the display control circuit 4 via an OR circuit 42. Further, the 1 o'clock information obtained by the counting circuit 3 is sent to the AND circuit 43, and the 1 o'clock information set to the alarm time setting circuit 6 is sent to the AND circuit 43.
4 will be sent to each. The AND circuit 43 receives the Q height measurement force signal from the flip 70 and the knob 10, and the AND circuit 44
The Q height measurement force signals of the flip 70 and the knob 10 are respectively given as gate control numbers 64. The output information of each of these AND circuits 43 and 44 is sent out from the display control circuit 4 via an OR circuit 45. Furthermore, the minute 1 information obtained by the counter counting circuit 3 is sent to an AND circuit 46, and the 1 minute-1 information set in the alarm time setting circuit 6 is sent to an AND circuit 47. is a 7-lip 70-tub 10 Q height measurement force signal, and an AND circuit 47
The Q measurement power (symbols) of the seven lip-flops 10 are respectively given as gate control signals.The output information of these AND circuits 46 and 47 is sent from the display control circuit 4 via the OR circuit 48.

On the other hand, the liquid crystal display section 5 includes a first digital display section 49 that digitally displays the hour unit as the time unit, and a first digital display section 49 that digitally displays the minute unit as the time unit.
51 of two digital display sections 50. This analog display section 51 is divided into 4 (out of each dot display body)
In the figure, above the 7th dot display from the left end are the corresponding day of the week designation symbols r8 (day 114) J, rM (Monday), as shown in Figure 1.
, r'r (Tuesday, M-Sun),""W(Wednesday),""rT(Thursday),""rF(Friday)," and "rs (Saturday)" are fixedly displayed by means such as printing. As shown in Figure 1, above the dot display located at the right end (eighth position) in the figure, there is a symbol indicating the afternoon time zone.
PM", and below it is a symbol 1' indicating the start of recording.
- ST A B and T J are fixedly displayed by means such as printing. For convenience of explanation, the analog display section 51 is assumed to be the analog display section 51a of WJl including the dot display bodies located at the seventh position from t7ij on the left in the figure.
In the figure, the dot display located at the right end is the second analog display section 51b.

Further, the output information of the AND circuit 37 is given to the second analog display section 51b, and the dot display is driven for display. Further, the output information of the AND circuit 38 is
It is applied to the analog display section 51b of the dot display section 51b, and any one of the dot display bodies included therein is selectively driven to light up. Further, the output information of the OR circuit 42 is given to the analog display section 51 that constitutes the first and second analog display sections 51a and 51b, and the dot display included therein is shown from the left end in the figure. The lighting is driven sequentially and cumulatively. Furthermore, the output information of the OR circuit 45 is given to a first digital display section 49 and driven to be displayed digitally. Further, the output information of the OR circuit 48 is provided to the second digital display iso and displayed digitally.

Next, regarding the operation of the electronic timepiece configured as described above, the timing chart shown in FIG. 4, and FIGS.
2+ will be explained with reference to the display state diagrams shown in FIGS. 6(1) and (2). First, when a 1" signal is output from the Q detection power terminal of the binary 7 lip 7 stomach tube IO, the AND circuits 37.3B and 4 are output in the display control circuit 4.
3.46 are respectively de-gated. Therefore, the PM information, day of the week information, hourly information, and minutely information obtained by the counting circuit 3 are sent out from the display control circuit 4 via the corresponding AND circuit and given to the liquid crystal display section 5. As a result, the liquid crystal display section 5 displays the current time and day of the week information. That is, for example, as shown in FIG.
"30" in minutes is displayed on the second digital display section 50 to clearly indicate the current time "10:30," and each dot display on the first analog display section 51a Among them, the fourth dot display counting from the left end in the figure is driven to light up to clearly indicate "Wednesday 14th", and furthermore, the dot display on the second analog display section 51b is driven to light up. the first and second digital display sections 4;
It is clearly shown that the time displayed at 9.50 belongs to the afternoon time zone.

Next, when the display furnace # switch 81 is operated, a pulse signal is output from the one-shot circuit 8, and the output state of the binary flip-flop 10 is inverted. As a result, the @1# signal is output from the Q detection power terminal of the pinary flip flip flop 10. Therefore, in the display control circuit 4, gates of AND times 1!2544.47 are released, so that the AND circuit 44 corresponding to the hourly unit information and minute unit information of the alarm time set in the alarm expiry setting circuit 6 Sent via .47.

Therefore, the alarm time of "12:35" is displayed on the liquid crystal display section 5, for example, as shown in FIG. 5(2)1.

In the alarm mode in which this alarm time is displayed, when the recording switch S2 is operated, the operation signal of this switch S2 is given to the one-shot circuit 9, and as shown in FIG. circuit 9 to 1
output a pulse signal.

Therefore, this one pulse signal is output from the AND circuit 11 whose gate is released by the Q light output signal of the binary flip-flop 1o.
31 is preset to @8''. Further, one pulse signal outputted from the AND circuit 11 is given to the switch control section 12.

In this switch control section 12, a TLS type flip-flop 31 is operated as shown in FIG.
A signal of "1" is output from the Q detection force terminal of the 0 knob 35. The Q light output signal of the Aritz flop 31 is sent out from the switch control section 12 as a control signal f1, and also releases the gate of the AND circuit 32. Since this AND circuit 32 is given a 2 Hz output as shown in FIG.
As shown in Figure (5) 1, a 2Hz signal is output, and 8
It is counted by the tracing counter 33. And octal counter 3
The contents counted in step 3 are sent to the display control circuit 4.

This display control circuit 4 includes a control signal f1 and a binary 7
Since the Q light output signal of the lip 70 tube 10 is provided, the AND circuit 40 is gated off. For this reason, 8
The contents of the associate counter 33 are an AND circuit 40 and an OR circuit 42
The signal is sent from the display control circuit 4 via the analog display section 51 and provided to the analog display section 51. Therefore, in the liquid crystal display section 5, the alarm time "12:35" is displayed on the digital display section 49.50, and each dot display on the analog display section 51 is displayed every 0.5 seconds from the left end. Then, as shown in FIG. 6 (1), after 4 seconds, all the dot indicators are lit and a fixed display [5TAR, the dot indicators 51b corresponding to TJ are lit, ! It now indicates the start of the ψ sound.

On the other hand, as the control signal f1 is output from the switch control section 12, the buzzer sound signal generation circuit 29 operates,
Gate 30 is de-gated.

Therefore, a buzzer sound signal is output from the buzzer sound signal generation path 29, and is applied to the speaker 25 via the gate 3Q, whereby a buzzer sound of a predetermined frequency is generated. This buzzer sound is generated by the control 4j from the switch control section 12.
It is sounded while the j number fl is being output.

Therefore, in the switch control section 12, the AND circuit 3
2 to 4 (5), when eight pulse signals are output, the count value of the octal counter 33 becomes "8", and from the octal counter 33, the count value of the octal counter 33 becomes "8". A carry signal is now output as shown in . The output of this carry signal resets the 7-lip flop 31, and its output state is inverted, as shown in FIG.
As shown in FIG. 8, a signal of "O#" is output from the Q height measurement force terminal, and a signal of "1#" is output from the Q height measurement force terminal. Then, Q (l
From the id output terminal, as shown in Figure 4 (9), @1
” is output, the AND circuit 36 outputs the fourth signal.
An output as shown in FIG. a1 is obtained, and the switch control unit 12
is sent out as a control signal f2.

That is, this control signal f2 is output after 4 seconds have elapsed since the recording switch S2 was operated, and the recording iJ enable state is achieved by outputting this control signal f2. In this way, for 4 seconds after operating the recording switch S2, a buzzer sound is emitted as a confirmation sound to notify the start of recording, and the elapsed time until 4 seconds have elapsed since the recording switch S2 was operated. The analog display unit 51 displays the level of time every 0.5 seconds.

When the control signal f2 is output, the semiconductor memory 19 receives write designation and the address section 16
Address information is output from the I10 switching circuit 2.
2 operates as an input circuit, and the A/D conversion circuit 17 and the encoding circuit 18 become operable. In this state, play music that suits the user's preference from a radio receiver or the like into the microphone 25, or say the word that the alarm time means, such as "meeting", "meeting", "meeting", etc., by voice. pronounce. Then, the audio signal sensed by the microphone 25 is converted into a digital quantity by the A/D conversion circuit 17, further encoded by the encoding circuit 18, and provided to the semiconductor memory 19. In this semiconductor memory 19, the specified address is sequentially converted according to the output t# information from address [16, and audio information is written to this specified address.
Predetermined music, sounds such as "meeting" and "meeting" are recorded.

That is, the gate of the AND circuit 14 is released by outputting the control signal f2. This AND circuit 14 has a
) is given a l Hz signal as shown in
When the AND circuit 14 is degated, the AND circuit 14
As shown in FIG. 4, an IHz signal is output. Therefore, 1"8" preset in the down counter 13 is subtracted by 1 each time the IHz signal output from the AND circuit 14 is applied. The output content A of this down counter 13 is sent to the display control oil 1 path 4. This display control circuit 4 has QO1 of binary 7 lip 70 knob 10! Since the I output signal and the control signal f2 are applied, the AND circuit 39 is gated. Therefore, the output content A of the down counter 13 is
9, is sent from the display control circuit 4 via the OR circuit 42 and applied to the analog display section 51. As a result, in the liquid crystal display section 5, the digital display body 49.50 has @
As shown in 61J(2), the alarm time "12:35
In addition, when the output of the down counter 13 is @8'', all eight dot displays on the analog display section 510 are lit, but the fixed displays rPMJ, rsJ , rFJ・・・・・・・・・
・When the dot display corresponding to goes out and the output content A of the down counter 13 becomes ``5'',
As shown in FIG. 6 (2), each dot indicator from the left end to the fifth one in the figure lights up, and the remaining recording capacity of the semiconductor memory 19 is expressed in time as 5 seconds remaining. Something is made clear. In this way, the remaining recordable capacity is optically displayed on the analog display section 51, so that recording can be performed while viewing this display.

When the AND circuit 14 outputs eight pulse signals, the down counter 13 outputs the signal C12 in FIG.
As shown in Figure 1, Borrow<A is output.

This borrow signal is sent to switch control 111S12.

Then, in the switch control section 12, the borrow signal from the down counter 13 inverts the output state of the 7 lip-flop 35 via the OR circuit 34. Therefore, the Q output signals of the 7-lip flop 35 are As shown in Figure (9), it becomes 1 ohm, and along with this, the AND circuit 3
The output signal of 6 is also @0# as shown in FIG. 4aI.

Therefore, the recording will end within 8 seconds from the start of the recording.

Therefore, when the alarm time is reached and the alarm signal AL is output from the matching circuit 7, the alarm signal AL is given to the address section 16 via the OR circuit 15, causing the address section 16 to output address information. The encoding circuit 20 and the audio signal synthesis circuit 21 are each put into an operable state. At this time, since the control signal f2 is not given to the semiconductor memory 19 and the I10 switching circuit 22,
The semiconductor memory 19 receives the reading designation and also receives the I
The 10 switching circuit 22 operates as an output circuit.

In this state, the audio information stored in the semiconductor memory 19 is sequentially read out in accordance with the address designation of the address section 16. The read audio information is encoded by the encoding circuit 20, then sent to the audio signal synthesis circuit 21, where it is converted and synthesized into an audio signal, and then passed through the I10 switching circuit 22 to the amplifier 23. sent to.

The audio signal amplified by this amplifier 23 is transferred to the inverter 2
The signal is sent to the speaker 25 via the gate circuit 24 whose gate is released by the output signal of No. 6, and is emitted as an alarm time notification sound. Note that if the recorded audio information is a predetermined song, the word 4 is pronounced, and if it is a word meant by the alarm time, this word, for example, "meeting" or "meeting" is pronounced.

On the other hand, the alarm signal AL is sent to the A/D via the OR circuit 28.
The conversion circuit 27 is made operable. In this state, the volume signal amplified by the amplifier 23 is converted into digital A/1 by the A/D conversion circuit 27 and sent to the display control circuit 4. Since the -alarm signal AL is applied to the display control circuit 4, the gate of the AND circuit 41 is released.

Therefore, the audio information from the A/D conversion circuit 27 is sent out from the display 1 simple control circuit 4 via the AND circuit 41 and the OR circuit 42, and is given to the analog display section 51. Therefore, the level of the volume of the recorded content produced by each dot display on the analog display section 51 is displayed.

In this way, recording becomes possible 4 seconds after the recording switch S2 is operated. At the same time as the @Kihon sound is sounded to notify the start, the level of the remaining time until the recording starts is displayed. Therefore, the starting point of the flame sound can be known audibly and visually, and recording can be performed effectively without wasting the recordable capacity. Furthermore, since the remaining recording capacity is displayed at a level during recording, it is possible to record while keeping this display clear, eliminating any omissions in the recording, and ensuring reliable recording. Furthermore, when the content of Of is being sounded, its capacity is displayed as a level.

The seventh [4] shows another embodiment of the present invention, and shows another embodiment of the switch control section 12. Components that are the same as the switch control section 12 described above are designated by the same reference numerals, and their explanations will be omitted.

In the figure, reference numeral 53 is an R/S type 7 lip-flop, and its set side input terminal S has a one-shot circuit 9.
One pulse signal from the AND circuit 11 is applied to the AND circuit 11, and the carry signal of the down counter 13 is applied to the reset side input terminal R. Further, one pulse signal outputted from the AND circuit 11 is sent out from the switch control section 52 as a control signal f1. It is sent out as the flip control signal f2.

When the recording switch S2 is operated, the control signal f1 consisting of one pulse is output, so a short buzzer sound is emitted, the flip 70 knob 53 is set, and the control signal f2 is output. will be sent and recording will begin. In this way, when the recording switch S2 is operated,
Recording can be started as soon as the buzzer sound is generated.

In each of the above embodiments, the alarm sound is sounded at a set time, but the present invention is not limited to this, and the alarm sound may be sounded at a specific time on a specific day or at a set time. , when the timer time elapses, the timer notification sound may be emitted, or a time signal may be emitted every hour on the hour.

Further, in each of the above embodiments, the audio information recorded in the semiconductor memory is only sounded as an alarm sound, but the audio information may be arbitrarily read out and emitted by an external operation switch.

Further, in each of the above embodiments, a buzzer sound is generated as a confirmation sound for starting recording at the time of starting recording, but the present invention is not limited to this. For example, the invention is not limited to this. The recording may be started at the end of the song.

As explained in detail above, this invention inputs and records audio from the outside and makes the recorded content sound, so that the user can play music, desired words, etc. that suit the user's taste, for example. This can be heard as a notification sound for the alarm time, and at the same time, the start of recording is announced as a confirmation sound, so you can clearly know when recording starts, and you can avoid wasting the available recording capacity. Therefore, recording can be performed effectively.

[Brief explanation of the drawing]

The drawings show an embodiment of the present invention; FIG. 1 is a circuit configuration diagram of an electronic timepiece, FIG. 2 is a circuit configuration diagram of a switch control section, and FIG. 3 is a configuration of a display control circuit and a liquid crystal display section. figure,
Fourth meat (1) to α4 are timing charts of various signals,
Figure 5 (1), (2), Figure 6 (1). (2) is a diagram showing a display state, and FIG. 7 is a circuit configuration diagram of a switch control section showing another embodiment of the present invention. 12... Switch system i2! Part 1, 17...
...A/D conversion circuit, 18... Encoding circuit, 1
9...Semiconductor memo IJ, 20...Encoding circuit, 21...Audio signal synthesis circuit, 25°...
...Microphone/speaker, 29...
Buzzer sound No. 4g generation circuit, S2... Recording switch. Figure 5 (6th cause amendment procedure oral format) 6゜] 1. Indication of the case Patent Application No. 170677 of 1988 2. Electronic device with a recording function for the name of the invention 3. Person making the amendment Relationship with the case Patent application Address: 2-6-1-4 Nishi-Shinjuku, Shinjuku-ku, Tokyo Date of amendment: October 25, 1985 (departure gate) Contents of amendment: "(1)" on page 29, line 10 of the statement ~(12)J
Delete. that's all

Claims (1)

[Claims] A semiconductor memory that stores externally input audio as encoded audio data, an address section that outputs address information of the semiconductor memory, a recording switch, and confirmation by operating the recording switch. a confirmation sound generation signal output means for outputting a signal for generating a sound; and after the confirmation sound generation signal output means generates the confirmation sound, a control signal is supplied to the address section to cause the address section to output address information. An electronic device with a recording function, comprising: control signal output means for starting a storage operation of the audio data in the semiconductor memory.